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Initial Spartan 7 support. 

Fixes https://github.com/SymbiFlow/prjxray/issues/1803

Updating all based on "Merge pull request #1802 from MidsummerNight/xc7s50"

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
This commit is contained in:
Tim 'mithro' Ansell 2021-12-14 10:06:25 -08:00
parent cd41f08a8a
commit a1a8a03c2f
419 changed files with 2238880 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

506
Info.md
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@ -37,20 +37,18 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Wed 04 Aug 2021 03:32:51 PM UTC (2021-08-04T15:32:51+00:00).
Last updated on Mon Dec 13 15:06:10 UTC 2021 (2021-12-13T15:06:10+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [f7f06896](https://github.com/SymbiFlow/prjxray/commit/f7f06896ad26bb7c94680dc323d4b871eded1f4e).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [3d1a0052](https://github.com/SymbiFlow/prjxray/commit/3d1a00527cf8f406d75f462d6cbb3487f8699668).
Latest commit was;
```
commit f7f06896ad26bb7c94680dc323d4b871eded1f4e
Merge: 6e6bff0b ceb0eadf
Author: Alessandro Comodi <44773360+acomodi@users.noreply.github.com>
Date: Thu Jul 8 14:45:27 2021 +0200
commit 3d1a00527cf8f406d75f462d6cbb3487f8699668
Merge: 60168e9b f3474a26
Author: Steve <steve.bohan.liu@outlook.com>
Date: Mon Dec 13 11:39:52 2021 +0100
Merge pull request #1705 from antmicro/fix-iob-ppips
071-ppips: add LIOB33 and RIOB33 ppips
Merge f3474a2625ec320b4245e174cb9943192f83c121 into 60168e9b7e89956ce8a197f3cfdf6d4bc80926d3
```
@ -59,7 +57,7 @@ Date: Thu Jul 8 14:45:27 2021 +0200
### Settings
Created using following [settings/artix7.sh (sha256: fc677f338196f4cecea5f963feb41c09d281505828d0cde9740f2a4bb305532a)](https://github.com/SymbiFlow/prjxray/blob/f7f06896ad26bb7c94680dc323d4b871eded1f4e/settings/artix7.sh)
Created using following [settings/artix7.sh (sha256: fc677f338196f4cecea5f963feb41c09d281505828d0cde9740f2a4bb305532a)](https://github.com/SymbiFlow/prjxray/blob/3d1a00527cf8f406d75f462d6cbb3487f8699668/settings/artix7.sh)
```shell
#!/bin/bash
# Copyright (C) 2017-2020 The Project X-Ray Authors.
@ -886,7 +884,7 @@ Results have checksums;
### Settings
Created using following [settings/kintex7.sh (sha256: 26dfa36e49b4528298fc43411d654aa647076ce8160f4d8cfe71727594eb3848)](https://github.com/SymbiFlow/prjxray/blob/f7f06896ad26bb7c94680dc323d4b871eded1f4e/settings/kintex7.sh)
Created using following [settings/kintex7.sh (sha256: 26dfa36e49b4528298fc43411d654aa647076ce8160f4d8cfe71727594eb3848)](https://github.com/SymbiFlow/prjxray/blob/3d1a00527cf8f406d75f462d6cbb3487f8699668/settings/kintex7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
@ -1317,11 +1315,495 @@ Results have checksums;
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv676-3/part.yaml`](./kintex7/xc7k70tfbv676-3/part.yaml)
## Database for [spartan7](spartan7/)
### Settings
Created using following [settings/spartan7.sh (sha256: e4e716c51468b214347a8dd026a137f81a56295441095d6dfcd71973d4ca812d)](https://github.com/SymbiFlow/prjxray/blob/3d1a00527cf8f406d75f462d6cbb3487f8699668/settings/spartan7.sh)
```shell
#!/bin/bash
# Copyright (C) 2017-2021 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
export XRAY_DATABASE="spartan7"
export XRAY_PART="xc7s50fgga484-1"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# All CLB's in part, all BRAM's in part, all DSP's in part.
# tcl queries IOB => don't bother adding
export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
export XRAY_EXCLUDE_ROI_TILEGRID=""
# This is used by fuzzers/005-tilegrid/generate_full.py
# (special handling for frame addresses of certain IOIs -- see the script for details).
# This needs to be changed for any new device!
# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST.
export XRAY_IOI3_TILES="LIOI3_X0Y9 RIOI3_X43Y9"
# These settings must remain in sync
export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59 IOB_X0Y100:IOB_X0Y149"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="10"
export XRAY_ROI_GRID_X2="58"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="0"
export XRAY_ROI_GRID_Y2="51"
# clock pin
export XRAY_PIN_00="F14"
# data pins
export XRAY_PIN_01="F13"
export XRAY_PIN_02="F12"
export XRAY_PIN_03="F11"
export XRAY_PIN_04="G11"
export XRAY_PIN_05="G10"
export XRAY_PIN_06="G13"
source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh
eval $(python3 ${XRAY_UTILS_DIR}/create_environment.py)
ENV_RET=$?
if [[ $ENV_RET != 0 ]] ; then
return $ENV_RET
fi
eval $env
```
### [Results](spartan7/)
Results have checksums;
* [`08718436be0d58ded3bc8d8d19343980250ce0512b2ab4efd959b51b4da9f4c0 ./spartan7/element_counts.csv`](./spartan7/element_counts.csv)
* [`4f942a606758e8036731a6b535d9c6123eb2df0f72d5a6b14ed56eda9f7bca6a ./spartan7/mapping/devices.yaml`](./spartan7/mapping/devices.yaml)
* [`f9b2be0eda3e8af68a2fc10034eaa6efb9c3974b20d72c3b5a9ee757c4887c21 ./spartan7/mapping/parts.yaml`](./spartan7/mapping/parts.yaml)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./spartan7/mask_bram_l.block_ram.db`](./spartan7/mask_bram_l.block_ram.db)
* [`3658831678f3df2149d588f19bfdc2a59ad9ac9293351daf7f4af52255facc88 ./spartan7/mask_bram_l.db`](./spartan7/mask_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_bram_l.origin_info.db`](./spartan7/mask_bram_l.origin_info.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./spartan7/mask_bram_r.block_ram.db`](./spartan7/mask_bram_r.block_ram.db)
* [`3658831678f3df2149d588f19bfdc2a59ad9ac9293351daf7f4af52255facc88 ./spartan7/mask_bram_r.db`](./spartan7/mask_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_bram_r.origin_info.db`](./spartan7/mask_bram_r.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./spartan7/mask_clbll_l.db`](./spartan7/mask_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_clbll_l.origin_info.db`](./spartan7/mask_clbll_l.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./spartan7/mask_clbll_r.db`](./spartan7/mask_clbll_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_clbll_r.origin_info.db`](./spartan7/mask_clbll_r.origin_info.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./spartan7/mask_clblm_l.db`](./spartan7/mask_clblm_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_clblm_l.origin_info.db`](./spartan7/mask_clblm_l.origin_info.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./spartan7/mask_clblm_r.db`](./spartan7/mask_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_clblm_r.origin_info.db`](./spartan7/mask_clblm_r.origin_info.db)
* [`a01322f2b03d6e7a29dd225905afe60347f157b8cd48a0e3ad0299a8776774cf ./spartan7/mask_clk_bufg_bot_r.db`](./spartan7/mask_clk_bufg_bot_r.db)
* [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea ./spartan7/mask_clk_bufg_rebuf.db`](./spartan7/mask_clk_bufg_rebuf.db)
* [`a01322f2b03d6e7a29dd225905afe60347f157b8cd48a0e3ad0299a8776774cf ./spartan7/mask_clk_bufg_top_r.db`](./spartan7/mask_clk_bufg_top_r.db)
* [`492d7880ed2be3ce5479b397a88e012ea0c98e2ba667fa02d1d57acbdf10208f ./spartan7/mask_clk_hrow_bot_r.db`](./spartan7/mask_clk_hrow_bot_r.db)
* [`8065dd1943464a57b58323eb09fa9d34148e09a3cd0d7d750dc31166ac25164a ./spartan7/mask_clk_hrow_top_r.db`](./spartan7/mask_clk_hrow_top_r.db)
* [`a2feae6086637d13e25411af10ed264effe9ffcd4fed213d5d5282bac3633a58 ./spartan7/mask_dsp_l.db`](./spartan7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_dsp_l.origin_info.db`](./spartan7/mask_dsp_l.origin_info.db)
* [`f6ba6207f09e5cc8d0e271be73d24ad8005764a3d2c852233a8fcdb41d3b991d ./spartan7/mask_dsp_r.db`](./spartan7/mask_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_dsp_r.origin_info.db`](./spartan7/mask_dsp_r.origin_info.db)
* [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404 ./spartan7/mask_hclk_cmt.db`](./spartan7/mask_hclk_cmt.db)
* [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404 ./spartan7/mask_hclk_cmt_l.db`](./spartan7/mask_hclk_cmt_l.db)
* [`d0914443ac28056e840aee431bd51933a7cdc6504eefb052113d7e33e8b08e83 ./spartan7/mask_hclk_ioi.db`](./spartan7/mask_hclk_ioi.db)
* [`49f54d634cddc4d58df9b8a0c371364088c73c1eeaaf87b80c871430aae66077 ./spartan7/mask_hclk_ioi3.db`](./spartan7/mask_hclk_ioi3.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./spartan7/mask_hclk_l.db`](./spartan7/mask_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_hclk_l.origin_info.db`](./spartan7/mask_hclk_l.origin_info.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./spartan7/mask_hclk_r.db`](./spartan7/mask_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/mask_hclk_r.origin_info.db`](./spartan7/mask_hclk_r.origin_info.db)
* [`b1e6417cccea25799f1e5bf4b86b7a42fa1c46cb1351da93e380a519691e9fbd ./spartan7/mask_liob33.db`](./spartan7/mask_liob33.db)
* [`ee61e489eb229833788ea3b511e987b483d331e19fbde33182b9b3ffc25738e7 ./spartan7/mask_lioi3.db`](./spartan7/mask_lioi3.db)
* [`ee61e489eb229833788ea3b511e987b483d331e19fbde33182b9b3ffc25738e7 ./spartan7/mask_lioi3_tbytesrc.db`](./spartan7/mask_lioi3_tbytesrc.db)
* [`ee61e489eb229833788ea3b511e987b483d331e19fbde33182b9b3ffc25738e7 ./spartan7/mask_lioi3_tbyteterm.db`](./spartan7/mask_lioi3_tbyteterm.db)
* [`b1e6417cccea25799f1e5bf4b86b7a42fa1c46cb1351da93e380a519691e9fbd ./spartan7/mask_riob33.db`](./spartan7/mask_riob33.db)
* [`ee61e489eb229833788ea3b511e987b483d331e19fbde33182b9b3ffc25738e7 ./spartan7/mask_rioi3.db`](./spartan7/mask_rioi3.db)
* [`ee61e489eb229833788ea3b511e987b483d331e19fbde33182b9b3ffc25738e7 ./spartan7/mask_rioi3_tbytesrc.db`](./spartan7/mask_rioi3_tbytesrc.db)
* [`ee61e489eb229833788ea3b511e987b483d331e19fbde33182b9b3ffc25738e7 ./spartan7/mask_rioi3_tbyteterm.db`](./spartan7/mask_rioi3_tbyteterm.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./spartan7/ppips_bram_int_interface_l.db`](./spartan7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_bram_int_interface_l.origin_info.db`](./spartan7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./spartan7/ppips_bram_int_interface_r.db`](./spartan7/ppips_bram_int_interface_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_bram_int_interface_r.origin_info.db`](./spartan7/ppips_bram_int_interface_r.origin_info.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./spartan7/ppips_bram_l.db`](./spartan7/ppips_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_bram_l.origin_info.db`](./spartan7/ppips_bram_l.origin_info.db)
* [`e58acdfa3cc740d2346dcb5d3a4c13434d459ebdc2ceb655dcb65fd631da4e4d ./spartan7/ppips_bram_r.db`](./spartan7/ppips_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_bram_r.origin_info.db`](./spartan7/ppips_bram_r.origin_info.db)
* [`be58cd551e870914cff515baabe383dc2655f34f5332c395ceb20ca25414dd63 ./spartan7/ppips_brkh_int.db`](./spartan7/ppips_brkh_int.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./spartan7/ppips_clbll_l.db`](./spartan7/ppips_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_clbll_l.origin_info.db`](./spartan7/ppips_clbll_l.origin_info.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./spartan7/ppips_clbll_r.db`](./spartan7/ppips_clbll_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_clbll_r.origin_info.db`](./spartan7/ppips_clbll_r.origin_info.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./spartan7/ppips_clblm_l.db`](./spartan7/ppips_clblm_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_clblm_l.origin_info.db`](./spartan7/ppips_clblm_l.origin_info.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./spartan7/ppips_clblm_r.db`](./spartan7/ppips_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_clblm_r.origin_info.db`](./spartan7/ppips_clblm_r.origin_info.db)
* [`77fba62caedba6632e55834bbc40ff797181d8825e2f4d55987a04a38a95a6c0 ./spartan7/ppips_clk_bufg_bot_r.db`](./spartan7/ppips_clk_bufg_bot_r.db)
* [`15dba278ba801744b1ed558220334899fc098acd8e8aff20ab9761249a70e839 ./spartan7/ppips_clk_bufg_top_r.db`](./spartan7/ppips_clk_bufg_top_r.db)
* [`0dbef414182c3ef9054f4b9bc15c41c435d4bef2db30850add728d3de93749b8 ./spartan7/ppips_clk_hrow_bot_r.db`](./spartan7/ppips_clk_hrow_bot_r.db)
* [`8774624d8398b6000e80cefbcf5a5bac095e1c8650772c23f9b73448e0df5dbb ./spartan7/ppips_clk_hrow_top_r.db`](./spartan7/ppips_clk_hrow_top_r.db)
* [`86af96d6f2c02f2810033362bb9fdd4c3cd03e22dc0eeb00b2746e2c964c10b9 ./spartan7/ppips_cmt_top_l_lower_b.db`](./spartan7/ppips_cmt_top_l_lower_b.db)
* [`76ec382173915e8a5051e193da2e3f1444732a11f7e9b3cce09f625fc9470491 ./spartan7/ppips_cmt_top_l_lower_t.db`](./spartan7/ppips_cmt_top_l_lower_t.db)
* [`3bfa8e34baae599129beb382c5b80c0b8fd0f4a0f7d014763309247354796eea ./spartan7/ppips_cmt_top_l_upper_b.db`](./spartan7/ppips_cmt_top_l_upper_b.db)
* [`98131a12cbd232d1413ce4105d06afa7882241b03e1df7b6f7d49e6b14123deb ./spartan7/ppips_cmt_top_l_upper_t.db`](./spartan7/ppips_cmt_top_l_upper_t.db)
* [`5ec9636f945df96c85ccdb629547895c6bd91ab53d10e191dbf84c1b6042891e ./spartan7/ppips_cmt_top_r_lower_b.db`](./spartan7/ppips_cmt_top_r_lower_b.db)
* [`73e08394d2e4fe5a545c11b28b2a4f9d787dde620d35dcb5d060e5b397bb539e ./spartan7/ppips_cmt_top_r_lower_t.db`](./spartan7/ppips_cmt_top_r_lower_t.db)
* [`1d4bccbcd029d59281817179ab9372cc54bc70422aeb5215fc8990d5d3fbccda ./spartan7/ppips_cmt_top_r_upper_b.db`](./spartan7/ppips_cmt_top_r_upper_b.db)
* [`1388b1284e2c7a82b8e1c96dcc85622c60043bce12b22dc1e40720f8ef192b7a ./spartan7/ppips_cmt_top_r_upper_t.db`](./spartan7/ppips_cmt_top_r_upper_t.db)
* [`19a75e750918cac3938c3d9124bf22ab0c97ed13a7de9f9624721d2912ddd027 ./spartan7/ppips_dsp_l.db`](./spartan7/ppips_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_dsp_l.origin_info.db`](./spartan7/ppips_dsp_l.origin_info.db)
* [`c9cd59ba1b2c83aaa406c9beab055c146532535096acb52b4c25d12efb3fe5ec ./spartan7/ppips_dsp_r.db`](./spartan7/ppips_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./spartan7/ppips_dsp_r.origin_info.db`](./spartan7/ppips_dsp_r.origin_info.db)
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* [`bc71258536b864a886cb37982b6c1ae6382d818c9a621881c54f86672399c089 ./spartan7/tile_type_CMT_TOP_R_UPPER_T.json`](./spartan7/tile_type_CMT_TOP_R_UPPER_T.json)
* [`c0e9a7f304a6ac7ba977423d3dde23b4f582431787f537055da3a293df05a651 ./spartan7/tile_type_DSP_L.json`](./spartan7/tile_type_DSP_L.json)
* [`7b46567b5f4b81d0a92218a78c1c69345cbb0a6de530ddf9af1025ab425b1349 ./spartan7/tile_type_DSP_R.json`](./spartan7/tile_type_DSP_R.json)
* [`9d1dcf2272f9444d33aada814268d3d7c8755b80711700d4e38627a25ca66ad6 ./spartan7/tile_type_GTP_CHANNEL_0.json`](./spartan7/tile_type_GTP_CHANNEL_0.json)
* [`e5ab3107f063180efc35926ba5949c58cdc27894c379f595f64e0c18b271faa3 ./spartan7/tile_type_GTP_CHANNEL_1.json`](./spartan7/tile_type_GTP_CHANNEL_1.json)
* [`c023036fffa15c51f121135dd6c986e3bdc58afeab8fdec420ea5f747e60e0a5 ./spartan7/tile_type_GTP_CHANNEL_2.json`](./spartan7/tile_type_GTP_CHANNEL_2.json)
* [`0d2ac7a133cd107cbf9403cb86642675961e381719483d438ef0b529e4518be7 ./spartan7/tile_type_GTP_CHANNEL_3.json`](./spartan7/tile_type_GTP_CHANNEL_3.json)
* [`83c2646b94a4e71f1bec99fa1a1b9e9b83dc985e2b606f6b274089b373404712 ./spartan7/tile_type_GTP_COMMON.json`](./spartan7/tile_type_GTP_COMMON.json)
* [`17539ba01ea6a00c8344f3b954feaeaf021c79b56b69dee8a3ebd64e843642c5 ./spartan7/tile_type_GTP_INT_INTERFACE.json`](./spartan7/tile_type_GTP_INT_INTERFACE.json)
* [`8161e7e508536df01e2d58da947c228db0af1c8dd9af88c6919d2e3c3568790e ./spartan7/tile_type_HCLK_BRAM.json`](./spartan7/tile_type_HCLK_BRAM.json)
* [`191a39fc956f7bb56e36f65a7fad57632f489052887a8569869c40b21af80d63 ./spartan7/tile_type_HCLK_CLB.json`](./spartan7/tile_type_HCLK_CLB.json)
* [`ca4dc215eb05e20c613da253c2d13929f1ec43a31cd816cf0a6449e135d1e894 ./spartan7/tile_type_HCLK_CMT.json`](./spartan7/tile_type_HCLK_CMT.json)
* [`cb281635fc51452b7bbed0f2cec780c3915501ae7d9d6a0b92fa5934bd390123 ./spartan7/tile_type_HCLK_CMT_L.json`](./spartan7/tile_type_HCLK_CMT_L.json)
* [`b9839b9c2b660625ac28e93f0817741bef6d0e1ed65a96431f461f2c89cc8fb0 ./spartan7/tile_type_HCLK_DSP_L.json`](./spartan7/tile_type_HCLK_DSP_L.json)
* [`42fd5e8e2d9acb69c05171851ce6c1738ace0bb1294ab255230b0d5b0c38e03c ./spartan7/tile_type_HCLK_DSP_R.json`](./spartan7/tile_type_HCLK_DSP_R.json)
* [`55c960eaada832f9c300ec932582b4aed11063abc2bd7f6894488ec563410883 ./spartan7/tile_type_HCLK_FEEDTHRU_1.json`](./spartan7/tile_type_HCLK_FEEDTHRU_1.json)
* [`2d68dba3f874c0b57733c0ce1337603132774c5face2b101f41882c7a48e5813 ./spartan7/tile_type_HCLK_FEEDTHRU_2.json`](./spartan7/tile_type_HCLK_FEEDTHRU_2.json)
* [`657b0fbfbc18e6305d2d4981ed1a6fac13de7fe2169288093c2e78f3e093c9f4 ./spartan7/tile_type_HCLK_FIFO_L.json`](./spartan7/tile_type_HCLK_FIFO_L.json)
* [`c93fdc46f9ce5af990f31b450ea4f54f888460b4cd0076b11e8f7770a1b29605 ./spartan7/tile_type_HCLK_GTX.json`](./spartan7/tile_type_HCLK_GTX.json)
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* [`75924d75150b1cd565369cb5fd30b52596e36f9e3d77b9a1f05be69907d31c6c ./spartan7/tile_type_HCLK_IOI3.json`](./spartan7/tile_type_HCLK_IOI3.json)
* [`6e7bf7df7c20a4763f0a78a126f7d1815a3f6722f090947098262cb73e3c630b ./spartan7/tile_type_HCLK_L.json`](./spartan7/tile_type_HCLK_L.json)
* [`9107f79f1fd8970fc4ac42be3d4952d26bc77a61ca2b2667cea094bb61537628 ./spartan7/tile_type_HCLK_L_BOT_UTURN.json`](./spartan7/tile_type_HCLK_L_BOT_UTURN.json)
* [`ec736cba930473c056a939d5dba9b206f996798ad89d7783d09bfb7d28c66e0e ./spartan7/tile_type_HCLK_R.json`](./spartan7/tile_type_HCLK_R.json)
* [`cef6a444f7205be6436bd0df522676914c65c2f86ddc255a13c6d39b2b40436b ./spartan7/tile_type_HCLK_R_BOT_UTURN.json`](./spartan7/tile_type_HCLK_R_BOT_UTURN.json)
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* [`2d352aa58106c31c0862d3f9bbc47d618286817c53665336fcdd485ae4a43dbf ./spartan7/tile_type_HCLK_TERM_GTX.json`](./spartan7/tile_type_HCLK_TERM_GTX.json)
* [`877b9165125fb1ee79a300b002a651c23951921a1151aca52da89a8b6bba3c55 ./spartan7/tile_type_HCLK_VBRK.json`](./spartan7/tile_type_HCLK_VBRK.json)
* [`e1033a2139e77bf556961a22dd521f8ac44112e7db4eaf4462dcdcc280f71996 ./spartan7/tile_type_HCLK_VFRAME.json`](./spartan7/tile_type_HCLK_VFRAME.json)
* [`ee791ad9e0bcbee17b2aa252dd86d01014439a581710370e2c2b26348d847d33 ./spartan7/tile_type_INT_FEEDTHRU_1.json`](./spartan7/tile_type_INT_FEEDTHRU_1.json)
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* [`1d485459ccb8b8deb194961c6b31193fccdadec2d8d7bfb2dc724107c5f111ec ./spartan7/tile_type_INT_INTERFACE_L.json`](./spartan7/tile_type_INT_INTERFACE_L.json)
* [`20164cc8ec06d35a112a5262e196bf3a2832e84dc150d702084bff3ec24ec701 ./spartan7/tile_type_INT_INTERFACE_R.json`](./spartan7/tile_type_INT_INTERFACE_R.json)
* [`8a797a63bfa17434596b552857bdfe4f650124755169f5a41fbff493596bcbe4 ./spartan7/tile_type_INT_L.json`](./spartan7/tile_type_INT_L.json)
* [`de16784ca2b0f5b2198302b8427c6788dd0940164c0560d9aa0f74f198192045 ./spartan7/tile_type_INT_R.json`](./spartan7/tile_type_INT_R.json)
* [`2895d4a043ce8b668ac49e7758248adc54bc1e10ce0b3caafef99445b9d4383e ./spartan7/tile_type_IO_INT_INTERFACE_L.json`](./spartan7/tile_type_IO_INT_INTERFACE_L.json)
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* [`1601e8b364fbb7bd1ead4ac45680c1bc44ed6f5e564b6e834671c6415093d849 ./spartan7/tile_type_LIOB33.json`](./spartan7/tile_type_LIOB33.json)
* [`3c28639cb4bf1d8a91b69e03bc27b3d9979b9dbcdd06b6b5d920739fcf3ebcfd ./spartan7/tile_type_LIOB33_SING.json`](./spartan7/tile_type_LIOB33_SING.json)
* [`7e48c2acf74e484be7b35ad4251411cef0648f959760f991daedc6ead3c69597 ./spartan7/tile_type_LIOI3.json`](./spartan7/tile_type_LIOI3.json)
* [`65e6812009e1fc95c4614b8ffffc8f1cf6604dd89f5238db9402f838e5e8a1ae ./spartan7/tile_type_LIOI3_SING.json`](./spartan7/tile_type_LIOI3_SING.json)
* [`f9fc1b1ec1e01b9edf3e2962edf66c085b6b5ab223046c37271ca949bf7da323 ./spartan7/tile_type_LIOI3_TBYTESRC.json`](./spartan7/tile_type_LIOI3_TBYTESRC.json)
* [`a1eabe80d07cdfcef33f8ad7d2ae5dad4e40ddd17731d436bb70cd03f44a6ace ./spartan7/tile_type_LIOI3_TBYTETERM.json`](./spartan7/tile_type_LIOI3_TBYTETERM.json)
* [`ec23df842a105af6ffec036b52b06576751bafd08036277637cab85ff649a6c7 ./spartan7/tile_type_L_TERM_INT.json`](./spartan7/tile_type_L_TERM_INT.json)
* [`662a70ae60ed7ff01f9f1c5fbd5dcf7da1c70ec0ce61ef9d0833bfb19d7a6a10 ./spartan7/tile_type_MONITOR_BOT.json`](./spartan7/tile_type_MONITOR_BOT.json)
* [`1b704144bedef609d598b5f2652ad4e60e06019c6a4a2114b52d7887ef917a6f ./spartan7/tile_type_MONITOR_MID.json`](./spartan7/tile_type_MONITOR_MID.json)
* [`aebd63cbe00e7563a2039de4ade97e0d13cd64a6e970d9ba35f96ea0424c3a4f ./spartan7/tile_type_MONITOR_TOP.json`](./spartan7/tile_type_MONITOR_TOP.json)
* [`d430688c70e289f09318774410f2f55e53639c3544fca8a3c98d420f714b0c2f ./spartan7/tile_type_NULL.json`](./spartan7/tile_type_NULL.json)
* [`e8bc6faf0046398d7a378018f88f7117478ee209181f842dd83d34188c82a488 ./spartan7/tile_type_PCIE_BOT.json`](./spartan7/tile_type_PCIE_BOT.json)
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* [`467d1a8087047de8ba7b7c824bd74db1a5a07129a381b058ef6b3cd248118a36 ./spartan7/tile_type_PCIE_INT_INTERFACE_R.json`](./spartan7/tile_type_PCIE_INT_INTERFACE_R.json)
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* [`a3b22b8f5e84d9d357d06f9228d91ade85096b465a70793a2413e39ddd1afb34 ./spartan7/tile_type_RIOB33.json`](./spartan7/tile_type_RIOB33.json)
* [`a195020886d311b54a2376e8d47aea332482fdb5e122ef8a8b6a814da7032f36 ./spartan7/tile_type_RIOB33_SING.json`](./spartan7/tile_type_RIOB33_SING.json)
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* [`c4046ebb8b4ad92769b3712ae7fb5267531528e6af611272a1775823913dd47b ./spartan7/tile_type_VBRK.json`](./spartan7/tile_type_VBRK.json)
* [`21b90c91f9813d358bd844deb77ed7dde43e215a52950e3ba66af04729ccfba2 ./spartan7/tile_type_VBRK_EXT.json`](./spartan7/tile_type_VBRK_EXT.json)
* [`fc110ffa38f152eb0be0c40107d6c76c83054ec4e9f4b0a333be5b96371ceecd ./spartan7/tile_type_VFRAME.json`](./spartan7/tile_type_VFRAME.json)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./spartan7/timings/BRAM_L.sdf`](./spartan7/timings/BRAM_L.sdf)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./spartan7/timings/BRAM_R.sdf`](./spartan7/timings/BRAM_R.sdf)
* [`120e57d254f8394507718098dd4fe299ede60d3228c3b4e90669577c9de64042 ./spartan7/timings/CFG_CENTER_MID.sdf`](./spartan7/timings/CFG_CENTER_MID.sdf)
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* [`64317dce36fb887f93b18c4020382cea2d94668f2ffe6417b6bd78787f80001e ./spartan7/timings/CLBLL_L.sdf`](./spartan7/timings/CLBLL_L.sdf)
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* [`9461f82cd0dbf257bc8efa85899bac3b187962cd3fe5dec44b252a6b37f6b9d9 ./spartan7/timings/CLBLM_L.sdf`](./spartan7/timings/CLBLM_L.sdf)
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* [`c396e1f4aa219633ad558731183c49ec9e92659b79eeff85b42fdac0de7c2368 ./spartan7/timings/CLK_HROW_BOT_R.sdf`](./spartan7/timings/CLK_HROW_BOT_R.sdf)
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* [`ff96f865bbd65952c73a8b8065c1ba6763ad61c94fe1ba40406dbdd850d4da04 ./spartan7/timings/CMT_FIFO_L.sdf`](./spartan7/timings/CMT_FIFO_L.sdf)
* [`ff96f865bbd65952c73a8b8065c1ba6763ad61c94fe1ba40406dbdd850d4da04 ./spartan7/timings/CMT_FIFO_R.sdf`](./spartan7/timings/CMT_FIFO_R.sdf)
* [`668be5d275b3b9522a2e02aa7789bd4df746ddf4eaf14ddb2c29d20ca8f5c751 ./spartan7/timings/CMT_TOP_L_LOWER_B.sdf`](./spartan7/timings/CMT_TOP_L_LOWER_B.sdf)
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* [`668be5d275b3b9522a2e02aa7789bd4df746ddf4eaf14ddb2c29d20ca8f5c751 ./spartan7/timings/CMT_TOP_R_LOWER_B.sdf`](./spartan7/timings/CMT_TOP_R_LOWER_B.sdf)
* [`bda848e132cf93158addf5db6e449dd5d79050155bd2ba52ccad7bd3c1607ec4 ./spartan7/timings/CMT_TOP_R_LOWER_T.sdf`](./spartan7/timings/CMT_TOP_R_LOWER_T.sdf)
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* [`3f9923d175379d32f859a8d3e07992c0174cabe3b260c14b69394009fa1d0569 ./spartan7/timings/DSP_L.sdf`](./spartan7/timings/DSP_L.sdf)
* [`3f9923d175379d32f859a8d3e07992c0174cabe3b260c14b69394009fa1d0569 ./spartan7/timings/DSP_R.sdf`](./spartan7/timings/DSP_R.sdf)
* [`2e60feee8ddc9e67946362378ff347e1fedd2dbabe346e745a2ea83a6abe0dbf ./spartan7/timings/HCLK_CMT.sdf`](./spartan7/timings/HCLK_CMT.sdf)
* [`2e60feee8ddc9e67946362378ff347e1fedd2dbabe346e745a2ea83a6abe0dbf ./spartan7/timings/HCLK_CMT_L.sdf`](./spartan7/timings/HCLK_CMT_L.sdf)
* [`aa457af9f2c18f89df64c0cfedf6374e08fb7e0ef4c671f25c677f2de7430708 ./spartan7/timings/HCLK_IOI3.sdf`](./spartan7/timings/HCLK_IOI3.sdf)
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./spartan7/timings/LIOB33.sdf`](./spartan7/timings/LIOB33.sdf)
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* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./spartan7/timings/LIOI3.sdf`](./spartan7/timings/LIOI3.sdf)
* [`4cd6468585cb94150403030132d9ba73b414875a93a3f87b8e5a8d56a64ef43f ./spartan7/timings/LIOI3_SING.sdf`](./spartan7/timings/LIOI3_SING.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./spartan7/timings/LIOI3_TBYTESRC.sdf`](./spartan7/timings/LIOI3_TBYTESRC.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./spartan7/timings/LIOI3_TBYTETERM.sdf`](./spartan7/timings/LIOI3_TBYTETERM.sdf)
* [`8adb21c5b19dc331cfeba427e65c1c15f33fbd7e43427acba206c109f5ce9985 ./spartan7/timings/MONITOR_BOT.sdf`](./spartan7/timings/MONITOR_BOT.sdf)
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./spartan7/timings/RIOB33.sdf`](./spartan7/timings/RIOB33.sdf)
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./spartan7/timings/RIOB33_SING.sdf`](./spartan7/timings/RIOB33_SING.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./spartan7/timings/RIOI3.sdf`](./spartan7/timings/RIOI3.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./spartan7/timings/RIOI3_SING.sdf`](./spartan7/timings/RIOI3_SING.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./spartan7/timings/RIOI3_TBYTESRC.sdf`](./spartan7/timings/RIOI3_TBYTESRC.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./spartan7/timings/RIOI3_TBYTETERM.sdf`](./spartan7/timings/RIOI3_TBYTETERM.sdf)
* [`feb5cf787894379d158c5218ba44af20458c8008a1e75e30df00adde8aa97108 ./spartan7/timings/carry4_slicel.sdf`](./spartan7/timings/carry4_slicel.sdf)
* [`626d9e188a1c4874f7ac657e82c64df8d52f819624e8ee4f9ed9e557d85ad3f2 ./spartan7/timings/carry4_slicem.sdf`](./spartan7/timings/carry4_slicem.sdf)
* [`fd31d66077f869d01f13d9fabbd0dcd38b4aab0322179ecf9ac190a3b70c5456 ./spartan7/timings/slicel.sdf`](./spartan7/timings/slicel.sdf)
* [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e ./spartan7/timings/slicem.sdf`](./spartan7/timings/slicem.sdf)
* [`b60e01fef4c8c8d47fc646190d2d17fc63210cd0e82613624761e7463a7c35a6 ./spartan7/xc7s50/node_wires.json`](./spartan7/xc7s50/node_wires.json)
* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./spartan7/xc7s50/tileconn.json`](./spartan7/xc7s50/tileconn.json)
* [`478cd2342474f7114c138109ae836d2cd4a6fe5bafb487fafdb04afe3de05623 ./spartan7/xc7s50/tilegrid.json`](./spartan7/xc7s50/tilegrid.json)
* [`0c8dd2e217feaa7ef948d77fda96ffe010309499ad2fdb8745be2d8253264b63 ./spartan7/xc7s50csga324-1/package_pins.csv`](./spartan7/xc7s50csga324-1/package_pins.csv)
* [`242008a2dab3f303995a979ec8574c4d78695a5e216b0257a96a375588a839a4 ./spartan7/xc7s50csga324-1/part.json`](./spartan7/xc7s50csga324-1/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50csga324-1/part.yaml`](./spartan7/xc7s50csga324-1/part.yaml)
* [`0c8dd2e217feaa7ef948d77fda96ffe010309499ad2fdb8745be2d8253264b63 ./spartan7/xc7s50csga324-1IL/package_pins.csv`](./spartan7/xc7s50csga324-1IL/package_pins.csv)
* [`242008a2dab3f303995a979ec8574c4d78695a5e216b0257a96a375588a839a4 ./spartan7/xc7s50csga324-1IL/part.json`](./spartan7/xc7s50csga324-1IL/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50csga324-1IL/part.yaml`](./spartan7/xc7s50csga324-1IL/part.yaml)
* [`0c8dd2e217feaa7ef948d77fda96ffe010309499ad2fdb8745be2d8253264b63 ./spartan7/xc7s50csga324-2/package_pins.csv`](./spartan7/xc7s50csga324-2/package_pins.csv)
* [`242008a2dab3f303995a979ec8574c4d78695a5e216b0257a96a375588a839a4 ./spartan7/xc7s50csga324-2/part.json`](./spartan7/xc7s50csga324-2/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50csga324-2/part.yaml`](./spartan7/xc7s50csga324-2/part.yaml)
* [`000cb04fb2e863df7a1e01925c184da5bb68cf6777a0a7cc2776d980bb204742 ./spartan7/xc7s50fgga484-1/package_pins.csv`](./spartan7/xc7s50fgga484-1/package_pins.csv)
* [`242008a2dab3f303995a979ec8574c4d78695a5e216b0257a96a375588a839a4 ./spartan7/xc7s50fgga484-1/part.json`](./spartan7/xc7s50fgga484-1/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50fgga484-1/part.yaml`](./spartan7/xc7s50fgga484-1/part.yaml)
* [`000cb04fb2e863df7a1e01925c184da5bb68cf6777a0a7cc2776d980bb204742 ./spartan7/xc7s50fgga484-1IL/package_pins.csv`](./spartan7/xc7s50fgga484-1IL/package_pins.csv)
* [`242008a2dab3f303995a979ec8574c4d78695a5e216b0257a96a375588a839a4 ./spartan7/xc7s50fgga484-1IL/part.json`](./spartan7/xc7s50fgga484-1IL/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50fgga484-1IL/part.yaml`](./spartan7/xc7s50fgga484-1IL/part.yaml)
* [`000cb04fb2e863df7a1e01925c184da5bb68cf6777a0a7cc2776d980bb204742 ./spartan7/xc7s50fgga484-2/package_pins.csv`](./spartan7/xc7s50fgga484-2/package_pins.csv)
* [`242008a2dab3f303995a979ec8574c4d78695a5e216b0257a96a375588a839a4 ./spartan7/xc7s50fgga484-2/part.json`](./spartan7/xc7s50fgga484-2/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50fgga484-2/part.yaml`](./spartan7/xc7s50fgga484-2/part.yaml)
* [`3b96b36462a8c00916b2705595534cb647c8bd6a8b0454f6543f4342d9c94478 ./spartan7/xc7s50ftgb196-1/package_pins.csv`](./spartan7/xc7s50ftgb196-1/package_pins.csv)
* [`7482900d8562daeafe22e933caead9413f3469318ba0e57760277867060e44c8 ./spartan7/xc7s50ftgb196-1/part.json`](./spartan7/xc7s50ftgb196-1/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50ftgb196-1/part.yaml`](./spartan7/xc7s50ftgb196-1/part.yaml)
* [`3b96b36462a8c00916b2705595534cb647c8bd6a8b0454f6543f4342d9c94478 ./spartan7/xc7s50ftgb196-1IL/package_pins.csv`](./spartan7/xc7s50ftgb196-1IL/package_pins.csv)
* [`7482900d8562daeafe22e933caead9413f3469318ba0e57760277867060e44c8 ./spartan7/xc7s50ftgb196-1IL/part.json`](./spartan7/xc7s50ftgb196-1IL/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50ftgb196-1IL/part.yaml`](./spartan7/xc7s50ftgb196-1IL/part.yaml)
* [`3b96b36462a8c00916b2705595534cb647c8bd6a8b0454f6543f4342d9c94478 ./spartan7/xc7s50ftgb196-2/package_pins.csv`](./spartan7/xc7s50ftgb196-2/package_pins.csv)
* [`7482900d8562daeafe22e933caead9413f3469318ba0e57760277867060e44c8 ./spartan7/xc7s50ftgb196-2/part.json`](./spartan7/xc7s50ftgb196-2/part.json)
* [`53f2d35b2dd5494169c9ee2f010b1369e041460c9020e9f1ccea9780561a3ede ./spartan7/xc7s50ftgb196-2/part.yaml`](./spartan7/xc7s50ftgb196-2/part.yaml)
## Database for [zynq7](zynq7/)
### Settings
Created using following [settings/zynq7.sh (sha256: d3953bf67abbbaa760df1dd60a71f2edf66da37e2bf63220a70fada25188d3c9)](https://github.com/SymbiFlow/prjxray/blob/f7f06896ad26bb7c94680dc323d4b871eded1f4e/settings/zynq7.sh)
Created using following [settings/zynq7.sh (sha256: d3953bf67abbbaa760df1dd60a71f2edf66da37e2bf63220a70fada25188d3c9)](https://github.com/SymbiFlow/prjxray/blob/3d1a00527cf8f406d75f462d6cbb3487f8699668/settings/zynq7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#

9
spartan7/element_counts.csv Normal file
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@ -0,0 +1,9 @@
type,count
nodes,1953452
package_pins,484
pips,22002368
site_pins,529419
site_pips,1189262
sites,15481
tiles,18055
wires,6193757
1 type count
2 nodes 1953452
3 package_pins 484
4 pips 22002368
5 site_pins 529419
6 site_pips 1189262
7 sites 15481
8 tiles 18055
9 wires 6193757

4
spartan7/mapping/devices.yaml Normal file
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@ -0,0 +1,4 @@
# device to fabric mapping
"xc7s50":
fabric: "xc7s50"

36
spartan7/mapping/parts.yaml Normal file
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@ -0,0 +1,36 @@
xc7s50csga324-1:
device: xc7s50
package: csga324
speedgrade: '1'
xc7s50csga324-1IL:
device: xc7s50
package: csga324
speedgrade: 1IL
xc7s50csga324-2:
device: xc7s50
package: csga324
speedgrade: '2'
xc7s50fgga484-1:
device: xc7s50
package: fgga484
speedgrade: '1'
xc7s50fgga484-1IL:
device: xc7s50
package: fgga484
speedgrade: 1IL
xc7s50fgga484-2:
device: xc7s50
package: fgga484
speedgrade: '2'
xc7s50ftgb196-1:
device: xc7s50
package: ftgb196
speedgrade: '1'
xc7s50ftgb196-1IL:
device: xc7s50
package: ftgb196
speedgrade: 1IL
xc7s50ftgb196-2:
device: xc7s50
package: ftgb196
speedgrade: '2'

36864
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1874
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0
spartan7/mask_bram_l.origin_info.db Normal file
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36864
spartan7/mask_bram_r.block_ram.db Normal file
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1874
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0
spartan7/mask_bram_r.origin_info.db Normal file
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2254
spartan7/mask_clbll_l.db Normal file
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0
spartan7/mask_clbll_l.origin_info.db Normal file
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2254
spartan7/mask_clbll_r.db Normal file
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0
spartan7/mask_clbll_r.origin_info.db Normal file
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2264
spartan7/mask_clblm_l.db Normal file
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0
spartan7/mask_clblm_l.origin_info.db Normal file
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2264
spartan7/mask_clblm_r.db Normal file
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0
spartan7/mask_clblm_r.origin_info.db Normal file
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1135
spartan7/mask_clk_bufg_bot_r.db Normal file
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128
spartan7/mask_clk_bufg_rebuf.db Normal file
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@ -0,0 +1,128 @@
bit 26_00
bit 26_01
bit 26_02
bit 26_03
bit 26_12
bit 26_13
bit 26_14
bit 26_15
bit 26_16
bit 26_17
bit 26_18
bit 26_19
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_32
bit 26_33
bit 26_34
bit 26_35
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_48
bit 26_49
bit 26_50
bit 26_51
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_64
bit 26_65
bit 26_66
bit 26_67
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_80
bit 26_81
bit 26_82
bit 26_83
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_96
bit 26_97
bit 26_98
bit 26_99
bit 26_108
bit 26_109
bit 26_110
bit 26_111
bit 26_112
bit 26_113
bit 26_114
bit 26_115
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 27_00
bit 27_01
bit 27_02
bit 27_03
bit 27_12
bit 27_13
bit 27_14
bit 27_15
bit 27_16
bit 27_17
bit 27_18
bit 27_19
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_32
bit 27_33
bit 27_34
bit 27_35
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_48
bit 27_49
bit 27_50
bit 27_51
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_64
bit 27_65
bit 27_66
bit 27_67
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_80
bit 27_81
bit 27_82
bit 27_83
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_96
bit 27_97
bit 27_98
bit 27_99
bit 27_108
bit 27_109
bit 27_110
bit 27_111
bit 27_112
bit 27_113
bit 27_114
bit 27_115
bit 27_124
bit 27_125
bit 27_126
bit 27_127

1135
spartan7/mask_clk_bufg_top_r.db Normal file
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994
spartan7/mask_clk_hrow_bot_r.db Normal file
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@ -0,0 +1,994 @@
bit 00_209
bit 00_217
bit 00_218
bit 00_219
bit 00_221
bit 00_305
bit 00_310
bit 00_313
bit 00_314
bit 00_315
bit 00_317
bit 01_205
bit 01_213
bit 01_216
bit 01_217
bit 01_218
bit 01_301
bit 01_308
bit 01_309
bit 01_312
bit 01_313
bit 01_314
bit 21_232
bit 21_328
bit 25_232
bit 25_328
bit 26_24
bit 26_25
bit 26_26
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_40
bit 26_41
bit 26_42
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_56
bit 26_57
bit 26_58
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_72
bit 26_73
bit 26_74
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_88
bit 26_89
bit 26_90
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_104
bit 26_105
bit 26_106
bit 26_108
bit 26_109
bit 26_110
bit 26_111
bit 26_120
bit 26_121
bit 26_122
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_136
bit 26_137
bit 26_138
bit 26_140
bit 26_141
bit 26_142
bit 26_143
bit 26_163
bit 26_168
bit 26_169
bit 26_170
bit 26_171
bit 26_172
bit 26_173
bit 26_174
bit 26_175
bit 26_179
bit 26_184
bit 26_185
bit 26_186
bit 26_187
bit 26_188
bit 26_189
bit 26_190
bit 26_191
bit 26_195
bit 26_200
bit 26_201
bit 26_202
bit 26_203
bit 26_204
bit 26_205
bit 26_206
bit 26_207
bit 26_211
bit 26_216
bit 26_217
bit 26_218
bit 26_219
bit 26_220
bit 26_221
bit 26_222
bit 26_223
bit 26_227
bit 26_232
bit 26_233
bit 26_234
bit 26_235
bit 26_236
bit 26_237
bit 26_238
bit 26_239
bit 26_240
bit 26_241
bit 26_243
bit 26_248
bit 26_249
bit 26_250
bit 26_251
bit 26_252
bit 26_253
bit 26_254
bit 26_255
bit 26_270
bit 26_271
bit 26_274
bit 26_275
bit 26_276
bit 26_277
bit 26_278
bit 26_279
bit 26_280
bit 26_281
bit 26_282
bit 26_283
bit 26_284
bit 26_285
bit 26_286
bit 26_287
bit 26_291
bit 26_296
bit 26_297
bit 26_298
bit 26_299
bit 26_300
bit 26_301
bit 26_302
bit 26_303
bit 26_307
bit 26_312
bit 26_313
bit 26_314
bit 26_315
bit 26_316
bit 26_317
bit 26_318
bit 26_319
bit 26_323
bit 26_328
bit 26_329
bit 26_330
bit 26_331
bit 26_332
bit 26_333
bit 26_334
bit 26_335
bit 26_339
bit 26_344
bit 26_345
bit 26_346
bit 26_347
bit 26_348
bit 26_349
bit 26_350
bit 26_351
bit 26_355
bit 26_360
bit 26_361
bit 26_362
bit 26_363
bit 26_364
bit 26_365
bit 26_366
bit 26_367
bit 26_371
bit 26_376
bit 26_377
bit 26_378
bit 26_379
bit 26_380
bit 26_381
bit 26_382
bit 26_383
bit 26_408
bit 26_409
bit 26_410
bit 26_412
bit 26_413
bit 26_414
bit 26_415
bit 26_424
bit 26_425
bit 26_426
bit 26_428
bit 26_429
bit 26_430
bit 26_431
bit 26_440
bit 26_441
bit 26_442
bit 26_444
bit 26_445
bit 26_446
bit 26_447
bit 26_456
bit 26_457
bit 26_458
bit 26_460
bit 26_461
bit 26_462
bit 26_463
bit 26_472
bit 26_473
bit 26_474
bit 26_476
bit 26_477
bit 26_478
bit 26_479
bit 26_488
bit 26_489
bit 26_490
bit 26_492
bit 26_493
bit 26_494
bit 26_495
bit 26_504
bit 26_505
bit 26_506
bit 26_508
bit 26_509
bit 26_510
bit 26_511
bit 26_520
bit 26_521
bit 26_522
bit 26_524
bit 26_525
bit 26_526
bit 26_527
bit 27_24
bit 27_25
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_40
bit 27_41
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_56
bit 27_57
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_72
bit 27_73
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_88
bit 27_89
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_104
bit 27_105
bit 27_108
bit 27_109
bit 27_110
bit 27_111
bit 27_120
bit 27_121
bit 27_124
bit 27_125
bit 27_126
bit 27_127
bit 27_136
bit 27_137
bit 27_140
bit 27_141
bit 27_142
bit 27_143
bit 27_163
bit 27_166
bit 27_167
bit 27_168
bit 27_169
bit 27_170
bit 27_171
bit 27_172
bit 27_173
bit 27_174
bit 27_175
bit 27_179
bit 27_182
bit 27_183
bit 27_184
bit 27_185
bit 27_186
bit 27_187
bit 27_188
bit 27_189
bit 27_190
bit 27_191
bit 27_195
bit 27_198
bit 27_199
bit 27_200
bit 27_201
bit 27_202
bit 27_203
bit 27_204
bit 27_205
bit 27_206
bit 27_207
bit 27_211
bit 27_214
bit 27_215
bit 27_216
bit 27_217
bit 27_218
bit 27_219
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 27_227
bit 27_230
bit 27_231
bit 27_232
bit 27_233
bit 27_234
bit 27_235
bit 27_236
bit 27_237
bit 27_238
bit 27_239
bit 27_240
bit 27_241
bit 27_243
bit 27_246
bit 27_247
bit 27_248
bit 27_249
bit 27_250
bit 27_251
bit 27_252
bit 27_253
bit 27_254
bit 27_255
bit 27_270
bit 27_271
bit 27_274
bit 27_275
bit 27_276
bit 27_277
bit 27_278
bit 27_279
bit 27_280
bit 27_281
bit 27_282
bit 27_283
bit 27_284
bit 27_285
bit 27_286
bit 27_287
bit 27_291
bit 27_294
bit 27_295
bit 27_296
bit 27_297
bit 27_298
bit 27_299
bit 27_300
bit 27_301
bit 27_302
bit 27_303
bit 27_307
bit 27_310
bit 27_311
bit 27_312
bit 27_313
bit 27_314
bit 27_315
bit 27_316
bit 27_317
bit 27_318
bit 27_319
bit 27_323
bit 27_326
bit 27_327
bit 27_328
bit 27_329
bit 27_330
bit 27_331
bit 27_332
bit 27_333
bit 27_334
bit 27_335
bit 27_339
bit 27_342
bit 27_343
bit 27_344
bit 27_345
bit 27_346
bit 27_347
bit 27_348
bit 27_349
bit 27_350
bit 27_351
bit 27_355
bit 27_358
bit 27_359
bit 27_360
bit 27_361
bit 27_362
bit 27_363
bit 27_364
bit 27_365
bit 27_366
bit 27_367
bit 27_371
bit 27_374
bit 27_375
bit 27_376
bit 27_377
bit 27_378
bit 27_379
bit 27_380
bit 27_381
bit 27_382
bit 27_383
bit 27_408
bit 27_409
bit 27_412
bit 27_413
bit 27_414
bit 27_415
bit 27_424
bit 27_425
bit 27_428
bit 27_429
bit 27_430
bit 27_431
bit 27_440
bit 27_441
bit 27_444
bit 27_445
bit 27_446
bit 27_447
bit 27_456
bit 27_457
bit 27_460
bit 27_461
bit 27_462
bit 27_463
bit 27_472
bit 27_473
bit 27_476
bit 27_477
bit 27_478
bit 27_479
bit 27_488
bit 27_489
bit 27_492
bit 27_493
bit 27_494
bit 27_495
bit 27_504
bit 27_505
bit 27_508
bit 27_509
bit 27_510
bit 27_511
bit 27_520
bit 27_521
bit 27_524
bit 27_525
bit 27_526
bit 27_527
bit 28_24
bit 28_25
bit 28_26
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 28_40
bit 28_41
bit 28_42
bit 28_44
bit 28_45
bit 28_46
bit 28_47
bit 28_56
bit 28_57
bit 28_58
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_72
bit 28_73
bit 28_74
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_88
bit 28_89
bit 28_90
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 28_104
bit 28_105
bit 28_106
bit 28_108
bit 28_109
bit 28_110
bit 28_111
bit 28_120
bit 28_121
bit 28_122
bit 28_124
bit 28_125
bit 28_126
bit 28_127
bit 28_136
bit 28_137
bit 28_138
bit 28_140
bit 28_141
bit 28_142
bit 28_143
bit 28_163
bit 28_168
bit 28_169
bit 28_170
bit 28_171
bit 28_172
bit 28_173
bit 28_174
bit 28_175
bit 28_179
bit 28_184
bit 28_185
bit 28_186
bit 28_187
bit 28_188
bit 28_189
bit 28_190
bit 28_191
bit 28_195
bit 28_200
bit 28_201
bit 28_202
bit 28_203
bit 28_204
bit 28_205
bit 28_206
bit 28_207
bit 28_211
bit 28_216
bit 28_217
bit 28_218
bit 28_219
bit 28_220
bit 28_221
bit 28_222
bit 28_223
bit 28_227
bit 28_232
bit 28_233
bit 28_234
bit 28_235
bit 28_236
bit 28_237
bit 28_238
bit 28_239
bit 28_240
bit 28_241
bit 28_243
bit 28_248
bit 28_249
bit 28_250
bit 28_251
bit 28_252
bit 28_253
bit 28_254
bit 28_255
bit 28_270
bit 28_271
bit 28_274
bit 28_275
bit 28_276
bit 28_277
bit 28_278
bit 28_279
bit 28_280
bit 28_281
bit 28_282
bit 28_283
bit 28_284
bit 28_285
bit 28_286
bit 28_287
bit 28_291
bit 28_296
bit 28_297
bit 28_298
bit 28_299
bit 28_300
bit 28_301
bit 28_302
bit 28_303
bit 28_307
bit 28_312
bit 28_313
bit 28_314
bit 28_315
bit 28_316
bit 28_317
bit 28_318
bit 28_319
bit 28_323
bit 28_328
bit 28_329
bit 28_330
bit 28_331
bit 28_332
bit 28_333
bit 28_334
bit 28_335
bit 28_339
bit 28_344
bit 28_345
bit 28_346
bit 28_347
bit 28_348
bit 28_349
bit 28_350
bit 28_351
bit 28_355
bit 28_360
bit 28_361
bit 28_362
bit 28_363
bit 28_364
bit 28_365
bit 28_366
bit 28_367
bit 28_371
bit 28_376
bit 28_377
bit 28_378
bit 28_379
bit 28_380
bit 28_381
bit 28_382
bit 28_383
bit 28_408
bit 28_409
bit 28_410
bit 28_412
bit 28_413
bit 28_414
bit 28_415
bit 28_424
bit 28_425
bit 28_426
bit 28_428
bit 28_429
bit 28_430
bit 28_431
bit 28_440
bit 28_441
bit 28_442
bit 28_444
bit 28_445
bit 28_446
bit 28_447
bit 28_456
bit 28_457
bit 28_458
bit 28_460
bit 28_461
bit 28_462
bit 28_463
bit 28_472
bit 28_473
bit 28_474
bit 28_476
bit 28_477
bit 28_478
bit 28_479
bit 28_488
bit 28_489
bit 28_490
bit 28_492
bit 28_493
bit 28_494
bit 28_495
bit 28_504
bit 28_505
bit 28_506
bit 28_508
bit 28_509
bit 28_510
bit 28_511
bit 28_520
bit 28_521
bit 28_522
bit 28_524
bit 28_525
bit 28_526
bit 28_527
bit 29_24
bit 29_25
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 29_40
bit 29_41
bit 29_44
bit 29_45
bit 29_46
bit 29_47
bit 29_56
bit 29_57
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_72
bit 29_73
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_88
bit 29_89
bit 29_92
bit 29_93
bit 29_94
bit 29_95
bit 29_104
bit 29_105
bit 29_108
bit 29_109
bit 29_110
bit 29_111
bit 29_120
bit 29_121
bit 29_124
bit 29_125
bit 29_126
bit 29_127
bit 29_136
bit 29_137
bit 29_140
bit 29_141
bit 29_142
bit 29_143
bit 29_163
bit 29_166
bit 29_167
bit 29_168
bit 29_169
bit 29_170
bit 29_171
bit 29_172
bit 29_173
bit 29_174
bit 29_175
bit 29_179
bit 29_182
bit 29_183
bit 29_184
bit 29_185
bit 29_186
bit 29_187
bit 29_188
bit 29_189
bit 29_190
bit 29_191
bit 29_195
bit 29_198
bit 29_199
bit 29_200
bit 29_201
bit 29_202
bit 29_203
bit 29_204
bit 29_205
bit 29_206
bit 29_207
bit 29_211
bit 29_214
bit 29_215
bit 29_216
bit 29_217
bit 29_218
bit 29_219
bit 29_220
bit 29_221
bit 29_222
bit 29_223
bit 29_227
bit 29_230
bit 29_231
bit 29_232
bit 29_233
bit 29_234
bit 29_235
bit 29_236
bit 29_237
bit 29_238
bit 29_239
bit 29_240
bit 29_241
bit 29_243
bit 29_246
bit 29_247
bit 29_248
bit 29_249
bit 29_250
bit 29_251
bit 29_252
bit 29_253
bit 29_254
bit 29_255
bit 29_270
bit 29_271
bit 29_274
bit 29_275
bit 29_276
bit 29_277
bit 29_278
bit 29_279
bit 29_280
bit 29_281
bit 29_282
bit 29_283
bit 29_284
bit 29_285
bit 29_286
bit 29_287
bit 29_291
bit 29_294
bit 29_295
bit 29_296
bit 29_297
bit 29_298
bit 29_299
bit 29_300
bit 29_301
bit 29_302
bit 29_303
bit 29_307
bit 29_310
bit 29_311
bit 29_312
bit 29_313
bit 29_314
bit 29_315
bit 29_316
bit 29_317
bit 29_318
bit 29_319
bit 29_323
bit 29_326
bit 29_327
bit 29_328
bit 29_329
bit 29_330
bit 29_331
bit 29_332
bit 29_333
bit 29_334
bit 29_335
bit 29_339
bit 29_342
bit 29_343
bit 29_344
bit 29_345
bit 29_346
bit 29_347
bit 29_348
bit 29_349
bit 29_350
bit 29_351
bit 29_355
bit 29_358
bit 29_359
bit 29_360
bit 29_361
bit 29_362
bit 29_363
bit 29_364
bit 29_365
bit 29_366
bit 29_367
bit 29_371
bit 29_374
bit 29_375
bit 29_376
bit 29_377
bit 29_378
bit 29_379
bit 29_380
bit 29_381
bit 29_382
bit 29_383
bit 29_408
bit 29_409
bit 29_412
bit 29_413
bit 29_414
bit 29_415
bit 29_424
bit 29_425
bit 29_428
bit 29_429
bit 29_430
bit 29_431
bit 29_440
bit 29_441
bit 29_444
bit 29_445
bit 29_446
bit 29_447
bit 29_456
bit 29_457
bit 29_460
bit 29_461
bit 29_462
bit 29_463
bit 29_472
bit 29_473
bit 29_476
bit 29_477
bit 29_478
bit 29_479
bit 29_488
bit 29_489
bit 29_492
bit 29_493
bit 29_494
bit 29_495
bit 29_504
bit 29_505
bit 29_508
bit 29_509
bit 29_510
bit 29_511
bit 29_520
bit 29_521
bit 29_524
bit 29_525
bit 29_526
bit 29_527

1026
spartan7/mask_clk_hrow_top_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

1525
spartan7/mask_dsp_l.db Normal file
View File

File diff suppressed because it is too large Load Diff

0
spartan7/mask_dsp_l.origin_info.db Normal file
View File

1515
spartan7/mask_dsp_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

0
spartan7/mask_dsp_r.origin_info.db Normal file
View File

286
spartan7/mask_hclk_cmt.db Normal file
View File

@ -0,0 +1,286 @@
bit 26_117
bit 26_118
bit 26_120
bit 26_121
bit 26_122
bit 26_123
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_128
bit 26_129
bit 26_130
bit 26_131
bit 26_132
bit 26_133
bit 26_134
bit 26_135
bit 26_136
bit 26_137
bit 26_138
bit 26_139
bit 26_140
bit 26_141
bit 26_142
bit 26_143
bit 26_144
bit 26_145
bit 26_146
bit 26_147
bit 26_148
bit 26_149
bit 26_150
bit 26_151
bit 26_152
bit 26_153
bit 26_154
bit 26_155
bit 26_156
bit 26_158
bit 26_159
bit 26_174
bit 26_175
bit 26_181
bit 26_182
bit 26_183
bit 26_184
bit 26_185
bit 26_195
bit 26_196
bit 26_197
bit 26_198
bit 26_200
bit 26_201
bit 26_202
bit 26_203
bit 26_204
bit 26_205
bit 26_207
bit 26_208
bit 26_209
bit 26_210
bit 26_211
bit 26_212
bit 26_214
bit 26_215
bit 26_216
bit 26_217
bit 26_218
bit 26_219
bit 26_221
bit 26_222
bit 26_223
bit 26_224
bit 26_225
bit 26_226
bit 26_228
bit 26_229
bit 26_230
bit 26_231
bit 26_232
bit 26_233
bit 26_234
bit 27_117
bit 27_118
bit 27_119
bit 27_120
bit 27_121
bit 27_122
bit 27_123
bit 27_125
bit 27_126
bit 27_127
bit 27_128
bit 27_129
bit 27_130
bit 27_132
bit 27_133
bit 27_134
bit 27_135
bit 27_136
bit 27_137
bit 27_139
bit 27_140
bit 27_141
bit 27_142
bit 27_143
bit 27_144
bit 27_146
bit 27_147
bit 27_148
bit 27_149
bit 27_150
bit 27_151
bit 27_153
bit 27_154
bit 27_155
bit 27_157
bit 27_158
bit 27_159
bit 27_174
bit 27_175
bit 27_181
bit 27_182
bit 27_183
bit 27_184
bit 27_185
bit 27_195
bit 27_196
bit 27_197
bit 27_198
bit 27_199
bit 27_200
bit 27_201
bit 27_202
bit 27_203
bit 27_204
bit 27_205
bit 27_206
bit 27_207
bit 27_208
bit 27_209
bit 27_210
bit 27_211
bit 27_212
bit 27_213
bit 27_214
bit 27_215
bit 27_216
bit 27_217
bit 27_218
bit 27_219
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 27_224
bit 27_225
bit 27_226
bit 27_227
bit 27_228
bit 27_229
bit 27_230
bit 27_231
bit 27_233
bit 27_234
bit 28_117
bit 28_118
bit 28_120
bit 28_121
bit 28_122
bit 28_135
bit 28_136
bit 28_137
bit 28_138
bit 28_139
bit 28_140
bit 28_141
bit 28_142
bit 28_143
bit 28_144
bit 28_145
bit 28_146
bit 28_147
bit 28_148
bit 28_149
bit 28_150
bit 28_151
bit 28_152
bit 28_153
bit 28_154
bit 28_155
bit 28_156
bit 28_157
bit 28_158
bit 28_159
bit 28_174
bit 28_175
bit 28_186
bit 28_192
bit 28_193
bit 28_195
bit 28_196
bit 28_197
bit 28_198
bit 28_200
bit 28_201
bit 28_202
bit 28_203
bit 28_204
bit 28_205
bit 28_207
bit 28_208
bit 28_209
bit 28_210
bit 28_211
bit 28_212
bit 28_214
bit 28_215
bit 28_216
bit 28_217
bit 28_230
bit 28_231
bit 28_232
bit 28_233
bit 28_234
bit 29_117
bit 29_118
bit 29_119
bit 29_120
bit 29_121
bit 29_135
bit 29_136
bit 29_137
bit 29_139
bit 29_140
bit 29_141
bit 29_142
bit 29_143
bit 29_144
bit 29_146
bit 29_147
bit 29_148
bit 29_149
bit 29_150
bit 29_151
bit 29_153
bit 29_154
bit 29_155
bit 29_156
bit 29_157
bit 29_158
bit 29_159
bit 29_174
bit 29_175
bit 29_186
bit 29_192
bit 29_193
bit 29_195
bit 29_196
bit 29_197
bit 29_198
bit 29_199
bit 29_200
bit 29_201
bit 29_202
bit 29_203
bit 29_204
bit 29_205
bit 29_206
bit 29_207
bit 29_208
bit 29_209
bit 29_210
bit 29_211
bit 29_212
bit 29_213
bit 29_214
bit 29_215
bit 29_216
bit 29_218
bit 29_229
bit 29_230
bit 29_231
bit 29_233
bit 29_234

286
spartan7/mask_hclk_cmt_l.db Normal file
View File

@ -0,0 +1,286 @@
bit 26_117
bit 26_118
bit 26_120
bit 26_121
bit 26_122
bit 26_123
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_128
bit 26_129
bit 26_130
bit 26_131
bit 26_132
bit 26_133
bit 26_134
bit 26_135
bit 26_136
bit 26_137
bit 26_138
bit 26_139
bit 26_140
bit 26_141
bit 26_142
bit 26_143
bit 26_144
bit 26_145
bit 26_146
bit 26_147
bit 26_148
bit 26_149
bit 26_150
bit 26_151
bit 26_152
bit 26_153
bit 26_154
bit 26_155
bit 26_156
bit 26_158
bit 26_159
bit 26_174
bit 26_175
bit 26_181
bit 26_182
bit 26_183
bit 26_184
bit 26_185
bit 26_195
bit 26_196
bit 26_197
bit 26_198
bit 26_200
bit 26_201
bit 26_202
bit 26_203
bit 26_204
bit 26_205
bit 26_207
bit 26_208
bit 26_209
bit 26_210
bit 26_211
bit 26_212
bit 26_214
bit 26_215
bit 26_216
bit 26_217
bit 26_218
bit 26_219
bit 26_221
bit 26_222
bit 26_223
bit 26_224
bit 26_225
bit 26_226
bit 26_228
bit 26_229
bit 26_230
bit 26_231
bit 26_232
bit 26_233
bit 26_234
bit 27_117
bit 27_118
bit 27_119
bit 27_120
bit 27_121
bit 27_122
bit 27_123
bit 27_125
bit 27_126
bit 27_127
bit 27_128
bit 27_129
bit 27_130
bit 27_132
bit 27_133
bit 27_134
bit 27_135
bit 27_136
bit 27_137
bit 27_139
bit 27_140
bit 27_141
bit 27_142
bit 27_143
bit 27_144
bit 27_146
bit 27_147
bit 27_148
bit 27_149
bit 27_150
bit 27_151
bit 27_153
bit 27_154
bit 27_155
bit 27_157
bit 27_158
bit 27_159
bit 27_174
bit 27_175
bit 27_181
bit 27_182
bit 27_183
bit 27_184
bit 27_185
bit 27_195
bit 27_196
bit 27_197
bit 27_198
bit 27_199
bit 27_200
bit 27_201
bit 27_202
bit 27_203
bit 27_204
bit 27_205
bit 27_206
bit 27_207
bit 27_208
bit 27_209
bit 27_210
bit 27_211
bit 27_212
bit 27_213
bit 27_214
bit 27_215
bit 27_216
bit 27_217
bit 27_218
bit 27_219
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 27_224
bit 27_225
bit 27_226
bit 27_227
bit 27_228
bit 27_229
bit 27_230
bit 27_231
bit 27_233
bit 27_234
bit 28_117
bit 28_118
bit 28_120
bit 28_121
bit 28_122
bit 28_135
bit 28_136
bit 28_137
bit 28_138
bit 28_139
bit 28_140
bit 28_141
bit 28_142
bit 28_143
bit 28_144
bit 28_145
bit 28_146
bit 28_147
bit 28_148
bit 28_149
bit 28_150
bit 28_151
bit 28_152
bit 28_153
bit 28_154
bit 28_155
bit 28_156
bit 28_157
bit 28_158
bit 28_159
bit 28_174
bit 28_175
bit 28_186
bit 28_192
bit 28_193
bit 28_195
bit 28_196
bit 28_197
bit 28_198
bit 28_200
bit 28_201
bit 28_202
bit 28_203
bit 28_204
bit 28_205
bit 28_207
bit 28_208
bit 28_209
bit 28_210
bit 28_211
bit 28_212
bit 28_214
bit 28_215
bit 28_216
bit 28_217
bit 28_230
bit 28_231
bit 28_232
bit 28_233
bit 28_234
bit 29_117
bit 29_118
bit 29_119
bit 29_120
bit 29_121
bit 29_135
bit 29_136
bit 29_137
bit 29_139
bit 29_140
bit 29_141
bit 29_142
bit 29_143
bit 29_144
bit 29_146
bit 29_147
bit 29_148
bit 29_149
bit 29_150
bit 29_151
bit 29_153
bit 29_154
bit 29_155
bit 29_156
bit 29_157
bit 29_158
bit 29_159
bit 29_174
bit 29_175
bit 29_186
bit 29_192
bit 29_193
bit 29_195
bit 29_196
bit 29_197
bit 29_198
bit 29_199
bit 29_200
bit 29_201
bit 29_202
bit 29_203
bit 29_204
bit 29_205
bit 29_206
bit 29_207
bit 29_208
bit 29_209
bit 29_210
bit 29_211
bit 29_212
bit 29_213
bit 29_214
bit 29_215
bit 29_216
bit 29_218
bit 29_229
bit 29_230
bit 29_231
bit 29_233
bit 29_234

182
spartan7/mask_hclk_ioi.db Normal file
View File

@ -0,0 +1,182 @@
bit 26_14
bit 26_15
bit 26_16
bit 26_17
bit 26_18
bit 26_19
bit 26_20
bit 26_21
bit 26_22
bit 26_23
bit 26_24
bit 26_25
bit 26_26
bit 26_27
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 27_14
bit 27_15
bit 27_16
bit 27_17
bit 27_18
bit 27_19
bit 27_20
bit 27_21
bit 27_22
bit 27_23
bit 27_24
bit 27_25
bit 27_26
bit 27_27
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 28_14
bit 28_15
bit 28_18
bit 28_19
bit 28_20
bit 28_21
bit 28_22
bit 28_23
bit 28_24
bit 28_25
bit 28_26
bit 28_27
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 29_14
bit 29_15
bit 29_16
bit 29_17
bit 29_18
bit 29_19
bit 29_20
bit 29_21
bit 29_22
bit 29_23
bit 29_24
bit 29_25
bit 29_26
bit 29_27
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
bit 30_21
bit 30_22
bit 30_23
bit 30_24
bit 30_25
bit 30_26
bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 31_14
bit 31_15
bit 31_16
bit 31_17
bit 31_18
bit 31_20
bit 31_21
bit 31_22
bit 31_23
bit 31_24
bit 31_25
bit 31_26
bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_31
bit 32_14
bit 32_15
bit 32_16
bit 32_17
bit 32_19
bit 32_20
bit 32_22
bit 32_23
bit 32_24
bit 32_25
bit 32_26
bit 32_28
bit 32_30
bit 33_14
bit 33_15
bit 33_16
bit 33_17
bit 33_18
bit 33_19
bit 33_20
bit 33_21
bit 33_23
bit 33_24
bit 33_25
bit 33_26
bit 33_27
bit 33_28
bit 33_29
bit 33_30
bit 33_31
bit 34_15
bit 34_16
bit 34_17
bit 34_18
bit 34_19
bit 34_20
bit 34_23
bit 34_24
bit 34_25
bit 34_26
bit 34_29
bit 34_30
bit 34_31
bit 35_15
bit 35_16
bit 35_17
bit 35_18
bit 35_19
bit 35_21
bit 35_23
bit 35_24
bit 35_25
bit 35_26
bit 35_27
bit 35_28
bit 35_29
bit 36_14
bit 36_16
bit 36_17
bit 36_18
bit 36_20
bit 36_21
bit 36_24
bit 36_25
bit 36_26
bit 36_27
bit 36_28
bit 36_29
bit 36_31
bit 37_14
bit 37_16
bit 37_17
bit 37_18
bit 37_21
bit 37_22
bit 37_28
bit 37_29
bit 37_31

40
spartan7/mask_hclk_ioi3.db Normal file
View File

@ -0,0 +1,40 @@
bit 31_20
bit 32_16
bit 32_17
bit 32_19
bit 32_20
bit 32_22
bit 32_26
bit 32_28
bit 32_30
bit 33_14
bit 33_15
bit 33_16
bit 33_17
bit 33_18
bit 33_19
bit 33_20
bit 33_21
bit 33_23
bit 33_24
bit 33_25
bit 33_26
bit 33_27
bit 33_28
bit 33_29
bit 33_30
bit 33_31
bit 34_15
bit 34_16
bit 34_23
bit 34_24
bit 34_31
bit 35_19
bit 35_21
bit 35_23
bit 35_24
bit 35_25
bit 36_24
bit 36_25
bit 36_26
bit 36_27

104
spartan7/mask_hclk_l.db Normal file
View File

@ -0,0 +1,104 @@
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

0
spartan7/mask_hclk_l.origin_info.db Normal file
View File

104
spartan7/mask_hclk_r.db Normal file
View File

@ -0,0 +1,104 @@
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

0
spartan7/mask_hclk_r.origin_info.db Normal file
View File

72
spartan7/mask_liob33.db Normal file
View File

@ -0,0 +1,72 @@
bit 38_00
bit 38_02
bit 38_04
bit 38_06
bit 38_08
bit 38_10
bit 38_14
bit 38_16
bit 38_18
bit 38_20
bit 38_22
bit 38_32
bit 38_34
bit 38_38
bit 38_40
bit 38_42
bit 38_44
bit 38_62
bit 38_64
bit 38_74
bit 38_76
bit 38_82
bit 38_84
bit 38_86
bit 38_92
bit 38_94
bit 38_98
bit 38_100
bit 38_102
bit 38_106
bit 38_110
bit 38_112
bit 38_118
bit 38_120
bit 38_122
bit 38_126
bit 39_01
bit 39_05
bit 39_07
bit 39_09
bit 39_15
bit 39_17
bit 39_21
bit 39_33
bit 39_35
bit 39_41
bit 39_43
bit 39_45
bit 39_59
bit 39_61
bit 39_63
bit 39_65
bit 39_75
bit 39_83
bit 39_85
bit 39_87
bit 39_89
bit 39_93
bit 39_95
bit 39_97
bit 39_101
bit 39_105
bit 39_107
bit 39_109
bit 39_111
bit 39_113
bit 39_117
bit 39_119
bit 39_121
bit 39_123
bit 39_125
bit 39_127

327
spartan7/mask_lioi3.db Normal file
View File

@ -0,0 +1,327 @@
bit 25_07
bit 25_20
bit 25_21
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_11
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 35_05
bit 35_07
bit 35_11
bit 35_13
bit 35_17
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

327
spartan7/mask_lioi3_tbytesrc.db Normal file
View File

@ -0,0 +1,327 @@
bit 25_07
bit 25_20
bit 25_21
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_11
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 35_05
bit 35_07
bit 35_11
bit 35_13
bit 35_17
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

327
spartan7/mask_lioi3_tbyteterm.db Normal file
View File

@ -0,0 +1,327 @@
bit 25_07
bit 25_20
bit 25_21
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_11
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 35_05
bit 35_07
bit 35_11
bit 35_13
bit 35_17
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

72
spartan7/mask_riob33.db Normal file
View File

@ -0,0 +1,72 @@
bit 38_00
bit 38_02
bit 38_04
bit 38_06
bit 38_08
bit 38_10
bit 38_14
bit 38_16
bit 38_18
bit 38_20
bit 38_22
bit 38_32
bit 38_34
bit 38_38
bit 38_40
bit 38_42
bit 38_44
bit 38_62
bit 38_64
bit 38_74
bit 38_76
bit 38_82
bit 38_84
bit 38_86
bit 38_92
bit 38_94
bit 38_98
bit 38_100
bit 38_102
bit 38_106
bit 38_110
bit 38_112
bit 38_118
bit 38_120
bit 38_122
bit 38_126
bit 39_01
bit 39_05
bit 39_07
bit 39_09
bit 39_15
bit 39_17
bit 39_21
bit 39_33
bit 39_35
bit 39_41
bit 39_43
bit 39_45
bit 39_59
bit 39_61
bit 39_63
bit 39_65
bit 39_75
bit 39_83
bit 39_85
bit 39_87
bit 39_89
bit 39_93
bit 39_95
bit 39_97
bit 39_101
bit 39_105
bit 39_107
bit 39_109
bit 39_111
bit 39_113
bit 39_117
bit 39_119
bit 39_121
bit 39_123
bit 39_125
bit 39_127

327
spartan7/mask_rioi3.db Normal file
View File

@ -0,0 +1,327 @@
bit 25_07
bit 25_20
bit 25_21
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_11
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 35_05
bit 35_07
bit 35_11
bit 35_13
bit 35_17
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

327
spartan7/mask_rioi3_tbytesrc.db Normal file
View File

@ -0,0 +1,327 @@
bit 25_07
bit 25_20
bit 25_21
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_11
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 35_05
bit 35_07
bit 35_11
bit 35_13
bit 35_17
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

327
spartan7/mask_rioi3_tbyteterm.db Normal file
View File

@ -0,0 +1,327 @@
bit 25_07
bit 25_20
bit 25_21
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_11
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 35_05
bit 35_07
bit 35_11
bit 35_13
bit 35_17
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

24
spartan7/ppips_bram_int_interface_l.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

0
spartan7/ppips_bram_int_interface_l.origin_info.db Normal file
View File

24
spartan7/ppips_bram_int_interface_r.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

0
spartan7/ppips_bram_int_interface_r.origin_info.db Normal file
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794
spartan7/ppips_bram_l.db Normal file
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@ -0,0 +1,794 @@
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_L.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_L.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_L.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_L.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_L.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_L.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_L.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_L.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_L.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_L.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_L.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_L.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_L.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_L.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_L.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_L.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_L.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_L.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_L.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_L.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_L.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_L.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_L.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_L.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_L.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_L.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_L.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_L.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_L.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_L.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_L.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_L.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_L.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_L.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_L.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_L.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_L.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_L.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_L.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_L.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_L.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_L.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_L.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_L.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_L.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_L.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_L.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_L.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_L.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_L.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_L.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_L.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_L.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_L.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_L.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_L.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_L.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_L.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_L.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_L.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_L.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_L.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_L.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_L.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_L.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_L.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_L.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_L.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_L.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_L.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_L.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_L.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_L.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_L.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_L.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_L.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_L.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_L.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_L.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_L.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_L.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_L.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_L.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_L.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_L.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_L.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_L.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_L.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_L.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_L.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_L.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_L.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_L.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_L.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_L.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_L.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_L.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_L.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_L.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_L.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_L.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_L.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_L.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_L.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_L.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_L.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_L.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_L.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_L.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_L.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_L.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_L.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_L.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_L.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_L.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_L.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_L.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_L.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_L.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_L.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_L.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_L.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_L.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_L.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_L.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_L.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_L.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_L.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_L.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_L.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_L.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_L.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_L.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_L.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_L.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_L.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_L.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_L.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_L.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_L.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_L.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_L.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_L.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_L.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_L.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_L.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_L.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_L.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_L.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_L.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_L.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_L.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_L.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_L.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_L.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

0
spartan7/ppips_bram_l.origin_info.db Normal file
View File

794
spartan7/ppips_bram_r.db Normal file
View File

@ -0,0 +1,794 @@
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_R.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_R.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_R.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_R.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_R.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_R.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_R.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_R.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_R.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_R.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_R.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_R.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_R.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_R.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_R.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_R.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_R.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_R.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_R.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_R.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_R.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_R.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_R.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_R.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_R.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_R.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_R.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_R.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_R.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_R.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_R.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_R.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_R.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_R.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_R.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_R.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_R.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_R.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_R.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_R.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_R.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_R.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_R.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_R.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_R.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_R.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_R.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_R.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_R.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_R.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_R.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_R.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_R.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_R.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_R.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_R.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_R.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_R.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_R.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_R.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_R.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_R.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_R.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_R.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_R.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_R.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_R.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_R.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_R.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_R.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_R.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_R.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_R.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_R.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_R.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_R.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_R.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_R.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_R.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_R.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_R.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_R.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_R.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_R.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_R.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_R.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_R.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_R.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_R.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_R.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_R.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_R.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_R.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_R.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_R.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_R.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_R.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_R.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_R.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_R.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_R.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_R.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_R.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_R.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_R.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_R.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_R.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_R.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_R.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_R.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_R.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_R.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_R.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_R.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_R.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_R.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_R.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_R.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_R.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_R.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_R.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_R.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_R.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_R.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_R.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_R.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_R.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_R.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_R.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_R.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_R.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_R.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_R.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_R.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_R.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_R.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_R.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_R.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_R.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_R.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_R.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_R.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_R.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_R.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_R.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_R.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_R.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_R.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_R.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_R.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_R.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_R.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_R.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_R.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_R.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

0
spartan7/ppips_bram_r.origin_info.db Normal file
View File

14
spartan7/ppips_brkh_int.db Normal file
View File

@ -0,0 +1,14 @@
BRKH_INT.BRKH_INT_NL1BEG0_SLOW.BRKH_INT_NL1BEG0 always
BRKH_INT.BRKH_INT_NL1BEG1_SLOW.BRKH_INT_NL1BEG1 always
BRKH_INT.BRKH_INT_NL1BEG2_SLOW.BRKH_INT_NL1BEG2 always
BRKH_INT.BRKH_INT_NR1BEG0_SLOW.BRKH_INT_NR1BEG0 always
BRKH_INT.BRKH_INT_NR1BEG1_SLOW.BRKH_INT_NR1BEG1 always
BRKH_INT.BRKH_INT_NR1BEG2_SLOW.BRKH_INT_NR1BEG2 always
BRKH_INT.BRKH_INT_NR1BEG3_SLOW.BRKH_INT_NR1BEG3 always
BRKH_INT.BRKH_INT_SL1END0.BRKH_INT_SL1END0_SLOW always
BRKH_INT.BRKH_INT_SL1END1.BRKH_INT_SL1END1_SLOW always
BRKH_INT.BRKH_INT_SL1END2.BRKH_INT_SL1END2_SLOW always
BRKH_INT.BRKH_INT_SL1END3.BRKH_INT_SL1END3_SLOW always
BRKH_INT.BRKH_INT_SR1END1.BRKH_INT_SR1END1_SLOW always
BRKH_INT.BRKH_INT_SR1END2.BRKH_INT_SR1END2_SLOW always
BRKH_INT.BRKH_INT_SR1END3.BRKH_INT_SR1END3_SLOW always

146
spartan7/ppips_clbll_l.db Normal file
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@ -0,0 +1,146 @@
CLBLL_L.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always

0
spartan7/ppips_clbll_l.origin_info.db Normal file
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146
spartan7/ppips_clbll_r.db Normal file
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@ -0,0 +1,146 @@
CLBLL_R.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always

0
spartan7/ppips_clbll_r.origin_info.db Normal file
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151
spartan7/ppips_clblm_l.db Normal file
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@ -0,0 +1,151 @@
CLBLM_L.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always

0
spartan7/ppips_clblm_l.origin_info.db Normal file
View File

151
spartan7/ppips_clblm_r.db Normal file
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@ -0,0 +1,151 @@
CLBLM_R.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always

0
spartan7/ppips_clblm_r.origin_info.db Normal file
View File

128
spartan7/ppips_clk_bufg_bot_r.db Normal file
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@ -0,0 +1,128 @@
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_IGNORE1.CLK_BUFG_IMUX9_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_S0.CLK_BUFG_IMUX5_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_S1.CLK_BUFG_IMUX1_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_CE0.CLK_BUFG_IMUX22_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_CE1.CLK_BUFG_IMUX18_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_IGNORE0.CLK_BUFG_IMUX14_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_IGNORE1.CLK_BUFG_IMUX10_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_S0.CLK_BUFG_IMUX6_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_S1.CLK_BUFG_IMUX2_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_CE0.CLK_BUFG_IMUX23_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_CE1.CLK_BUFG_IMUX19_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_IGNORE0.CLK_BUFG_IMUX15_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_IGNORE1.CLK_BUFG_IMUX11_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_S0.CLK_BUFG_IMUX7_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_S1.CLK_BUFG_IMUX3_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_CE0.CLK_BUFG_IMUX20_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_CE1.CLK_BUFG_IMUX16_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_IGNORE0.CLK_BUFG_IMUX12_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_IGNORE1.CLK_BUFG_IMUX8_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_S0.CLK_BUFG_IMUX4_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_S1.CLK_BUFG_IMUX0_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_CE0.CLK_BUFG_IMUX21_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_CE1.CLK_BUFG_IMUX17_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_IGNORE0.CLK_BUFG_IMUX13_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_IGNORE1.CLK_BUFG_IMUX9_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_S0.CLK_BUFG_IMUX5_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_S1.CLK_BUFG_IMUX1_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_CE0.CLK_BUFG_IMUX22_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_CE1.CLK_BUFG_IMUX18_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_IGNORE0.CLK_BUFG_IMUX14_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_IGNORE1.CLK_BUFG_IMUX10_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_S0.CLK_BUFG_IMUX6_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_S1.CLK_BUFG_IMUX2_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_CE0.CLK_BUFG_IMUX23_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_CE1.CLK_BUFG_IMUX19_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_IGNORE0.CLK_BUFG_IMUX15_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_IGNORE1.CLK_BUFG_IMUX11_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_S0.CLK_BUFG_IMUX7_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_S1.CLK_BUFG_IMUX3_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_CE0.CLK_BUFG_IMUX20_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_CE1.CLK_BUFG_IMUX16_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_IGNORE0.CLK_BUFG_IMUX12_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_IGNORE1.CLK_BUFG_IMUX8_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_S0.CLK_BUFG_IMUX4_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_S1.CLK_BUFG_IMUX0_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_CE0.CLK_BUFG_IMUX21_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_CE1.CLK_BUFG_IMUX17_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always

128
spartan7/ppips_clk_bufg_top_r.db Normal file
View File

@ -0,0 +1,128 @@
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_IGNORE1.CLK_BUFG_IMUX9_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_S0.CLK_BUFG_IMUX5_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_S1.CLK_BUFG_IMUX1_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_CE0.CLK_BUFG_IMUX22_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_CE1.CLK_BUFG_IMUX18_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_IGNORE0.CLK_BUFG_IMUX14_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_IGNORE1.CLK_BUFG_IMUX10_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_S0.CLK_BUFG_IMUX6_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_S1.CLK_BUFG_IMUX2_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_CE0.CLK_BUFG_IMUX23_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_CE1.CLK_BUFG_IMUX19_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_IGNORE0.CLK_BUFG_IMUX15_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_IGNORE1.CLK_BUFG_IMUX11_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_S0.CLK_BUFG_IMUX7_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_S1.CLK_BUFG_IMUX3_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_CE0.CLK_BUFG_IMUX20_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_CE1.CLK_BUFG_IMUX16_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_IGNORE0.CLK_BUFG_IMUX12_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_IGNORE1.CLK_BUFG_IMUX8_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_S0.CLK_BUFG_IMUX4_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_S1.CLK_BUFG_IMUX0_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_CE0.CLK_BUFG_IMUX21_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_CE1.CLK_BUFG_IMUX17_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_IGNORE0.CLK_BUFG_IMUX13_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_IGNORE1.CLK_BUFG_IMUX9_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_S0.CLK_BUFG_IMUX5_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_S1.CLK_BUFG_IMUX1_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_CE0.CLK_BUFG_IMUX22_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_CE1.CLK_BUFG_IMUX18_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_IGNORE0.CLK_BUFG_IMUX14_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_IGNORE1.CLK_BUFG_IMUX10_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_S0.CLK_BUFG_IMUX6_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_S1.CLK_BUFG_IMUX2_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_CE0.CLK_BUFG_IMUX23_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_CE1.CLK_BUFG_IMUX19_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_IGNORE0.CLK_BUFG_IMUX15_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_IGNORE1.CLK_BUFG_IMUX11_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_S0.CLK_BUFG_IMUX7_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_S1.CLK_BUFG_IMUX3_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_CE0.CLK_BUFG_IMUX20_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_CE1.CLK_BUFG_IMUX16_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_IGNORE0.CLK_BUFG_IMUX12_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_IGNORE1.CLK_BUFG_IMUX8_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_S0.CLK_BUFG_IMUX4_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_S1.CLK_BUFG_IMUX0_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_CE0.CLK_BUFG_IMUX21_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_CE1.CLK_BUFG_IMUX17_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always

168
spartan7/ppips_clk_hrow_bot_r.db Normal file
View File

@ -0,0 +1,168 @@
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L4.CLK_HROW_CE_INT_BOT10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L5.CLK_HROW_CE_INT_BOT11 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R4.CLK_HROW_CE_INT_BOT4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R5.CLK_HROW_CE_INT_BOT5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4.CLK_HROW_IMUX4_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5.CLK_HROW_IMUX5_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4.CLK_HROW_IMUX4_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5.CLK_HROW_IMUX5_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L4.CLK_HROW_CK_HCLK_OUT_L4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L5.CLK_HROW_CK_HCLK_OUT_L5 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R4.CLK_HROW_CK_HCLK_OUT_R4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R5.CLK_HROW_CK_HCLK_OUT_R5 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST13.CLK_HROW_CK_GCLK_TEST_OUT13 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST14.CLK_HROW_CK_GCLK_TEST_OUT14 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST15.CLK_HROW_CK_GCLK_TEST_OUT15 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST23.CLK_HROW_CK_GCLK_TEST_OUT23 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST24.CLK_HROW_CK_GCLK_TEST_OUT24 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST25.CLK_HROW_CK_GCLK_TEST_OUT25 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN13.CLK_HROW_CK_GCLK_IN_TEST13 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN14.CLK_HROW_CK_GCLK_IN_TEST14 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN15.CLK_HROW_CK_GCLK_IN_TEST15 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN23.CLK_HROW_CK_GCLK_IN_TEST23 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN24.CLK_HROW_CK_GCLK_IN_TEST24 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN25.CLK_HROW_CK_GCLK_IN_TEST25 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4.CLK_HROW_CK_MUX_OUT_L4 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5.CLK_HROW_CK_MUX_OUT_L5 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4.CLK_HROW_CK_MUX_OUT_R4 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5.CLK_HROW_CK_MUX_OUT_R5 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_OUT.CLK_HROW_CK_IN_R_OUT_TEST always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0.CLK_HROW_CLK0_3 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1.CLK_HROW_CLK1_3 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0.CLK_HROW_CLK0_4 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1.CLK_HROW_CLK1_4 always

168
spartan7/ppips_clk_hrow_top_r.db Normal file
View File

@ -0,0 +1,168 @@
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L4.CLK_HROW_CE_INT_BOT10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L5.CLK_HROW_CE_INT_BOT11 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R4.CLK_HROW_CE_INT_BOT4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R5.CLK_HROW_CE_INT_BOT5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4.CLK_HROW_IMUX4_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5.CLK_HROW_IMUX5_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4.CLK_HROW_IMUX4_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5.CLK_HROW_IMUX5_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L4.CLK_HROW_CK_HCLK_OUT_L4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L5.CLK_HROW_CK_HCLK_OUT_L5 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R4.CLK_HROW_CK_HCLK_OUT_R4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R5.CLK_HROW_CK_HCLK_OUT_R5 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST13.CLK_HROW_CK_GCLK_TEST_OUT13 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST14.CLK_HROW_CK_GCLK_TEST_OUT14 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST15.CLK_HROW_CK_GCLK_TEST_OUT15 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST23.CLK_HROW_CK_GCLK_TEST_OUT23 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST24.CLK_HROW_CK_GCLK_TEST_OUT24 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST25.CLK_HROW_CK_GCLK_TEST_OUT25 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN13.CLK_HROW_CK_GCLK_IN_TEST13 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN14.CLK_HROW_CK_GCLK_IN_TEST14 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN15.CLK_HROW_CK_GCLK_IN_TEST15 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN23.CLK_HROW_CK_GCLK_IN_TEST23 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN24.CLK_HROW_CK_GCLK_IN_TEST24 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN25.CLK_HROW_CK_GCLK_IN_TEST25 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4.CLK_HROW_CK_MUX_OUT_L4 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5.CLK_HROW_CK_MUX_OUT_L5 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4.CLK_HROW_CK_MUX_OUT_R4 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5.CLK_HROW_CK_MUX_OUT_R5 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_OUT.CLK_HROW_CK_IN_R_OUT_TEST always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0.CLK_HROW_CLK0_3 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1.CLK_HROW_CLK1_3 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0.CLK_HROW_CLK0_4 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1.CLK_HROW_CLK1_4 always

155
spartan7/ppips_cmt_top_l_lower_b.db Normal file
View File

@ -0,0 +1,155 @@
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always

234
spartan7/ppips_cmt_top_l_lower_t.db Normal file
View File

@ -0,0 +1,234 @@
CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always

325
spartan7/ppips_cmt_top_l_upper_b.db Normal file
View File

@ -0,0 +1,325 @@
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_R_PHASER_IN_C_WRCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_R_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_R_PHASER_OUT_C_RDCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDENABLE_FIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always

136
spartan7/ppips_cmt_top_l_upper_t.db Normal file
View File

@ -0,0 +1,136 @@
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always

155
spartan7/ppips_cmt_top_r_lower_b.db Normal file
View File

@ -0,0 +1,155 @@
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always

234
spartan7/ppips_cmt_top_r_lower_t.db Normal file
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@ -0,0 +1,234 @@
CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always

325
spartan7/ppips_cmt_top_r_upper_b.db Normal file
View File

@ -0,0 +1,325 @@
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_PHASER_IN_C_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_PHASER_OUT_C_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDENABLE_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always

136
spartan7/ppips_cmt_top_r_upper_t.db Normal file
View File

@ -0,0 +1,136 @@
CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always

560
spartan7/ppips_dsp_l.db Normal file
View File

@ -0,0 +1,560 @@
DSP_L.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_L.DSP_0_CEC.DSP_IMUX40_2 always
DSP_L.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_L.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_L.DSP_0_CEM.DSP_IMUX1_2 always
DSP_L.DSP_0_CEP.DSP_IMUX34_2 always
DSP_L.DSP_0_CLK.DSP_CLK0_1 always
DSP_L.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_L.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_L.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_L.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_L.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_L.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_L.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_L.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_L.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_L.DSP_0_A0.DSP_IMUX23_0 always
DSP_L.DSP_0_A1.DSP_IMUX19_0 always
DSP_L.DSP_0_A2.DSP_IMUX21_0 always
DSP_L.DSP_0_A3.DSP_IMUX17_0 always
DSP_L.DSP_0_A4.DSP_IMUX23_1 always
DSP_L.DSP_0_A5.DSP_IMUX19_1 always
DSP_L.DSP_0_A6.DSP_IMUX21_1 always
DSP_L.DSP_0_A7.DSP_IMUX17_1 always
DSP_L.DSP_0_A8.DSP_IMUX23_2 always
DSP_L.DSP_0_A9.DSP_IMUX19_2 always
DSP_L.DSP_0_A10.DSP_IMUX21_2 always
DSP_L.DSP_0_A11.DSP_IMUX17_2 always
DSP_L.DSP_0_A12.DSP_IMUX47_3 always
DSP_L.DSP_0_A13.DSP_IMUX7_3 always
DSP_L.DSP_0_A14.DSP_IMUX46_3 always
DSP_L.DSP_0_A15.DSP_IMUX6_3 always
DSP_L.DSP_0_A16.DSP_IMUX47_4 always
DSP_L.DSP_0_A17.DSP_IMUX7_4 always
DSP_L.DSP_0_A18.DSP_IMUX46_4 always
DSP_L.DSP_0_A19.DSP_IMUX6_4 always
DSP_L.DSP_0_A20.DSP_IMUX47_0 always
DSP_L.DSP_0_A21.DSP_IMUX7_0 always
DSP_L.DSP_0_A22.DSP_IMUX46_0 always
DSP_L.DSP_0_A23.DSP_IMUX6_0 always
DSP_L.DSP_0_A24.DSP_IMUX47_1 always
DSP_L.DSP_0_A25.DSP_IMUX7_1 always
DSP_L.DSP_0_A26.DSP_IMUX46_1 always
DSP_L.DSP_0_A27.DSP_IMUX6_1 always
DSP_L.DSP_0_A28.DSP_IMUX47_2 always
DSP_L.DSP_0_A29.DSP_IMUX7_2 always
DSP_L.DSP_0_ALUMODE0.DSP_IMUX21_3 always
DSP_L.DSP_0_ALUMODE1.DSP_IMUX13_3 always
DSP_L.DSP_0_B0.DSP_IMUX22_0 always
DSP_L.DSP_0_B1.DSP_IMUX34_0 always
DSP_L.DSP_0_B2.DSP_IMUX36_0 always
DSP_L.DSP_0_B3.DSP_IMUX40_0 always
DSP_L.DSP_0_B4.DSP_IMUX38_1 always
DSP_L.DSP_0_B5.DSP_IMUX18_1 always
DSP_L.DSP_0_B6.DSP_IMUX36_1 always
DSP_L.DSP_0_B7.DSP_IMUX16_1 always
DSP_L.DSP_0_B8.DSP_IMUX22_2 always
DSP_L.DSP_0_B9.DSP_IMUX18_2 always
DSP_L.DSP_0_B10.DSP_IMUX36_2 always
DSP_L.DSP_0_B11.DSP_IMUX16_2 always
DSP_L.DSP_0_B12.DSP_IMUX43_3 always
DSP_L.DSP_0_B13.DSP_IMUX3_3 always
DSP_L.DSP_0_B14.DSP_IMUX42_3 always
DSP_L.DSP_0_B15.DSP_IMUX2_3 always
DSP_L.DSP_0_B16.DSP_IMUX43_4 always
DSP_L.DSP_0_B17.DSP_IMUX3_4 always
DSP_L.DSP_0_C0.DSP_IMUX39_0 always
DSP_L.DSP_0_C1.DSP_IMUX3_0 always
DSP_L.DSP_0_C2.DSP_IMUX37_0 always
DSP_L.DSP_0_C3.DSP_IMUX1_0 always
DSP_L.DSP_0_C4.DSP_IMUX39_1 always
DSP_L.DSP_0_C5.DSP_IMUX35_1 always
DSP_L.DSP_0_C6.DSP_IMUX37_1 always
DSP_L.DSP_0_C7.DSP_IMUX33_1 always
DSP_L.DSP_0_C8.DSP_IMUX39_2 always
DSP_L.DSP_0_C9.DSP_IMUX3_2 always
DSP_L.DSP_0_C10.DSP_IMUX37_2 always
DSP_L.DSP_0_C11.DSP_IMUX33_2 always
DSP_L.DSP_0_C12.DSP_IMUX39_3 always
DSP_L.DSP_0_C13.DSP_IMUX35_3 always
DSP_L.DSP_0_C14.DSP_IMUX37_3 always
DSP_L.DSP_0_C15.DSP_IMUX33_3 always
DSP_L.DSP_0_C16.DSP_IMUX39_4 always
DSP_L.DSP_0_C17.DSP_IMUX35_4 always
DSP_L.DSP_0_C18.DSP_IMUX21_4 always
DSP_L.DSP_0_C19.DSP_IMUX1_4 always
DSP_L.DSP_0_C20.DSP_IMUX38_0 always
DSP_L.DSP_0_C21.DSP_IMUX18_0 always
DSP_L.DSP_0_C22.DSP_IMUX20_0 always
DSP_L.DSP_0_C23.DSP_IMUX32_0 always
DSP_L.DSP_0_C24.DSP_IMUX22_1 always
DSP_L.DSP_0_C25.DSP_IMUX34_1 always
DSP_L.DSP_0_C26.DSP_IMUX20_1 always
DSP_L.DSP_0_C27.DSP_IMUX32_1 always
DSP_L.DSP_0_C28.DSP_IMUX6_2 always
DSP_L.DSP_0_C29.DSP_IMUX2_2 always
DSP_L.DSP_0_C30.DSP_IMUX4_2 always
DSP_L.DSP_0_C31.DSP_IMUX32_2 always
DSP_L.DSP_0_C32.DSP_IMUX38_3 always
DSP_L.DSP_0_C33.DSP_IMUX18_3 always
DSP_L.DSP_0_C34.DSP_IMUX20_3 always
DSP_L.DSP_0_C35.DSP_IMUX32_3 always
DSP_L.DSP_0_C36.DSP_IMUX38_4 always
DSP_L.DSP_0_C37.DSP_IMUX32_4 always
DSP_L.DSP_0_C38.DSP_IMUX20_4 always
DSP_L.DSP_0_C39.DSP_IMUX18_4 always
DSP_L.DSP_0_C40.DSP_IMUX35_0 always
DSP_L.DSP_0_C41.DSP_IMUX16_0 always
DSP_L.DSP_0_C42.DSP_IMUX42_0 always
DSP_L.DSP_0_C43.DSP_IMUX33_0 always
DSP_L.DSP_0_C44.DSP_IMUX34_4 always
DSP_L.DSP_0_C45.DSP_IMUX37_4 always
DSP_L.DSP_0_C46.DSP_IMUX19_4 always
DSP_L.DSP_0_C47.DSP_IMUX33_4 always
DSP_L.DSP_0_CARRYINSEL0.DSP_IMUX30_3 always
DSP_L.DSP_0_CARRYINSEL1.DSP_IMUX14_3 always
DSP_L.DSP_0_CEA1.DSP_IMUX40_1 always
DSP_L.DSP_0_CEA2.DSP_IMUX0_1 always
DSP_L.DSP_0_CEB1.DSP_IMUX41_1 always
DSP_L.DSP_0_CEB2.DSP_IMUX1_1 always
DSP_L.DSP_0_OPMODE0.DSP_IMUX35_2 always
DSP_L.DSP_0_OPMODE1.DSP_IMUX30_2 always
DSP_L.DSP_0_OPMODE2.DSP_IMUX27_2 always
DSP_L.DSP_0_OPMODE3.DSP_IMUX38_2 always
DSP_L.DSP_0_OPMODE4.DSP_IMUX20_2 always
DSP_L.DSP_0_OPMODE5.DSP_IMUX12_2 always
DSP_L.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_L.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_L.DSP_1_CEC.DSP_IMUX34_3 always
DSP_L.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_L.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_L.DSP_1_CEM.DSP_IMUX19_3 always
DSP_L.DSP_1_CEP.DSP_IMUX26_2 always
DSP_L.DSP_1_CLK.DSP_CLK0_3 always
DSP_L.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_L.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_L.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_L.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_L.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_L.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_L.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_L.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_L.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_L.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_L.DSP_1_A0.DSP_IMUX15_0 always
DSP_L.DSP_1_A1.DSP_IMUX11_0 always
DSP_L.DSP_1_A2.DSP_IMUX13_0 always
DSP_L.DSP_1_A3.DSP_IMUX9_0 always
DSP_L.DSP_1_A4.DSP_IMUX15_1 always
DSP_L.DSP_1_A5.DSP_IMUX11_1 always
DSP_L.DSP_1_A6.DSP_IMUX13_1 always
DSP_L.DSP_1_A7.DSP_IMUX9_1 always
DSP_L.DSP_1_A8.DSP_IMUX15_2 always
DSP_L.DSP_1_A9.DSP_IMUX11_2 always
DSP_L.DSP_1_A10.DSP_IMUX13_2 always
DSP_L.DSP_1_A11.DSP_IMUX9_2 always
DSP_L.DSP_1_A12.DSP_IMUX45_3 always
DSP_L.DSP_1_A13.DSP_IMUX5_3 always
DSP_L.DSP_1_A14.DSP_IMUX44_3 always
DSP_L.DSP_1_A15.DSP_IMUX4_3 always
DSP_L.DSP_1_A16.DSP_IMUX45_4 always
DSP_L.DSP_1_A17.DSP_IMUX5_4 always
DSP_L.DSP_1_A18.DSP_IMUX44_4 always
DSP_L.DSP_1_A19.DSP_IMUX4_4 always
DSP_L.DSP_1_A20.DSP_IMUX45_0 always
DSP_L.DSP_1_A21.DSP_IMUX5_0 always
DSP_L.DSP_1_A22.DSP_IMUX44_0 always
DSP_L.DSP_1_A23.DSP_IMUX4_0 always
DSP_L.DSP_1_A24.DSP_IMUX45_1 always
DSP_L.DSP_1_A25.DSP_IMUX5_1 always
DSP_L.DSP_1_A26.DSP_IMUX44_1 always
DSP_L.DSP_1_A27.DSP_IMUX4_1 always
DSP_L.DSP_1_A28.DSP_IMUX45_2 always
DSP_L.DSP_1_A29.DSP_IMUX5_2 always
DSP_L.DSP_1_ACIN0.DSP_0_ACOUT0 always
DSP_L.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_L.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_L.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_L.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_L.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_L.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_L.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_L.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_L.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_L.DSP_1_ACIN10.DSP_0_ACOUT10 always
DSP_L.DSP_1_ACIN11.DSP_0_ACOUT11 always
DSP_L.DSP_1_ACIN12.DSP_0_ACOUT12 always
DSP_L.DSP_1_ACIN13.DSP_0_ACOUT13 always
DSP_L.DSP_1_ACIN14.DSP_0_ACOUT14 always
DSP_L.DSP_1_ACIN15.DSP_0_ACOUT15 always
DSP_L.DSP_1_ACIN16.DSP_0_ACOUT16 always
DSP_L.DSP_1_ACIN17.DSP_0_ACOUT17 always
DSP_L.DSP_1_ACIN18.DSP_0_ACOUT18 always
DSP_L.DSP_1_ACIN19.DSP_0_ACOUT19 always
DSP_L.DSP_1_ACIN20.DSP_0_ACOUT20 always
DSP_L.DSP_1_ACIN21.DSP_0_ACOUT21 always
DSP_L.DSP_1_ACIN22.DSP_0_ACOUT22 always
DSP_L.DSP_1_ACIN23.DSP_0_ACOUT23 always
DSP_L.DSP_1_ACIN24.DSP_0_ACOUT24 always
DSP_L.DSP_1_ACIN25.DSP_0_ACOUT25 always
DSP_L.DSP_1_ACIN26.DSP_0_ACOUT26 always
DSP_L.DSP_1_ACIN27.DSP_0_ACOUT27 always
DSP_L.DSP_1_ACIN28.DSP_0_ACOUT28 always
DSP_L.DSP_1_ACIN29.DSP_0_ACOUT29 always
DSP_L.DSP_1_ALUMODE0.DSP_IMUX0_4 always
DSP_L.DSP_1_ALUMODE1.DSP_IMUX40_4 always
DSP_L.DSP_1_B0.DSP_IMUX14_0 always
DSP_L.DSP_1_B1.DSP_IMUX26_0 always
DSP_L.DSP_1_B2.DSP_IMUX28_0 always
DSP_L.DSP_1_B3.DSP_IMUX0_0 always
DSP_L.DSP_1_B4.DSP_IMUX30_1 always
DSP_L.DSP_1_B5.DSP_IMUX10_1 always
DSP_L.DSP_1_B6.DSP_IMUX28_1 always
DSP_L.DSP_1_B7.DSP_IMUX8_1 always
DSP_L.DSP_1_B8.DSP_IMUX14_2 always
DSP_L.DSP_1_B9.DSP_IMUX42_2 always
DSP_L.DSP_1_B10.DSP_IMUX44_2 always
DSP_L.DSP_1_B11.DSP_IMUX8_2 always
DSP_L.DSP_1_B12.DSP_IMUX41_3 always
DSP_L.DSP_1_B13.DSP_IMUX1_3 always
DSP_L.DSP_1_B14.DSP_IMUX40_3 always
DSP_L.DSP_1_B15.DSP_IMUX0_3 always
DSP_L.DSP_1_B16.DSP_IMUX42_4 always
DSP_L.DSP_1_B17.DSP_IMUX2_4 always
DSP_L.DSP_1_BCIN0.DSP_0_BCOUT0 always
DSP_L.DSP_1_BCIN1.DSP_0_BCOUT1 always
DSP_L.DSP_1_BCIN2.DSP_0_BCOUT2 always
DSP_L.DSP_1_BCIN3.DSP_0_BCOUT3 always
DSP_L.DSP_1_BCIN4.DSP_0_BCOUT4 always
DSP_L.DSP_1_BCIN5.DSP_0_BCOUT5 always
DSP_L.DSP_1_BCIN6.DSP_0_BCOUT6 always
DSP_L.DSP_1_BCIN7.DSP_0_BCOUT7 always
DSP_L.DSP_1_BCIN8.DSP_0_BCOUT8 always
DSP_L.DSP_1_BCIN9.DSP_0_BCOUT9 always
DSP_L.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_L.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_L.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_L.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_L.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_L.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_L.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_L.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_L.DSP_1_C0.DSP_IMUX31_0 always
DSP_L.DSP_1_C1.DSP_IMUX43_0 always
DSP_L.DSP_1_C2.DSP_IMUX29_0 always
DSP_L.DSP_1_C3.DSP_IMUX41_0 always
DSP_L.DSP_1_C4.DSP_IMUX31_1 always
DSP_L.DSP_1_C5.DSP_IMUX27_1 always
DSP_L.DSP_1_C6.DSP_IMUX29_1 always
DSP_L.DSP_1_C7.DSP_IMUX25_1 always
DSP_L.DSP_1_C8.DSP_IMUX31_2 always
DSP_L.DSP_1_C9.DSP_IMUX43_2 always
DSP_L.DSP_1_C10.DSP_IMUX29_2 always
DSP_L.DSP_1_C11.DSP_IMUX25_2 always
DSP_L.DSP_1_C12.DSP_IMUX31_3 always
DSP_L.DSP_1_C13.DSP_IMUX27_3 always
DSP_L.DSP_1_C14.DSP_IMUX29_3 always
DSP_L.DSP_1_C15.DSP_IMUX25_3 always
DSP_L.DSP_1_C16.DSP_IMUX31_4 always
DSP_L.DSP_1_C17.DSP_IMUX27_4 always
DSP_L.DSP_1_C18.DSP_IMUX13_4 always
DSP_L.DSP_1_C19.DSP_IMUX41_4 always
DSP_L.DSP_1_C20.DSP_IMUX30_0 always
DSP_L.DSP_1_C21.DSP_IMUX10_0 always
DSP_L.DSP_1_C22.DSP_IMUX12_0 always
DSP_L.DSP_1_C23.DSP_IMUX24_0 always
DSP_L.DSP_1_C24.DSP_IMUX14_1 always
DSP_L.DSP_1_C25.DSP_IMUX26_1 always
DSP_L.DSP_1_C26.DSP_IMUX12_1 always
DSP_L.DSP_1_C27.DSP_IMUX24_1 always
DSP_L.DSP_1_C28.DSP_IMUX46_2 always
DSP_L.DSP_1_C29.DSP_IMUX10_2 always
DSP_L.DSP_1_C30.DSP_IMUX28_2 always
DSP_L.DSP_1_C31.DSP_IMUX24_2 always
DSP_L.DSP_1_C32.DSP_IMUX22_3 always
DSP_L.DSP_1_C33.DSP_IMUX10_3 always
DSP_L.DSP_1_C34.DSP_IMUX12_3 always
DSP_L.DSP_1_C35.DSP_IMUX24_3 always
DSP_L.DSP_1_C36.DSP_IMUX30_4 always
DSP_L.DSP_1_C37.DSP_IMUX24_4 always
DSP_L.DSP_1_C38.DSP_IMUX12_4 always
DSP_L.DSP_1_C39.DSP_IMUX10_4 always
DSP_L.DSP_1_C40.DSP_IMUX27_0 always
DSP_L.DSP_1_C41.DSP_IMUX8_0 always
DSP_L.DSP_1_C42.DSP_IMUX2_0 always
DSP_L.DSP_1_C43.DSP_IMUX25_0 always
DSP_L.DSP_1_C44.DSP_IMUX26_4 always
DSP_L.DSP_1_C45.DSP_IMUX29_4 always
DSP_L.DSP_1_C46.DSP_IMUX11_4 always
DSP_L.DSP_1_C47.DSP_IMUX25_4 always
DSP_L.DSP_1_CARRYINSEL0.DSP_IMUX36_4 always
DSP_L.DSP_1_CARRYINSEL1.DSP_IMUX28_4 always
DSP_L.DSP_1_CEA1.DSP_IMUX9_3 always
DSP_L.DSP_1_CEA2.DSP_IMUX17_3 always
DSP_L.DSP_1_CEB1.DSP_IMUX8_3 always
DSP_L.DSP_1_CEB2.DSP_IMUX16_3 always
DSP_L.DSP_1_OPMODE0.DSP_IMUX28_3 always
DSP_L.DSP_1_OPMODE1.DSP_IMUX8_4 always
DSP_L.DSP_1_OPMODE2.DSP_IMUX36_3 always
DSP_L.DSP_1_OPMODE3.DSP_IMUX16_4 always
DSP_L.DSP_1_OPMODE4.DSP_IMUX17_4 always
DSP_L.DSP_1_OPMODE5.DSP_IMUX9_4 always
DSP_L.DSP_1_PCIN0.DSP_0_PCOUT0 always
DSP_L.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_L.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_L.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_L.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_L.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_L.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_L.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_L.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_L.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_L.DSP_1_PCIN10.DSP_0_PCOUT10 always
DSP_L.DSP_1_PCIN11.DSP_0_PCOUT11 always
DSP_L.DSP_1_PCIN12.DSP_0_PCOUT12 always
DSP_L.DSP_1_PCIN13.DSP_0_PCOUT13 always
DSP_L.DSP_1_PCIN14.DSP_0_PCOUT14 always
DSP_L.DSP_1_PCIN15.DSP_0_PCOUT15 always
DSP_L.DSP_1_PCIN16.DSP_0_PCOUT16 always
DSP_L.DSP_1_PCIN17.DSP_0_PCOUT17 always
DSP_L.DSP_1_PCIN18.DSP_0_PCOUT18 always
DSP_L.DSP_1_PCIN19.DSP_0_PCOUT19 always
DSP_L.DSP_1_PCIN20.DSP_0_PCOUT20 always
DSP_L.DSP_1_PCIN21.DSP_0_PCOUT21 always
DSP_L.DSP_1_PCIN22.DSP_0_PCOUT22 always
DSP_L.DSP_1_PCIN23.DSP_0_PCOUT23 always
DSP_L.DSP_1_PCIN24.DSP_0_PCOUT24 always
DSP_L.DSP_1_PCIN25.DSP_0_PCOUT25 always
DSP_L.DSP_1_PCIN26.DSP_0_PCOUT26 always
DSP_L.DSP_1_PCIN27.DSP_0_PCOUT27 always
DSP_L.DSP_1_PCIN28.DSP_0_PCOUT28 always
DSP_L.DSP_1_PCIN29.DSP_0_PCOUT29 always
DSP_L.DSP_1_PCIN30.DSP_0_PCOUT30 always
DSP_L.DSP_1_PCIN31.DSP_0_PCOUT31 always
DSP_L.DSP_1_PCIN32.DSP_0_PCOUT32 always
DSP_L.DSP_1_PCIN33.DSP_0_PCOUT33 always
DSP_L.DSP_1_PCIN34.DSP_0_PCOUT34 always
DSP_L.DSP_1_PCIN35.DSP_0_PCOUT35 always
DSP_L.DSP_1_PCIN36.DSP_0_PCOUT36 always
DSP_L.DSP_1_PCIN37.DSP_0_PCOUT37 always
DSP_L.DSP_1_PCIN38.DSP_0_PCOUT38 always
DSP_L.DSP_1_PCIN39.DSP_0_PCOUT39 always
DSP_L.DSP_1_PCIN40.DSP_0_PCOUT40 always
DSP_L.DSP_1_PCIN41.DSP_0_PCOUT41 always
DSP_L.DSP_1_PCIN42.DSP_0_PCOUT42 always
DSP_L.DSP_1_PCIN43.DSP_0_PCOUT43 always
DSP_L.DSP_1_PCIN44.DSP_0_PCOUT44 always
DSP_L.DSP_1_PCIN45.DSP_0_PCOUT45 always
DSP_L.DSP_1_PCIN46.DSP_0_PCOUT46 always
DSP_L.DSP_1_PCIN47.DSP_0_PCOUT47 always
DSP_L.DSP_CARRYCASCOUT.DSP_1_CARRYCASCOUT always
DSP_L.DSP_LOGIC_OUTS_B0_0.DSP_1_P23 always
DSP_L.DSP_LOGIC_OUTS_B0_1.DSP_1_P27 always
DSP_L.DSP_LOGIC_OUTS_B0_2.DSP_1_P31 always
DSP_L.DSP_LOGIC_OUTS_B0_3.DSP_1_P35 always
DSP_L.DSP_LOGIC_OUTS_B0_4.DSP_1_P37 always
DSP_L.DSP_LOGIC_OUTS_B1_0.DSP_1_P1 always
DSP_L.DSP_LOGIC_OUTS_B1_1.DSP_1_P5 always
DSP_L.DSP_LOGIC_OUTS_B1_2.DSP_1_P9 always
DSP_L.DSP_LOGIC_OUTS_B1_3.DSP_1_P13 always
DSP_L.DSP_LOGIC_OUTS_B1_4.DSP_1_P17 always
DSP_L.DSP_LOGIC_OUTS_B2_0.DSP_1_P22 always
DSP_L.DSP_LOGIC_OUTS_B2_1.DSP_1_P26 always
DSP_L.DSP_LOGIC_OUTS_B2_2.DSP_1_P30 always
DSP_L.DSP_LOGIC_OUTS_B2_3.DSP_1_P34 always
DSP_L.DSP_LOGIC_OUTS_B2_4.DSP_1_P38 always
DSP_L.DSP_LOGIC_OUTS_B3_0.DSP_1_P0 always
DSP_L.DSP_LOGIC_OUTS_B3_1.DSP_1_P4 always
DSP_L.DSP_LOGIC_OUTS_B3_2.DSP_1_P8 always
DSP_L.DSP_LOGIC_OUTS_B3_3.DSP_1_P12 always
DSP_L.DSP_LOGIC_OUTS_B3_4.DSP_1_P16 always
DSP_L.DSP_LOGIC_OUTS_B4_0.DSP_1_P3 always
DSP_L.DSP_LOGIC_OUTS_B4_1.DSP_1_P7 always
DSP_L.DSP_LOGIC_OUTS_B4_2.DSP_1_P11 always
DSP_L.DSP_LOGIC_OUTS_B4_3.DSP_1_P15 always
DSP_L.DSP_LOGIC_OUTS_B4_4.DSP_1_P19 always
DSP_L.DSP_LOGIC_OUTS_B5_0.DSP_1_P21 always
DSP_L.DSP_LOGIC_OUTS_B5_1.DSP_1_P25 always
DSP_L.DSP_LOGIC_OUTS_B5_2.DSP_1_P29 always
DSP_L.DSP_LOGIC_OUTS_B5_3.DSP_1_P33 always
DSP_L.DSP_LOGIC_OUTS_B5_4.DSP_1_P39 always
DSP_L.DSP_LOGIC_OUTS_B6_0.DSP_1_P2 always
DSP_L.DSP_LOGIC_OUTS_B6_1.DSP_1_P6 always
DSP_L.DSP_LOGIC_OUTS_B6_2.DSP_1_P10 always
DSP_L.DSP_LOGIC_OUTS_B6_3.DSP_1_P14 always
DSP_L.DSP_LOGIC_OUTS_B6_4.DSP_1_P18 always
DSP_L.DSP_LOGIC_OUTS_B7_0.DSP_1_P20 always
DSP_L.DSP_LOGIC_OUTS_B7_1.DSP_1_P24 always
DSP_L.DSP_LOGIC_OUTS_B7_2.DSP_1_P28 always
DSP_L.DSP_LOGIC_OUTS_B7_3.DSP_1_P32 always
DSP_L.DSP_LOGIC_OUTS_B7_4.DSP_1_P36 always
DSP_L.DSP_LOGIC_OUTS_B8_0.DSP_0_P43 always
DSP_L.DSP_LOGIC_OUTS_B8_2.DSP_1_OVERFLOW always
DSP_L.DSP_LOGIC_OUTS_B8_3.DSP_1_CARRYOUT0 always
DSP_L.DSP_LOGIC_OUTS_B8_4.DSP_0_P47 always
DSP_L.DSP_LOGIC_OUTS_B9_0.DSP_0_P42 always
DSP_L.DSP_LOGIC_OUTS_B9_2.DSP_0_UNDERFLOW always
DSP_L.DSP_LOGIC_OUTS_B9_4.DSP_0_P44 always
DSP_L.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_L.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_L.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_L.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_L.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_L.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_L.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_L.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_L.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_L.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_L.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_L.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_L.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_L.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_L.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_L.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_L.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_L.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_L.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_L.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_L.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_L.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_L.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_L.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_L.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_L.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_L.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_L.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_L.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_L.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_L.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_L.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_L.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_L.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_L.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_L.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_L.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_L.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_L.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_L.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_L.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_L.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_L.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_L.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_L.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_L.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_L.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_L.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_L.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_L.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_L.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_L.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_L.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_L.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_L.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_L.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_L.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_L.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_L.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_L.DSP_MULTSIGNOUT.DSP_1_MULTSIGNOUT always
DSP_L.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_L.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_L.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_L.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_L.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_L.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_L.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_L.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_L.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_L.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_L.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_L.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_L.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_L.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_L.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_L.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_L.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_L.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_L.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_L.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_L.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_L.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_L.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_L.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_L.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_L.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_L.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_L.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_L.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_L.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_L.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_L.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_L.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_L.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_L.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_L.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_L.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_L.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_L.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_L.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_L.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_L.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_L.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_L.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_L.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_L.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_L.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_L.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_L.DSP_PCOUT0.DSP_1_PCOUT0 always
DSP_L.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_L.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_L.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_L.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_L.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_L.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_L.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_L.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_L.DSP_PCOUT9.DSP_1_PCOUT9 always
DSP_L.DSP_PCOUT10.DSP_1_PCOUT10 always
DSP_L.DSP_PCOUT11.DSP_1_PCOUT11 always
DSP_L.DSP_PCOUT12.DSP_1_PCOUT12 always
DSP_L.DSP_PCOUT13.DSP_1_PCOUT13 always
DSP_L.DSP_PCOUT14.DSP_1_PCOUT14 always
DSP_L.DSP_PCOUT15.DSP_1_PCOUT15 always
DSP_L.DSP_PCOUT16.DSP_1_PCOUT16 always
DSP_L.DSP_PCOUT17.DSP_1_PCOUT17 always
DSP_L.DSP_PCOUT18.DSP_1_PCOUT18 always
DSP_L.DSP_PCOUT19.DSP_1_PCOUT19 always
DSP_L.DSP_PCOUT20.DSP_1_PCOUT20 always
DSP_L.DSP_PCOUT21.DSP_1_PCOUT21 always
DSP_L.DSP_PCOUT22.DSP_1_PCOUT22 always
DSP_L.DSP_PCOUT23.DSP_1_PCOUT23 always
DSP_L.DSP_PCOUT24.DSP_1_PCOUT24 always
DSP_L.DSP_PCOUT25.DSP_1_PCOUT25 always
DSP_L.DSP_PCOUT26.DSP_1_PCOUT26 always
DSP_L.DSP_PCOUT27.DSP_1_PCOUT27 always
DSP_L.DSP_PCOUT28.DSP_1_PCOUT28 always
DSP_L.DSP_PCOUT29.DSP_1_PCOUT29 always
DSP_L.DSP_PCOUT30.DSP_1_PCOUT30 always
DSP_L.DSP_PCOUT31.DSP_1_PCOUT31 always
DSP_L.DSP_PCOUT32.DSP_1_PCOUT32 always
DSP_L.DSP_PCOUT33.DSP_1_PCOUT33 always
DSP_L.DSP_PCOUT34.DSP_1_PCOUT34 always
DSP_L.DSP_PCOUT35.DSP_1_PCOUT35 always
DSP_L.DSP_PCOUT36.DSP_1_PCOUT36 always
DSP_L.DSP_PCOUT37.DSP_1_PCOUT37 always
DSP_L.DSP_PCOUT38.DSP_1_PCOUT38 always
DSP_L.DSP_PCOUT39.DSP_1_PCOUT39 always
DSP_L.DSP_PCOUT40.DSP_1_PCOUT40 always
DSP_L.DSP_PCOUT41.DSP_1_PCOUT41 always
DSP_L.DSP_PCOUT42.DSP_1_PCOUT42 always
DSP_L.DSP_PCOUT43.DSP_1_PCOUT43 always
DSP_L.DSP_PCOUT44.DSP_1_PCOUT44 always
DSP_L.DSP_PCOUT45.DSP_1_PCOUT45 always
DSP_L.DSP_PCOUT46.DSP_1_PCOUT46 always
DSP_L.DSP_PCOUT47.DSP_1_PCOUT47 always

0
spartan7/ppips_dsp_l.origin_info.db Normal file
View File

560
spartan7/ppips_dsp_r.db Normal file
View File

@ -0,0 +1,560 @@
DSP_R.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_R.DSP_0_CEC.DSP_IMUX40_2 always
DSP_R.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_R.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_R.DSP_0_CEM.DSP_IMUX1_2 always
DSP_R.DSP_0_CEP.DSP_IMUX34_2 always
DSP_R.DSP_0_CLK.DSP_CLK0_1 always
DSP_R.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_R.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_R.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_R.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_R.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_R.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_R.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_R.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_R.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_R.DSP_0_A0.DSP_IMUX23_0 always
DSP_R.DSP_0_A1.DSP_IMUX19_0 always
DSP_R.DSP_0_A2.DSP_IMUX21_0 always
DSP_R.DSP_0_A3.DSP_IMUX17_0 always
DSP_R.DSP_0_A4.DSP_IMUX23_1 always
DSP_R.DSP_0_A5.DSP_IMUX19_1 always
DSP_R.DSP_0_A6.DSP_IMUX21_1 always
DSP_R.DSP_0_A7.DSP_IMUX17_1 always
DSP_R.DSP_0_A8.DSP_IMUX23_2 always
DSP_R.DSP_0_A9.DSP_IMUX19_2 always
DSP_R.DSP_0_A10.DSP_IMUX21_2 always
DSP_R.DSP_0_A11.DSP_IMUX17_2 always
DSP_R.DSP_0_A12.DSP_IMUX47_3 always
DSP_R.DSP_0_A13.DSP_IMUX7_3 always
DSP_R.DSP_0_A14.DSP_IMUX46_3 always
DSP_R.DSP_0_A15.DSP_IMUX6_3 always
DSP_R.DSP_0_A16.DSP_IMUX47_4 always
DSP_R.DSP_0_A17.DSP_IMUX7_4 always
DSP_R.DSP_0_A18.DSP_IMUX46_4 always
DSP_R.DSP_0_A19.DSP_IMUX6_4 always
DSP_R.DSP_0_A20.DSP_IMUX47_0 always
DSP_R.DSP_0_A21.DSP_IMUX7_0 always
DSP_R.DSP_0_A22.DSP_IMUX46_0 always
DSP_R.DSP_0_A23.DSP_IMUX6_0 always
DSP_R.DSP_0_A24.DSP_IMUX47_1 always
DSP_R.DSP_0_A25.DSP_IMUX7_1 always
DSP_R.DSP_0_A26.DSP_IMUX46_1 always
DSP_R.DSP_0_A27.DSP_IMUX6_1 always
DSP_R.DSP_0_A28.DSP_IMUX47_2 always
DSP_R.DSP_0_A29.DSP_IMUX7_2 always
DSP_R.DSP_0_ALUMODE0.DSP_IMUX21_3 always
DSP_R.DSP_0_ALUMODE1.DSP_IMUX13_3 always
DSP_R.DSP_0_B0.DSP_IMUX22_0 always
DSP_R.DSP_0_B1.DSP_IMUX34_0 always
DSP_R.DSP_0_B2.DSP_IMUX36_0 always
DSP_R.DSP_0_B3.DSP_IMUX40_0 always
DSP_R.DSP_0_B4.DSP_IMUX38_1 always
DSP_R.DSP_0_B5.DSP_IMUX18_1 always
DSP_R.DSP_0_B6.DSP_IMUX36_1 always
DSP_R.DSP_0_B7.DSP_IMUX16_1 always
DSP_R.DSP_0_B8.DSP_IMUX22_2 always
DSP_R.DSP_0_B9.DSP_IMUX18_2 always
DSP_R.DSP_0_B10.DSP_IMUX36_2 always
DSP_R.DSP_0_B11.DSP_IMUX16_2 always
DSP_R.DSP_0_B12.DSP_IMUX43_3 always
DSP_R.DSP_0_B13.DSP_IMUX3_3 always
DSP_R.DSP_0_B14.DSP_IMUX42_3 always
DSP_R.DSP_0_B15.DSP_IMUX2_3 always
DSP_R.DSP_0_B16.DSP_IMUX43_4 always
DSP_R.DSP_0_B17.DSP_IMUX3_4 always
DSP_R.DSP_0_C0.DSP_IMUX39_0 always
DSP_R.DSP_0_C1.DSP_IMUX3_0 always
DSP_R.DSP_0_C2.DSP_IMUX37_0 always
DSP_R.DSP_0_C3.DSP_IMUX1_0 always
DSP_R.DSP_0_C4.DSP_IMUX39_1 always
DSP_R.DSP_0_C5.DSP_IMUX35_1 always
DSP_R.DSP_0_C6.DSP_IMUX37_1 always
DSP_R.DSP_0_C7.DSP_IMUX33_1 always
DSP_R.DSP_0_C8.DSP_IMUX39_2 always
DSP_R.DSP_0_C9.DSP_IMUX3_2 always
DSP_R.DSP_0_C10.DSP_IMUX37_2 always
DSP_R.DSP_0_C11.DSP_IMUX33_2 always
DSP_R.DSP_0_C12.DSP_IMUX39_3 always
DSP_R.DSP_0_C13.DSP_IMUX35_3 always
DSP_R.DSP_0_C14.DSP_IMUX37_3 always
DSP_R.DSP_0_C15.DSP_IMUX33_3 always
DSP_R.DSP_0_C16.DSP_IMUX39_4 always
DSP_R.DSP_0_C17.DSP_IMUX35_4 always
DSP_R.DSP_0_C18.DSP_IMUX21_4 always
DSP_R.DSP_0_C19.DSP_IMUX1_4 always
DSP_R.DSP_0_C20.DSP_IMUX38_0 always
DSP_R.DSP_0_C21.DSP_IMUX18_0 always
DSP_R.DSP_0_C22.DSP_IMUX20_0 always
DSP_R.DSP_0_C23.DSP_IMUX32_0 always
DSP_R.DSP_0_C24.DSP_IMUX22_1 always
DSP_R.DSP_0_C25.DSP_IMUX34_1 always
DSP_R.DSP_0_C26.DSP_IMUX20_1 always
DSP_R.DSP_0_C27.DSP_IMUX32_1 always
DSP_R.DSP_0_C28.DSP_IMUX6_2 always
DSP_R.DSP_0_C29.DSP_IMUX2_2 always
DSP_R.DSP_0_C30.DSP_IMUX4_2 always
DSP_R.DSP_0_C31.DSP_IMUX32_2 always
DSP_R.DSP_0_C32.DSP_IMUX38_3 always
DSP_R.DSP_0_C33.DSP_IMUX18_3 always
DSP_R.DSP_0_C34.DSP_IMUX20_3 always
DSP_R.DSP_0_C35.DSP_IMUX32_3 always
DSP_R.DSP_0_C36.DSP_IMUX38_4 always
DSP_R.DSP_0_C37.DSP_IMUX32_4 always
DSP_R.DSP_0_C38.DSP_IMUX20_4 always
DSP_R.DSP_0_C39.DSP_IMUX18_4 always
DSP_R.DSP_0_C40.DSP_IMUX35_0 always
DSP_R.DSP_0_C41.DSP_IMUX16_0 always
DSP_R.DSP_0_C42.DSP_IMUX42_0 always
DSP_R.DSP_0_C43.DSP_IMUX33_0 always
DSP_R.DSP_0_C44.DSP_IMUX34_4 always
DSP_R.DSP_0_C45.DSP_IMUX37_4 always
DSP_R.DSP_0_C46.DSP_IMUX19_4 always
DSP_R.DSP_0_C47.DSP_IMUX33_4 always
DSP_R.DSP_0_CARRYINSEL0.DSP_IMUX30_3 always
DSP_R.DSP_0_CARRYINSEL1.DSP_IMUX14_3 always
DSP_R.DSP_0_CEA1.DSP_IMUX40_1 always
DSP_R.DSP_0_CEA2.DSP_IMUX0_1 always
DSP_R.DSP_0_CEB1.DSP_IMUX41_1 always
DSP_R.DSP_0_CEB2.DSP_IMUX1_1 always
DSP_R.DSP_0_OPMODE0.DSP_IMUX35_2 always
DSP_R.DSP_0_OPMODE1.DSP_IMUX30_2 always
DSP_R.DSP_0_OPMODE2.DSP_IMUX27_2 always
DSP_R.DSP_0_OPMODE3.DSP_IMUX38_2 always
DSP_R.DSP_0_OPMODE4.DSP_IMUX20_2 always
DSP_R.DSP_0_OPMODE5.DSP_IMUX12_2 always
DSP_R.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_R.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_R.DSP_1_CEC.DSP_IMUX34_3 always
DSP_R.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_R.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_R.DSP_1_CEM.DSP_IMUX19_3 always
DSP_R.DSP_1_CEP.DSP_IMUX26_2 always
DSP_R.DSP_1_CLK.DSP_CLK0_3 always
DSP_R.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_R.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_R.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_R.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_R.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_R.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_R.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_R.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_R.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_R.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_R.DSP_1_A0.DSP_IMUX15_0 always
DSP_R.DSP_1_A1.DSP_IMUX11_0 always
DSP_R.DSP_1_A2.DSP_IMUX13_0 always
DSP_R.DSP_1_A3.DSP_IMUX9_0 always
DSP_R.DSP_1_A4.DSP_IMUX15_1 always
DSP_R.DSP_1_A5.DSP_IMUX11_1 always
DSP_R.DSP_1_A6.DSP_IMUX13_1 always
DSP_R.DSP_1_A7.DSP_IMUX9_1 always
DSP_R.DSP_1_A8.DSP_IMUX15_2 always
DSP_R.DSP_1_A9.DSP_IMUX11_2 always
DSP_R.DSP_1_A10.DSP_IMUX13_2 always
DSP_R.DSP_1_A11.DSP_IMUX9_2 always
DSP_R.DSP_1_A12.DSP_IMUX45_3 always
DSP_R.DSP_1_A13.DSP_IMUX5_3 always
DSP_R.DSP_1_A14.DSP_IMUX44_3 always
DSP_R.DSP_1_A15.DSP_IMUX4_3 always
DSP_R.DSP_1_A16.DSP_IMUX45_4 always
DSP_R.DSP_1_A17.DSP_IMUX5_4 always
DSP_R.DSP_1_A18.DSP_IMUX44_4 always
DSP_R.DSP_1_A19.DSP_IMUX4_4 always
DSP_R.DSP_1_A20.DSP_IMUX45_0 always
DSP_R.DSP_1_A21.DSP_IMUX5_0 always
DSP_R.DSP_1_A22.DSP_IMUX44_0 always
DSP_R.DSP_1_A23.DSP_IMUX4_0 always
DSP_R.DSP_1_A24.DSP_IMUX45_1 always
DSP_R.DSP_1_A25.DSP_IMUX5_1 always
DSP_R.DSP_1_A26.DSP_IMUX44_1 always
DSP_R.DSP_1_A27.DSP_IMUX4_1 always
DSP_R.DSP_1_A28.DSP_IMUX45_2 always
DSP_R.DSP_1_A29.DSP_IMUX5_2 always
DSP_R.DSP_1_ACIN0.DSP_0_ACOUT0 always
DSP_R.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_R.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_R.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_R.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_R.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_R.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_R.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_R.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_R.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_R.DSP_1_ACIN10.DSP_0_ACOUT10 always
DSP_R.DSP_1_ACIN11.DSP_0_ACOUT11 always
DSP_R.DSP_1_ACIN12.DSP_0_ACOUT12 always
DSP_R.DSP_1_ACIN13.DSP_0_ACOUT13 always
DSP_R.DSP_1_ACIN14.DSP_0_ACOUT14 always
DSP_R.DSP_1_ACIN15.DSP_0_ACOUT15 always
DSP_R.DSP_1_ACIN16.DSP_0_ACOUT16 always
DSP_R.DSP_1_ACIN17.DSP_0_ACOUT17 always
DSP_R.DSP_1_ACIN18.DSP_0_ACOUT18 always
DSP_R.DSP_1_ACIN19.DSP_0_ACOUT19 always
DSP_R.DSP_1_ACIN20.DSP_0_ACOUT20 always
DSP_R.DSP_1_ACIN21.DSP_0_ACOUT21 always
DSP_R.DSP_1_ACIN22.DSP_0_ACOUT22 always
DSP_R.DSP_1_ACIN23.DSP_0_ACOUT23 always
DSP_R.DSP_1_ACIN24.DSP_0_ACOUT24 always
DSP_R.DSP_1_ACIN25.DSP_0_ACOUT25 always
DSP_R.DSP_1_ACIN26.DSP_0_ACOUT26 always
DSP_R.DSP_1_ACIN27.DSP_0_ACOUT27 always
DSP_R.DSP_1_ACIN28.DSP_0_ACOUT28 always
DSP_R.DSP_1_ACIN29.DSP_0_ACOUT29 always
DSP_R.DSP_1_ALUMODE0.DSP_IMUX0_4 always
DSP_R.DSP_1_ALUMODE1.DSP_IMUX40_4 always
DSP_R.DSP_1_B0.DSP_IMUX14_0 always
DSP_R.DSP_1_B1.DSP_IMUX26_0 always
DSP_R.DSP_1_B2.DSP_IMUX28_0 always
DSP_R.DSP_1_B3.DSP_IMUX0_0 always
DSP_R.DSP_1_B4.DSP_IMUX30_1 always
DSP_R.DSP_1_B5.DSP_IMUX10_1 always
DSP_R.DSP_1_B6.DSP_IMUX28_1 always
DSP_R.DSP_1_B7.DSP_IMUX8_1 always
DSP_R.DSP_1_B8.DSP_IMUX14_2 always
DSP_R.DSP_1_B9.DSP_IMUX42_2 always
DSP_R.DSP_1_B10.DSP_IMUX44_2 always
DSP_R.DSP_1_B11.DSP_IMUX8_2 always
DSP_R.DSP_1_B12.DSP_IMUX41_3 always
DSP_R.DSP_1_B13.DSP_IMUX1_3 always
DSP_R.DSP_1_B14.DSP_IMUX40_3 always
DSP_R.DSP_1_B15.DSP_IMUX0_3 always
DSP_R.DSP_1_B16.DSP_IMUX42_4 always
DSP_R.DSP_1_B17.DSP_IMUX2_4 always
DSP_R.DSP_1_BCIN0.DSP_0_BCOUT0 always
DSP_R.DSP_1_BCIN1.DSP_0_BCOUT1 always
DSP_R.DSP_1_BCIN2.DSP_0_BCOUT2 always
DSP_R.DSP_1_BCIN3.DSP_0_BCOUT3 always
DSP_R.DSP_1_BCIN4.DSP_0_BCOUT4 always
DSP_R.DSP_1_BCIN5.DSP_0_BCOUT5 always
DSP_R.DSP_1_BCIN6.DSP_0_BCOUT6 always
DSP_R.DSP_1_BCIN7.DSP_0_BCOUT7 always
DSP_R.DSP_1_BCIN8.DSP_0_BCOUT8 always
DSP_R.DSP_1_BCIN9.DSP_0_BCOUT9 always
DSP_R.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_R.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_R.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_R.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_R.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_R.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_R.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_R.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_R.DSP_1_C0.DSP_IMUX31_0 always
DSP_R.DSP_1_C1.DSP_IMUX43_0 always
DSP_R.DSP_1_C2.DSP_IMUX29_0 always
DSP_R.DSP_1_C3.DSP_IMUX41_0 always
DSP_R.DSP_1_C4.DSP_IMUX31_1 always
DSP_R.DSP_1_C5.DSP_IMUX27_1 always
DSP_R.DSP_1_C6.DSP_IMUX29_1 always
DSP_R.DSP_1_C7.DSP_IMUX25_1 always
DSP_R.DSP_1_C8.DSP_IMUX31_2 always
DSP_R.DSP_1_C9.DSP_IMUX43_2 always
DSP_R.DSP_1_C10.DSP_IMUX29_2 always
DSP_R.DSP_1_C11.DSP_IMUX25_2 always
DSP_R.DSP_1_C12.DSP_IMUX31_3 always
DSP_R.DSP_1_C13.DSP_IMUX27_3 always
DSP_R.DSP_1_C14.DSP_IMUX29_3 always
DSP_R.DSP_1_C15.DSP_IMUX25_3 always
DSP_R.DSP_1_C16.DSP_IMUX31_4 always
DSP_R.DSP_1_C17.DSP_IMUX27_4 always
DSP_R.DSP_1_C18.DSP_IMUX13_4 always
DSP_R.DSP_1_C19.DSP_IMUX41_4 always
DSP_R.DSP_1_C20.DSP_IMUX30_0 always
DSP_R.DSP_1_C21.DSP_IMUX10_0 always
DSP_R.DSP_1_C22.DSP_IMUX12_0 always
DSP_R.DSP_1_C23.DSP_IMUX24_0 always
DSP_R.DSP_1_C24.DSP_IMUX14_1 always
DSP_R.DSP_1_C25.DSP_IMUX26_1 always
DSP_R.DSP_1_C26.DSP_IMUX12_1 always
DSP_R.DSP_1_C27.DSP_IMUX24_1 always
DSP_R.DSP_1_C28.DSP_IMUX46_2 always
DSP_R.DSP_1_C29.DSP_IMUX10_2 always
DSP_R.DSP_1_C30.DSP_IMUX28_2 always
DSP_R.DSP_1_C31.DSP_IMUX24_2 always
DSP_R.DSP_1_C32.DSP_IMUX22_3 always
DSP_R.DSP_1_C33.DSP_IMUX10_3 always
DSP_R.DSP_1_C34.DSP_IMUX12_3 always
DSP_R.DSP_1_C35.DSP_IMUX24_3 always
DSP_R.DSP_1_C36.DSP_IMUX30_4 always
DSP_R.DSP_1_C37.DSP_IMUX24_4 always
DSP_R.DSP_1_C38.DSP_IMUX12_4 always
DSP_R.DSP_1_C39.DSP_IMUX10_4 always
DSP_R.DSP_1_C40.DSP_IMUX27_0 always
DSP_R.DSP_1_C41.DSP_IMUX8_0 always
DSP_R.DSP_1_C42.DSP_IMUX2_0 always
DSP_R.DSP_1_C43.DSP_IMUX25_0 always
DSP_R.DSP_1_C44.DSP_IMUX26_4 always
DSP_R.DSP_1_C45.DSP_IMUX29_4 always
DSP_R.DSP_1_C46.DSP_IMUX11_4 always
DSP_R.DSP_1_C47.DSP_IMUX25_4 always
DSP_R.DSP_1_CARRYINSEL0.DSP_IMUX36_4 always
DSP_R.DSP_1_CARRYINSEL1.DSP_IMUX28_4 always
DSP_R.DSP_1_CEA1.DSP_IMUX9_3 always
DSP_R.DSP_1_CEA2.DSP_IMUX17_3 always
DSP_R.DSP_1_CEB1.DSP_IMUX8_3 always
DSP_R.DSP_1_CEB2.DSP_IMUX16_3 always
DSP_R.DSP_1_OPMODE0.DSP_IMUX28_3 always
DSP_R.DSP_1_OPMODE1.DSP_IMUX8_4 always
DSP_R.DSP_1_OPMODE2.DSP_IMUX36_3 always
DSP_R.DSP_1_OPMODE3.DSP_IMUX16_4 always
DSP_R.DSP_1_OPMODE4.DSP_IMUX17_4 always
DSP_R.DSP_1_OPMODE5.DSP_IMUX9_4 always
DSP_R.DSP_1_PCIN0.DSP_0_PCOUT0 always
DSP_R.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_R.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_R.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_R.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_R.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_R.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_R.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_R.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_R.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_R.DSP_1_PCIN10.DSP_0_PCOUT10 always
DSP_R.DSP_1_PCIN11.DSP_0_PCOUT11 always
DSP_R.DSP_1_PCIN12.DSP_0_PCOUT12 always
DSP_R.DSP_1_PCIN13.DSP_0_PCOUT13 always
DSP_R.DSP_1_PCIN14.DSP_0_PCOUT14 always
DSP_R.DSP_1_PCIN15.DSP_0_PCOUT15 always
DSP_R.DSP_1_PCIN16.DSP_0_PCOUT16 always
DSP_R.DSP_1_PCIN17.DSP_0_PCOUT17 always
DSP_R.DSP_1_PCIN18.DSP_0_PCOUT18 always
DSP_R.DSP_1_PCIN19.DSP_0_PCOUT19 always
DSP_R.DSP_1_PCIN20.DSP_0_PCOUT20 always
DSP_R.DSP_1_PCIN21.DSP_0_PCOUT21 always
DSP_R.DSP_1_PCIN22.DSP_0_PCOUT22 always
DSP_R.DSP_1_PCIN23.DSP_0_PCOUT23 always
DSP_R.DSP_1_PCIN24.DSP_0_PCOUT24 always
DSP_R.DSP_1_PCIN25.DSP_0_PCOUT25 always
DSP_R.DSP_1_PCIN26.DSP_0_PCOUT26 always
DSP_R.DSP_1_PCIN27.DSP_0_PCOUT27 always
DSP_R.DSP_1_PCIN28.DSP_0_PCOUT28 always
DSP_R.DSP_1_PCIN29.DSP_0_PCOUT29 always
DSP_R.DSP_1_PCIN30.DSP_0_PCOUT30 always
DSP_R.DSP_1_PCIN31.DSP_0_PCOUT31 always
DSP_R.DSP_1_PCIN32.DSP_0_PCOUT32 always
DSP_R.DSP_1_PCIN33.DSP_0_PCOUT33 always
DSP_R.DSP_1_PCIN34.DSP_0_PCOUT34 always
DSP_R.DSP_1_PCIN35.DSP_0_PCOUT35 always
DSP_R.DSP_1_PCIN36.DSP_0_PCOUT36 always
DSP_R.DSP_1_PCIN37.DSP_0_PCOUT37 always
DSP_R.DSP_1_PCIN38.DSP_0_PCOUT38 always
DSP_R.DSP_1_PCIN39.DSP_0_PCOUT39 always
DSP_R.DSP_1_PCIN40.DSP_0_PCOUT40 always
DSP_R.DSP_1_PCIN41.DSP_0_PCOUT41 always
DSP_R.DSP_1_PCIN42.DSP_0_PCOUT42 always
DSP_R.DSP_1_PCIN43.DSP_0_PCOUT43 always
DSP_R.DSP_1_PCIN44.DSP_0_PCOUT44 always
DSP_R.DSP_1_PCIN45.DSP_0_PCOUT45 always
DSP_R.DSP_1_PCIN46.DSP_0_PCOUT46 always
DSP_R.DSP_1_PCIN47.DSP_0_PCOUT47 always
DSP_R.DSP_CARRYCASCOUT.DSP_1_CARRYCASCOUT always
DSP_R.DSP_LOGIC_OUTS_B0_0.DSP_1_P23 always
DSP_R.DSP_LOGIC_OUTS_B0_1.DSP_1_P27 always
DSP_R.DSP_LOGIC_OUTS_B0_2.DSP_1_P31 always
DSP_R.DSP_LOGIC_OUTS_B0_3.DSP_1_P35 always
DSP_R.DSP_LOGIC_OUTS_B0_4.DSP_1_P37 always
DSP_R.DSP_LOGIC_OUTS_B1_0.DSP_1_P1 always
DSP_R.DSP_LOGIC_OUTS_B1_1.DSP_1_P5 always
DSP_R.DSP_LOGIC_OUTS_B1_2.DSP_1_P9 always
DSP_R.DSP_LOGIC_OUTS_B1_3.DSP_1_P13 always
DSP_R.DSP_LOGIC_OUTS_B1_4.DSP_1_P17 always
DSP_R.DSP_LOGIC_OUTS_B2_0.DSP_1_P22 always
DSP_R.DSP_LOGIC_OUTS_B2_1.DSP_1_P26 always
DSP_R.DSP_LOGIC_OUTS_B2_2.DSP_1_P30 always
DSP_R.DSP_LOGIC_OUTS_B2_3.DSP_1_P34 always
DSP_R.DSP_LOGIC_OUTS_B2_4.DSP_1_P38 always
DSP_R.DSP_LOGIC_OUTS_B3_0.DSP_1_P0 always
DSP_R.DSP_LOGIC_OUTS_B3_1.DSP_1_P4 always
DSP_R.DSP_LOGIC_OUTS_B3_2.DSP_1_P8 always
DSP_R.DSP_LOGIC_OUTS_B3_3.DSP_1_P12 always
DSP_R.DSP_LOGIC_OUTS_B3_4.DSP_1_P16 always
DSP_R.DSP_LOGIC_OUTS_B4_0.DSP_1_P3 always
DSP_R.DSP_LOGIC_OUTS_B4_1.DSP_1_P7 always
DSP_R.DSP_LOGIC_OUTS_B4_2.DSP_1_P11 always
DSP_R.DSP_LOGIC_OUTS_B4_3.DSP_1_P15 always
DSP_R.DSP_LOGIC_OUTS_B4_4.DSP_1_P19 always
DSP_R.DSP_LOGIC_OUTS_B5_0.DSP_1_P21 always
DSP_R.DSP_LOGIC_OUTS_B5_1.DSP_1_P25 always
DSP_R.DSP_LOGIC_OUTS_B5_2.DSP_1_P29 always
DSP_R.DSP_LOGIC_OUTS_B5_3.DSP_1_P33 always
DSP_R.DSP_LOGIC_OUTS_B5_4.DSP_1_P39 always
DSP_R.DSP_LOGIC_OUTS_B6_0.DSP_1_P2 always
DSP_R.DSP_LOGIC_OUTS_B6_1.DSP_1_P6 always
DSP_R.DSP_LOGIC_OUTS_B6_2.DSP_1_P10 always
DSP_R.DSP_LOGIC_OUTS_B6_3.DSP_1_P14 always
DSP_R.DSP_LOGIC_OUTS_B6_4.DSP_1_P18 always
DSP_R.DSP_LOGIC_OUTS_B7_0.DSP_1_P20 always
DSP_R.DSP_LOGIC_OUTS_B7_1.DSP_1_P24 always
DSP_R.DSP_LOGIC_OUTS_B7_2.DSP_1_P28 always
DSP_R.DSP_LOGIC_OUTS_B7_3.DSP_1_P32 always
DSP_R.DSP_LOGIC_OUTS_B7_4.DSP_1_P36 always
DSP_R.DSP_LOGIC_OUTS_B8_0.DSP_0_P43 always
DSP_R.DSP_LOGIC_OUTS_B8_2.DSP_1_OVERFLOW always
DSP_R.DSP_LOGIC_OUTS_B8_3.DSP_1_CARRYOUT0 always
DSP_R.DSP_LOGIC_OUTS_B8_4.DSP_0_P47 always
DSP_R.DSP_LOGIC_OUTS_B9_0.DSP_0_P42 always
DSP_R.DSP_LOGIC_OUTS_B9_2.DSP_0_UNDERFLOW always
DSP_R.DSP_LOGIC_OUTS_B9_4.DSP_0_P44 always
DSP_R.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_R.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_R.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_R.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_R.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_R.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_R.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_R.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_R.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_R.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_R.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_R.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_R.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_R.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_R.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_R.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_R.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_R.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_R.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_R.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_R.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_R.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_R.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_R.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_R.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_R.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_R.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_R.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_R.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_R.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_R.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_R.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_R.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_R.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_R.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_R.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_R.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_R.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_R.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_R.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_R.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_R.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_R.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_R.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_R.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_R.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_R.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_R.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_R.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_R.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_R.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_R.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_R.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_R.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_R.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_R.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_R.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_R.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_R.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_R.DSP_MULTSIGNOUT.DSP_1_MULTSIGNOUT always
DSP_R.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_R.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_R.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_R.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_R.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_R.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_R.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_R.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_R.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_R.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_R.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_R.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_R.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_R.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_R.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_R.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_R.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_R.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_R.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_R.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_R.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_R.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_R.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_R.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_R.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_R.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_R.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_R.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_R.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_R.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_R.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_R.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_R.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_R.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_R.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_R.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_R.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_R.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_R.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_R.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_R.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_R.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_R.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_R.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_R.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_R.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_R.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_R.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_R.DSP_PCOUT0.DSP_1_PCOUT0 always
DSP_R.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_R.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_R.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_R.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_R.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_R.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_R.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_R.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_R.DSP_PCOUT9.DSP_1_PCOUT9 always
DSP_R.DSP_PCOUT10.DSP_1_PCOUT10 always
DSP_R.DSP_PCOUT11.DSP_1_PCOUT11 always
DSP_R.DSP_PCOUT12.DSP_1_PCOUT12 always
DSP_R.DSP_PCOUT13.DSP_1_PCOUT13 always
DSP_R.DSP_PCOUT14.DSP_1_PCOUT14 always
DSP_R.DSP_PCOUT15.DSP_1_PCOUT15 always
DSP_R.DSP_PCOUT16.DSP_1_PCOUT16 always
DSP_R.DSP_PCOUT17.DSP_1_PCOUT17 always
DSP_R.DSP_PCOUT18.DSP_1_PCOUT18 always
DSP_R.DSP_PCOUT19.DSP_1_PCOUT19 always
DSP_R.DSP_PCOUT20.DSP_1_PCOUT20 always
DSP_R.DSP_PCOUT21.DSP_1_PCOUT21 always
DSP_R.DSP_PCOUT22.DSP_1_PCOUT22 always
DSP_R.DSP_PCOUT23.DSP_1_PCOUT23 always
DSP_R.DSP_PCOUT24.DSP_1_PCOUT24 always
DSP_R.DSP_PCOUT25.DSP_1_PCOUT25 always
DSP_R.DSP_PCOUT26.DSP_1_PCOUT26 always
DSP_R.DSP_PCOUT27.DSP_1_PCOUT27 always
DSP_R.DSP_PCOUT28.DSP_1_PCOUT28 always
DSP_R.DSP_PCOUT29.DSP_1_PCOUT29 always
DSP_R.DSP_PCOUT30.DSP_1_PCOUT30 always
DSP_R.DSP_PCOUT31.DSP_1_PCOUT31 always
DSP_R.DSP_PCOUT32.DSP_1_PCOUT32 always
DSP_R.DSP_PCOUT33.DSP_1_PCOUT33 always
DSP_R.DSP_PCOUT34.DSP_1_PCOUT34 always
DSP_R.DSP_PCOUT35.DSP_1_PCOUT35 always
DSP_R.DSP_PCOUT36.DSP_1_PCOUT36 always
DSP_R.DSP_PCOUT37.DSP_1_PCOUT37 always
DSP_R.DSP_PCOUT38.DSP_1_PCOUT38 always
DSP_R.DSP_PCOUT39.DSP_1_PCOUT39 always
DSP_R.DSP_PCOUT40.DSP_1_PCOUT40 always
DSP_R.DSP_PCOUT41.DSP_1_PCOUT41 always
DSP_R.DSP_PCOUT42.DSP_1_PCOUT42 always
DSP_R.DSP_PCOUT43.DSP_1_PCOUT43 always
DSP_R.DSP_PCOUT44.DSP_1_PCOUT44 always
DSP_R.DSP_PCOUT45.DSP_1_PCOUT45 always
DSP_R.DSP_PCOUT46.DSP_1_PCOUT46 always
DSP_R.DSP_PCOUT47.DSP_1_PCOUT47 always

0
spartan7/ppips_dsp_r.origin_info.db Normal file
View File

526
spartan7/ppips_gtp_channel_0.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_0.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_0_mid_left.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_0_mid_right.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_1.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_1.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_1_mid_left.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_1_mid_right.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_2.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_2.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_2_mid_left.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_2_mid_right.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_3.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_3.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_3_mid_left.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

526
spartan7/ppips_gtp_channel_3_mid_right.db Normal file
View File

@ -0,0 +1,526 @@
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

161
spartan7/ppips_gtp_common.db Normal file
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@ -0,0 +1,161 @@
GTP_COMMON.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always
GTP_COMMON.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always
GTP_COMMON.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always
GTP_COMMON.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always
GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always
GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always
GTP_COMMON.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always
GTP_COMMON.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always
GTP_COMMON.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always
GTP_COMMON.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always
GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always
GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always
GTP_COMMON.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always
GTP_COMMON.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always
GTP_COMMON.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always
GTP_COMMON.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always
GTP_COMMON.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always
GTP_COMMON.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always
GTP_COMMON.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK0.GTPE2_COMMON_RXOUTCLK_0 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK1.GTPE2_COMMON_RXOUTCLK_1 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK2.GTPE2_COMMON_TXOUTCLK_0 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK3.GTPE2_COMMON_TXOUTCLK_1 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK4.IBUFDS_GTPE2_0_MGTCLKOUT always
GTP_COMMON.GTPE2_COMMON_MGT_CLK5.IBUFDS_GTPE2_1_MGTCLKOUT always
GTP_COMMON.GTPE2_COMMON_MGT_CLK6.GTPE2_COMMON_RXOUTCLK_2 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK7.GTPE2_COMMON_RXOUTCLK_3 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK8.GTPE2_COMMON_TXOUTCLK_2 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK9.GTPE2_COMMON_TXOUTCLK_3 always
GTP_COMMON.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always
GTP_COMMON.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always
GTP_COMMON.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always
GTP_COMMON.GTPE2_COMMON_PLL0RESET.GTPE2_CTRL0_3 always
GTP_COMMON.GTPE2_COMMON_PLL1LOCKDETCLK.GTPE2_CLK1_1 always
GTP_COMMON.GTPE2_COMMON_PLL1LOCKEN.GTPE2_IMUX42_2 always
GTP_COMMON.GTPE2_COMMON_PLL1PD.GTPE2_IMUX42_1 always
GTP_COMMON.GTPE2_COMMON_PLL1RESET.GTPE2_CTRL1_3 always
GTP_COMMON.GTPE2_COMMON_RCALENB.GTPE2_IMUX3_5 always
GTP_COMMON.GTPE2_COMMON_BGRCALOVRD0.GTPE2_IMUX45_5 always
GTP_COMMON.GTPE2_COMMON_BGRCALOVRD1.GTPE2_IMUX45_4 always
GTP_COMMON.GTPE2_COMMON_BGRCALOVRD2.GTPE2_IMUX45_3 always
GTP_COMMON.GTPE2_COMMON_BGRCALOVRD3.GTPE2_IMUX45_2 always
GTP_COMMON.GTPE2_COMMON_BGRCALOVRD4.GTPE2_IMUX45_1 always
GTP_COMMON.GTPE2_COMMON_DRPADDR0.GTPE2_IMUX35_5 always
GTP_COMMON.GTPE2_COMMON_DRPADDR1.GTPE2_IMUX27_5 always
GTP_COMMON.GTPE2_COMMON_DRPADDR2.GTPE2_IMUX35_4 always
GTP_COMMON.GTPE2_COMMON_DRPADDR3.GTPE2_IMUX27_4 always
GTP_COMMON.GTPE2_COMMON_DRPADDR4.GTPE2_IMUX35_3 always
GTP_COMMON.GTPE2_COMMON_DRPADDR5.GTPE2_IMUX27_3 always
GTP_COMMON.GTPE2_COMMON_DRPADDR6.GTPE2_IMUX35_2 always
GTP_COMMON.GTPE2_COMMON_DRPADDR7.GTPE2_IMUX27_2 always
GTP_COMMON.GTPE2_COMMON_DRPDI0.GTPE2_IMUX38_5 always
GTP_COMMON.GTPE2_COMMON_DRPDI1.GTPE2_IMUX30_5 always
GTP_COMMON.GTPE2_COMMON_DRPDI2.GTPE2_IMUX38_4 always
GTP_COMMON.GTPE2_COMMON_DRPDI3.GTPE2_IMUX30_4 always
GTP_COMMON.GTPE2_COMMON_DRPDI4.GTPE2_IMUX38_3 always
GTP_COMMON.GTPE2_COMMON_DRPDI5.GTPE2_IMUX30_3 always
GTP_COMMON.GTPE2_COMMON_DRPDI6.GTPE2_IMUX38_2 always
GTP_COMMON.GTPE2_COMMON_DRPDI7.GTPE2_IMUX30_2 always
GTP_COMMON.GTPE2_COMMON_DRPDI8.GTPE2_IMUX38_1 always
GTP_COMMON.GTPE2_COMMON_DRPDI9.GTPE2_IMUX30_1 always
GTP_COMMON.GTPE2_COMMON_DRPDI10.GTPE2_IMUX22_2 always
GTP_COMMON.GTPE2_COMMON_DRPDI11.GTPE2_IMUX14_2 always
GTP_COMMON.GTPE2_COMMON_DRPDI12.GTPE2_IMUX22_5 always
GTP_COMMON.GTPE2_COMMON_DRPDI13.GTPE2_IMUX14_5 always
GTP_COMMON.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always
GTP_COMMON.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always
GTP_COMMON.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always
GTP_COMMON.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always
GTP_COMMON.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always
GTP_COMMON.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always
GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always
GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always
GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always
GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always
GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always
GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always
GTP_COMMON.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always
GTP_COMMON.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always
GTP_COMMON.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always
GTP_COMMON.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always
GTP_COMMON.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD13.GTPE2_IMUX24_4 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD14.GTPE2_IMUX32_3 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD15.GTPE2_IMUX24_3 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD16.GTPE2_IMUX32_2 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD17.GTPE2_IMUX24_2 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD18.GTPE2_IMUX32_1 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD19.GTPE2_IMUX24_1 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD20.GTPE2_IMUX5_5 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD21.GTPE2_IMUX5_4 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD22.GTPE2_IMUX5_3 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD23.GTPE2_IMUX5_2 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD24.GTPE2_IMUX5_1 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD110.GTPE2_IMUX40_5 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD111.GTPE2_IMUX40_4 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD112.GTPE2_IMUX0_5 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD113.GTPE2_IMUX0_4 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD114.GTPE2_IMUX0_3 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD115.GTPE2_IMUX0_2 always
GTP_COMMON.GTPE2_COMMON_PMARSVD0.GTPE2_IMUX20_5 always
GTP_COMMON.GTPE2_COMMON_PMARSVD1.GTPE2_IMUX20_4 always
GTP_COMMON.GTPE2_COMMON_PMARSVD2.GTPE2_IMUX20_3 always
GTP_COMMON.GTPE2_COMMON_PMARSVD3.GTPE2_IMUX20_2 always
GTP_COMMON.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always
GTP_COMMON.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always
GTP_COMMON.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always
GTP_COMMON.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always
GTP_COMMON.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always
GTP_COMMON.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always

151
spartan7/ppips_gtp_common_mid_left.db Normal file
View File

@ -0,0 +1,151 @@
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0RESET.GTPE2_CTRL0_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1LOCKDETCLK.GTPE2_CLK1_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1LOCKEN.GTPE2_IMUX42_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1PD.GTPE2_IMUX42_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1RESET.GTPE2_CTRL1_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_RCALENB.GTPE2_IMUX3_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD0.GTPE2_IMUX45_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD1.GTPE2_IMUX45_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD2.GTPE2_IMUX45_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD3.GTPE2_IMUX45_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD4.GTPE2_IMUX45_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR0.GTPE2_IMUX35_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR1.GTPE2_IMUX27_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR2.GTPE2_IMUX35_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR3.GTPE2_IMUX27_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR4.GTPE2_IMUX35_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR5.GTPE2_IMUX27_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR6.GTPE2_IMUX35_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR7.GTPE2_IMUX27_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI0.GTPE2_IMUX38_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI1.GTPE2_IMUX30_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI2.GTPE2_IMUX38_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI3.GTPE2_IMUX30_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI4.GTPE2_IMUX38_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI5.GTPE2_IMUX30_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI6.GTPE2_IMUX38_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI7.GTPE2_IMUX30_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI8.GTPE2_IMUX38_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI9.GTPE2_IMUX30_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI10.GTPE2_IMUX22_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI11.GTPE2_IMUX14_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI12.GTPE2_IMUX22_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI13.GTPE2_IMUX14_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD13.GTPE2_IMUX24_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD14.GTPE2_IMUX32_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD15.GTPE2_IMUX24_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD16.GTPE2_IMUX32_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD17.GTPE2_IMUX24_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD18.GTPE2_IMUX32_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD19.GTPE2_IMUX24_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD20.GTPE2_IMUX5_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD21.GTPE2_IMUX5_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD22.GTPE2_IMUX5_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD23.GTPE2_IMUX5_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD24.GTPE2_IMUX5_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD110.GTPE2_IMUX40_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD111.GTPE2_IMUX40_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD112.GTPE2_IMUX0_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD113.GTPE2_IMUX0_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD114.GTPE2_IMUX0_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD115.GTPE2_IMUX0_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD0.GTPE2_IMUX20_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD1.GTPE2_IMUX20_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD2.GTPE2_IMUX20_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD3.GTPE2_IMUX20_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always

151
spartan7/ppips_gtp_common_mid_right.db Normal file
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@ -0,0 +1,151 @@
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0RESET.GTPE2_CTRL0_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1LOCKDETCLK.GTPE2_CLK1_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1LOCKEN.GTPE2_IMUX42_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1PD.GTPE2_IMUX42_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1RESET.GTPE2_CTRL1_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RCALENB.GTPE2_IMUX3_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD0.GTPE2_IMUX45_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD1.GTPE2_IMUX45_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD2.GTPE2_IMUX45_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD3.GTPE2_IMUX45_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD4.GTPE2_IMUX45_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR0.GTPE2_IMUX35_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR1.GTPE2_IMUX27_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR2.GTPE2_IMUX35_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR3.GTPE2_IMUX27_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR4.GTPE2_IMUX35_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR5.GTPE2_IMUX27_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR6.GTPE2_IMUX35_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR7.GTPE2_IMUX27_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI0.GTPE2_IMUX38_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI1.GTPE2_IMUX30_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI2.GTPE2_IMUX38_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI3.GTPE2_IMUX30_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI4.GTPE2_IMUX38_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI5.GTPE2_IMUX30_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI6.GTPE2_IMUX38_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI7.GTPE2_IMUX30_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI8.GTPE2_IMUX38_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI9.GTPE2_IMUX30_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI10.GTPE2_IMUX22_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI11.GTPE2_IMUX14_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI12.GTPE2_IMUX22_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI13.GTPE2_IMUX14_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD13.GTPE2_IMUX24_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD14.GTPE2_IMUX32_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD15.GTPE2_IMUX24_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD16.GTPE2_IMUX32_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD17.GTPE2_IMUX24_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD18.GTPE2_IMUX32_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD19.GTPE2_IMUX24_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD20.GTPE2_IMUX5_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD21.GTPE2_IMUX5_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD22.GTPE2_IMUX5_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD23.GTPE2_IMUX5_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD24.GTPE2_IMUX5_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD110.GTPE2_IMUX40_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD111.GTPE2_IMUX40_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD112.GTPE2_IMUX0_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD113.GTPE2_IMUX0_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD114.GTPE2_IMUX0_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD115.GTPE2_IMUX0_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD0.GTPE2_IMUX20_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD1.GTPE2_IMUX20_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD2.GTPE2_IMUX20_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD3.GTPE2_IMUX20_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always

120
spartan7/ppips_gtp_int_interface.db Normal file
View File

@ -0,0 +1,120 @@
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY0.GTPE2_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY1.GTPE2_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY2.GTPE2_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY3.GTPE2_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY4.GTPE2_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY5.GTPE2_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY6.GTPE2_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY7.GTPE2_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY8.GTPE2_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY9.GTPE2_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY10.GTPE2_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY11.GTPE2_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY12.GTPE2_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY13.GTPE2_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY14.GTPE2_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY15.GTPE2_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY16.GTPE2_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY17.GTPE2_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY18.GTPE2_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY19.GTPE2_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY20.GTPE2_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY21.GTPE2_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY22.GTPE2_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY23.GTPE2_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY24.GTPE2_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY25.GTPE2_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY26.GTPE2_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY27.GTPE2_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY28.GTPE2_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY29.GTPE2_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY30.GTPE2_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY31.GTPE2_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY32.GTPE2_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY33.GTPE2_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY34.GTPE2_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY35.GTPE2_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY36.GTPE2_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY37.GTPE2_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY38.GTPE2_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY39.GTPE2_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY40.GTPE2_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY41.GTPE2_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY42.GTPE2_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY43.GTPE2_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY44.GTPE2_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY45.GTPE2_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY46.GTPE2_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY47.GTPE2_INT_INTERFACE_IMUX47 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT0.GTPE2_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT1.GTPE2_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT2.GTPE2_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT3.GTPE2_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT4.GTPE2_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT5.GTPE2_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT6.GTPE2_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT7.GTPE2_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT8.GTPE2_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT9.GTPE2_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT10.GTPE2_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT11.GTPE2_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT12.GTPE2_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT13.GTPE2_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT14.GTPE2_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT15.GTPE2_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT16.GTPE2_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT17.GTPE2_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT18.GTPE2_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT19.GTPE2_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT20.GTPE2_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT21.GTPE2_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT22.GTPE2_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT23.GTPE2_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT24.GTPE2_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT25.GTPE2_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT26.GTPE2_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT27.GTPE2_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT28.GTPE2_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT29.GTPE2_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT30.GTPE2_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT31.GTPE2_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT32.GTPE2_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT33.GTPE2_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT34.GTPE2_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT35.GTPE2_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT36.GTPE2_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT37.GTPE2_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT38.GTPE2_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT39.GTPE2_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT40.GTPE2_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT41.GTPE2_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT42.GTPE2_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT43.GTPE2_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT44.GTPE2_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT45.GTPE2_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT46.GTPE2_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT47.GTPE2_INT_INTERFACE_IMUX47 always

120
spartan7/ppips_gtp_int_interface_l.db Normal file
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@ -0,0 +1,120 @@
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS0.GTPE2_INT_INTERFACE_LOGIC_OUTS_B0 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS1.GTPE2_INT_INTERFACE_LOGIC_OUTS_B1 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS2.GTPE2_INT_INTERFACE_LOGIC_OUTS_B2 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS3.GTPE2_INT_INTERFACE_LOGIC_OUTS_B3 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS4.GTPE2_INT_INTERFACE_LOGIC_OUTS_B4 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS5.GTPE2_INT_INTERFACE_LOGIC_OUTS_B5 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS6.GTPE2_INT_INTERFACE_LOGIC_OUTS_B6 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS7.GTPE2_INT_INTERFACE_LOGIC_OUTS_B7 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS8.GTPE2_INT_INTERFACE_LOGIC_OUTS_B8 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS9.GTPE2_INT_INTERFACE_LOGIC_OUTS_B9 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS10.GTPE2_INT_INTERFACE_LOGIC_OUTS_B10 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS11.GTPE2_INT_INTERFACE_LOGIC_OUTS_B11 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS12.GTPE2_INT_INTERFACE_LOGIC_OUTS_B12 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS13.GTPE2_INT_INTERFACE_LOGIC_OUTS_B13 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS14.GTPE2_INT_INTERFACE_LOGIC_OUTS_B14 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS15.GTPE2_INT_INTERFACE_LOGIC_OUTS_B15 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS16.GTPE2_INT_INTERFACE_LOGIC_OUTS_B16 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS17.GTPE2_INT_INTERFACE_LOGIC_OUTS_B17 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS18.GTPE2_INT_INTERFACE_LOGIC_OUTS_B18 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS19.GTPE2_INT_INTERFACE_LOGIC_OUTS_B19 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS20.GTPE2_INT_INTERFACE_LOGIC_OUTS_B20 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS21.GTPE2_INT_INTERFACE_LOGIC_OUTS_B21 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS22.GTPE2_INT_INTERFACE_LOGIC_OUTS_B22 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS23.GTPE2_INT_INTERFACE_LOGIC_OUTS_B23 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY0.GTPE2_LEFT_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY1.GTPE2_LEFT_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY2.GTPE2_LEFT_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY3.GTPE2_LEFT_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY4.GTPE2_LEFT_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY5.GTPE2_LEFT_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY6.GTPE2_LEFT_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY7.GTPE2_LEFT_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY8.GTPE2_LEFT_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY9.GTPE2_LEFT_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY10.GTPE2_LEFT_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY11.GTPE2_LEFT_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY12.GTPE2_LEFT_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY13.GTPE2_LEFT_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY14.GTPE2_LEFT_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY15.GTPE2_LEFT_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY16.GTPE2_LEFT_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY17.GTPE2_LEFT_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY18.GTPE2_LEFT_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY19.GTPE2_LEFT_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY20.GTPE2_LEFT_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY21.GTPE2_LEFT_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY22.GTPE2_LEFT_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY23.GTPE2_LEFT_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY24.GTPE2_LEFT_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY25.GTPE2_LEFT_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY26.GTPE2_LEFT_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY27.GTPE2_LEFT_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY28.GTPE2_LEFT_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY29.GTPE2_LEFT_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY30.GTPE2_LEFT_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY31.GTPE2_LEFT_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY32.GTPE2_LEFT_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY33.GTPE2_LEFT_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY34.GTPE2_LEFT_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY35.GTPE2_LEFT_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY36.GTPE2_LEFT_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY37.GTPE2_LEFT_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY38.GTPE2_LEFT_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY39.GTPE2_LEFT_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY40.GTPE2_LEFT_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY41.GTPE2_LEFT_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY42.GTPE2_LEFT_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY43.GTPE2_LEFT_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY44.GTPE2_LEFT_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY45.GTPE2_LEFT_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY46.GTPE2_LEFT_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY47.GTPE2_LEFT_INT_INTERFACE_IMUX47 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT0.GTPE2_LEFT_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT1.GTPE2_LEFT_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT2.GTPE2_LEFT_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT3.GTPE2_LEFT_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT4.GTPE2_LEFT_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT5.GTPE2_LEFT_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT6.GTPE2_LEFT_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT7.GTPE2_LEFT_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT8.GTPE2_LEFT_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT9.GTPE2_LEFT_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT10.GTPE2_LEFT_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT11.GTPE2_LEFT_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT12.GTPE2_LEFT_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT13.GTPE2_LEFT_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT14.GTPE2_LEFT_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT15.GTPE2_LEFT_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT16.GTPE2_LEFT_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT17.GTPE2_LEFT_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT18.GTPE2_LEFT_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT19.GTPE2_LEFT_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT20.GTPE2_LEFT_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT21.GTPE2_LEFT_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT22.GTPE2_LEFT_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT23.GTPE2_LEFT_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT24.GTPE2_LEFT_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT25.GTPE2_LEFT_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT26.GTPE2_LEFT_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT27.GTPE2_LEFT_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT28.GTPE2_LEFT_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT29.GTPE2_LEFT_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT30.GTPE2_LEFT_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT31.GTPE2_LEFT_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT32.GTPE2_LEFT_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT33.GTPE2_LEFT_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT34.GTPE2_LEFT_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT35.GTPE2_LEFT_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT36.GTPE2_LEFT_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT37.GTPE2_LEFT_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT38.GTPE2_LEFT_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT39.GTPE2_LEFT_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT40.GTPE2_LEFT_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT41.GTPE2_LEFT_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT42.GTPE2_LEFT_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT43.GTPE2_LEFT_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT44.GTPE2_LEFT_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT45.GTPE2_LEFT_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT46.GTPE2_LEFT_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT47.GTPE2_LEFT_INT_INTERFACE_IMUX47 always

120
spartan7/ppips_gtp_int_interface_r.db Normal file
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@ -0,0 +1,120 @@
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS0.GTPE2_INT_INTERFACE_LOGIC_OUTS_B0 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS1.GTPE2_INT_INTERFACE_LOGIC_OUTS_B1 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS2.GTPE2_INT_INTERFACE_LOGIC_OUTS_B2 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS3.GTPE2_INT_INTERFACE_LOGIC_OUTS_B3 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS4.GTPE2_INT_INTERFACE_LOGIC_OUTS_B4 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS5.GTPE2_INT_INTERFACE_LOGIC_OUTS_B5 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS6.GTPE2_INT_INTERFACE_LOGIC_OUTS_B6 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS7.GTPE2_INT_INTERFACE_LOGIC_OUTS_B7 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS8.GTPE2_INT_INTERFACE_LOGIC_OUTS_B8 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS9.GTPE2_INT_INTERFACE_LOGIC_OUTS_B9 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS10.GTPE2_INT_INTERFACE_LOGIC_OUTS_B10 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS11.GTPE2_INT_INTERFACE_LOGIC_OUTS_B11 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS12.GTPE2_INT_INTERFACE_LOGIC_OUTS_B12 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS13.GTPE2_INT_INTERFACE_LOGIC_OUTS_B13 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS14.GTPE2_INT_INTERFACE_LOGIC_OUTS_B14 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS15.GTPE2_INT_INTERFACE_LOGIC_OUTS_B15 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS16.GTPE2_INT_INTERFACE_LOGIC_OUTS_B16 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS17.GTPE2_INT_INTERFACE_LOGIC_OUTS_B17 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS18.GTPE2_INT_INTERFACE_LOGIC_OUTS_B18 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS19.GTPE2_INT_INTERFACE_LOGIC_OUTS_B19 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS20.GTPE2_INT_INTERFACE_LOGIC_OUTS_B20 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS21.GTPE2_INT_INTERFACE_LOGIC_OUTS_B21 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS22.GTPE2_INT_INTERFACE_LOGIC_OUTS_B22 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS23.GTPE2_INT_INTERFACE_LOGIC_OUTS_B23 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY0.GTPE2_R_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY1.GTPE2_R_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY2.GTPE2_R_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY3.GTPE2_R_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY4.GTPE2_R_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY5.GTPE2_R_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY6.GTPE2_R_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY7.GTPE2_R_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY8.GTPE2_R_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY9.GTPE2_R_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY10.GTPE2_R_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY11.GTPE2_R_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY12.GTPE2_R_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY13.GTPE2_R_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY14.GTPE2_R_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY15.GTPE2_R_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY16.GTPE2_R_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY17.GTPE2_R_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY18.GTPE2_R_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY19.GTPE2_R_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY20.GTPE2_R_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY21.GTPE2_R_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY22.GTPE2_R_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY23.GTPE2_R_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY24.GTPE2_R_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY25.GTPE2_R_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY26.GTPE2_R_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY27.GTPE2_R_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY28.GTPE2_R_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY29.GTPE2_R_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY30.GTPE2_R_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY31.GTPE2_R_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY32.GTPE2_R_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY33.GTPE2_R_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY34.GTPE2_R_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY35.GTPE2_R_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY36.GTPE2_R_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY37.GTPE2_R_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY38.GTPE2_R_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY39.GTPE2_R_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY40.GTPE2_R_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY41.GTPE2_R_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY42.GTPE2_R_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY43.GTPE2_R_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY44.GTPE2_R_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY45.GTPE2_R_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY46.GTPE2_R_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY47.GTPE2_R_INT_INTERFACE_IMUX47 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT0.GTPE2_R_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT1.GTPE2_R_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT2.GTPE2_R_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT3.GTPE2_R_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT4.GTPE2_R_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT5.GTPE2_R_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT6.GTPE2_R_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT7.GTPE2_R_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT8.GTPE2_R_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT9.GTPE2_R_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT10.GTPE2_R_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT11.GTPE2_R_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT12.GTPE2_R_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT13.GTPE2_R_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT14.GTPE2_R_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT15.GTPE2_R_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT16.GTPE2_R_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT17.GTPE2_R_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT18.GTPE2_R_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT19.GTPE2_R_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT20.GTPE2_R_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT21.GTPE2_R_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT22.GTPE2_R_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT23.GTPE2_R_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT24.GTPE2_R_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT25.GTPE2_R_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT26.GTPE2_R_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT27.GTPE2_R_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT28.GTPE2_R_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT29.GTPE2_R_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT30.GTPE2_R_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT31.GTPE2_R_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT32.GTPE2_R_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT33.GTPE2_R_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT34.GTPE2_R_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT35.GTPE2_R_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT36.GTPE2_R_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT37.GTPE2_R_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT38.GTPE2_R_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT39.GTPE2_R_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT40.GTPE2_R_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT41.GTPE2_R_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT42.GTPE2_R_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT43.GTPE2_R_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT44.GTPE2_R_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT45.GTPE2_R_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT46.GTPE2_R_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT47.GTPE2_R_INT_INTERFACE_IMUX47 always

4
spartan7/ppips_hclk_cmt.db Normal file
View File

@ -0,0 +1,4 @@
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF0.HCLK_CMT_BUFMRCE_O0 always
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF1.HCLK_CMT_BUFMRCE_O1 always
HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP0.HCLK_CMT_BUFMR_CE0 always
HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP1.HCLK_CMT_BUFMR_CE1 always

36
spartan7/ppips_hclk_ioi3.db Normal file
View File

@ -0,0 +1,36 @@
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0.HCLK_IOI_RCLK2RCLK0 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1.HCLK_IOI_RCLK2RCLK1 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2.HCLK_IOI_RCLK2RCLK2 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3.HCLK_IOI_RCLK2RCLK3 always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK_OUT0.HCLK_IOI_RCLK_BEFORE_DIV0 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT1.HCLK_IOI_RCLK_BEFORE_DIV1 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT2.HCLK_IOI_RCLK_BEFORE_DIV2 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT3.HCLK_IOI_RCLK_BEFORE_DIV3 always
HCLK_IOI3.HCLK_IOI_BUFR0_CE.HCLK_RCLK_DIV_CE0 always
HCLK_IOI3.HCLK_IOI_BUFR0_CLR.HCLK_RCLK_DIV_CLR0 always
HCLK_IOI3.HCLK_IOI_BUFR1_CE.HCLK_RCLK_DIV_CE1 always
HCLK_IOI3.HCLK_IOI_BUFR1_CLR.HCLK_RCLK_DIV_CLR1 always
HCLK_IOI3.HCLK_IOI_BUFR2_CE.HCLK_RCLK_DIV_CE2 always
HCLK_IOI3.HCLK_IOI_BUFR2_CLR.HCLK_RCLK_DIV_CLR2 always
HCLK_IOI3.HCLK_IOI_BUFR3_CE.HCLK_RCLK_DIV_CE3 always
HCLK_IOI3.HCLK_IOI_BUFR3_CLR.HCLK_RCLK_DIV_CLR3 always
HCLK_IOI3.HCLK_IOI_IOCLK0.HCLK_IOI_BUFIO_O0 always
HCLK_IOI3.HCLK_IOI_IOCLK1.HCLK_IOI_BUFIO_O1 always
HCLK_IOI3.HCLK_IOI_IOCLK2.HCLK_IOI_BUFIO_O2 always
HCLK_IOI3.HCLK_IOI_IOCLK3.HCLK_IOI_BUFIO_O3 always
HCLK_IOI3.HCLK_IOI_RCLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 always
HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 always
HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 always
HCLK_IOI3.HCLK_IOI_RCLK2IO3.HCLK_IOI_CK_BUFRCLK3 always
HCLK_IOI3.HCLK_IOI_RCLK2RCLK0.HCLK_IOI_RCLK_OUT0 always
HCLK_IOI3.HCLK_IOI_RCLK2RCLK1.HCLK_IOI_RCLK_OUT1 always
HCLK_IOI3.HCLK_IOI_RCLK2RCLK2.HCLK_IOI_RCLK_OUT2 always
HCLK_IOI3.HCLK_IOI_RCLK2RCLK3.HCLK_IOI_RCLK_OUT3 always

8
spartan7/ppips_hclk_l.db Normal file
View File

@ -0,0 +1,8 @@
HCLK_L.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always
HCLK_L.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always
HCLK_L.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always
HCLK_L.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always
HCLK_L.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always
HCLK_L.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always
HCLK_L.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always
HCLK_L.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always

0
spartan7/ppips_hclk_l.origin_info.db Normal file
View File

8
spartan7/ppips_hclk_r.db Normal file
View File

@ -0,0 +1,8 @@
HCLK_R.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always
HCLK_R.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always
HCLK_R.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always
HCLK_R.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always
HCLK_R.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always
HCLK_R.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always
HCLK_R.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always
HCLK_R.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always

0
spartan7/ppips_hclk_r.origin_info.db Normal file
View File

Some files were not shown because too many files have changed in this diff Show More