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add changes from db-workspace-for-kintex

This commit is contained in:
Hans Baier 2023-03-30 02:36:49 +07:00
parent 0a0addedd7
commit d9e8b8246e
341 changed files with 6930959 additions and 627213 deletions
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43
kintex7/README.md Normal file
View File

@ -0,0 +1,43 @@
# workspace for prjxray DB for kintex7
A workspace for @hansfbaier's prjxray DB / kintex7.
## ChangeLog
[Dez 01]
* Use latest database from the CI run of the prjxray upstream merge,
except changes from this issue:
https://github.com/f4pga/prjxray/issues/2061
* add XC7K160T files from upstream prjxray db
[Mar 28]
* Add xc7k325tffg676-1 from the old database.
* Remove a (suspicious) conflicting bit
```
prjxray.fasm_assembler.FasmInconsistentBits: FASM line "INT_R_X95Y132.IMUX34.SL1END1" wanted to set bit (4206489, 65, 21) but was cleared by FASM line "RIOB18_X95Y131.IOB_Y0.SSTL135.DRIVE.I_FIXED"
```
-> Drop !25_85 from RIOB18.IOB_Y0.SSTL135.DRIVE.I_FIXED.
* Add the missing lines to segbits_rioi.db/segbits_rioi_tbyteterm.db from @hansfbaier's 20220326 DB.
* Add a fake ppips_rioi_tbyteterm.db which is created from ppips_rioi3_tbyteterm.db.
* Fill the empty "bits" of LIOI3_X0Y9 with the content of "bits" of LIOB33_X0Y9.
[Mar 29]
* Remove an another (suspicious) conflicting bit
```
prjxray.fasm_assembler.FasmInconsistentBits: FASM line "INT_R_X95Y101.IMUX34.SE2END1" wanted to clear bit (4206488, 2, 21) but was set by FASM line "RIOB18_X95Y101.IOB_Y1.SSTL135.DRIVE.I_FIXED"
```
-> Drop 24_21 from RIOB18.IOB_Y1.SSTL135.DRIVE.I_FIXED.
* Add "RIOI_O0.RIOI_OLOGIC[01]_OQ always" to ppips_rioi.db/ppips_rioi_tbytesrc.db. Looks lioi3 counterparts have them.

14
kintex7/element_counts.csv
View File

@ -1,9 +1,9 @@
type,count
nodes,2663055
nodes,6124690
package_pins,676
pips,29424910
site_pins,740913
site_pips,1505860
sites,20251
tiles,24453
wires,8339126
pips,67256102
site_pins,1761297
site_pips,3704892
sites,46697
tiles,49590
wires,18471828

1 type count
2 nodes 2663055 6124690
3 package_pins 676
4 pips 29424910 67256102
5 site_pins 740913 1761297
6 site_pips 1505860 3704892
7 sites 20251 46697
8 tiles 24453 49590
9 wires 8339126 18471828

8
kintex7/mapping/devices.yaml
View File

@ -1,3 +1,11 @@
# device to fabric mapping
"xc7k70t":
fabric: "xc7k70t"
"xc7k160t":
fabric: "xc7k160t"
"xc7k325t":
fabric: "xc7k325t"
"xc7k420t":
fabric: "xc7k480t"
"xc7k480t":
fabric: "xc7k480t"

352
kintex7/mapping/parts.yaml
View File

@ -1,3 +1,355 @@
xc7k160tfbg484-1:
device: xc7k160t
package: fbg484
speedgrade: '1'
xc7k160tfbg484-2:
device: xc7k160t
package: fbg484
speedgrade: '2'
xc7k160tfbg484-2L:
device: xc7k160t
package: fbg484
speedgrade: 2L
xc7k160tfbg484-3:
device: xc7k160t
package: fbg484
speedgrade: '3'
xc7k160tfbg676-1:
device: xc7k160t
package: fbg676
speedgrade: '1'
xc7k160tfbg676-2:
device: xc7k160t
package: fbg676
speedgrade: '2'
xc7k160tfbg676-2L:
device: xc7k160t
package: fbg676
speedgrade: 2L
xc7k160tfbg676-3:
device: xc7k160t
package: fbg676
speedgrade: '3'
xc7k160tfbv484-1:
device: xc7k160t
package: fbv484
speedgrade: '1'
xc7k160tfbv484-2:
device: xc7k160t
package: fbv484
speedgrade: '2'
xc7k160tfbv484-2L:
device: xc7k160t
package: fbv484
speedgrade: 2L
xc7k160tfbv484-3:
device: xc7k160t
package: fbv484
speedgrade: '3'
xc7k160tfbv676-1:
device: xc7k160t
package: fbv676
speedgrade: '1'
xc7k160tfbv676-2:
device: xc7k160t
package: fbv676
speedgrade: '2'
xc7k160tfbv676-2L:
device: xc7k160t
package: fbv676
speedgrade: 2L
xc7k160tfbv676-3:
device: xc7k160t
package: fbv676
speedgrade: '3'
xc7k160tffg676-1:
device: xc7k160t
package: ffg676
speedgrade: '1'
xc7k160tffg676-2:
device: xc7k160t
package: ffg676
speedgrade: '2'
xc7k160tffg676-2L:
device: xc7k160t
package: ffg676
speedgrade: 2L
xc7k160tffg676-3:
device: xc7k160t
package: ffg676
speedgrade: '3'
xc7k160tffv676-1:
device: xc7k160t
package: ffv676
speedgrade: '1'
xc7k160tffv676-2:
device: xc7k160t
package: ffv676
speedgrade: '2'
xc7k160tffv676-2L:
device: xc7k160t
package: ffv676
speedgrade: 2L
xc7k160tffv676-3:
device: xc7k160t
package: ffv676
speedgrade: '3'
xc7k325tfbg676-1:
device: xc7k325t
package: fbg676
speedgrade: '1'
xc7k325tfbg676-2:
device: xc7k325t
package: fbg676
speedgrade: '2'
xc7k325tfbg676-2L:
device: xc7k325t
package: fbg676
speedgrade: 2L
xc7k325tfbg676-3:
device: xc7k325t
package: fbg676
speedgrade: '3'
xc7k325tfbg900-1:
device: xc7k325t
package: fbg900
speedgrade: '1'
xc7k325tfbg900-2:
device: xc7k325t
package: fbg900
speedgrade: '2'
xc7k325tfbg900-2L:
device: xc7k325t
package: fbg900
speedgrade: 2L
xc7k325tfbg900-3:
device: xc7k325t
package: fbg900
speedgrade: '3'
xc7k325tfbv676-1:
device: xc7k325t
package: fbv676
speedgrade: '1'
xc7k325tfbv676-2:
device: xc7k325t
package: fbv676
speedgrade: '2'
xc7k325tfbv676-2L:
device: xc7k325t
package: fbv676
speedgrade: 2L
xc7k325tfbv676-3:
device: xc7k325t
package: fbv676
speedgrade: '3'
xc7k325tfbv900-1:
device: xc7k325t
package: fbv900
speedgrade: '1'
xc7k325tfbv900-2:
device: xc7k325t
package: fbv900
speedgrade: '2'
xc7k325tfbv900-2L:
device: xc7k325t
package: fbv900
speedgrade: 2L
xc7k325tfbv900-3:
device: xc7k325t
package: fbv900
speedgrade: '3'
xc7k325tffg676-1:
device: xc7k325t
package: ffg676
speedgrade: '1'
xc7k325tffg676-2:
device: xc7k325t
package: ffg676
speedgrade: '2'
xc7k325tffg676-2L:
device: xc7k325t
package: ffg676
speedgrade: 2L
xc7k325tffg676-3:
device: xc7k325t
package: ffg676
speedgrade: '3'
xc7k325tffg900-1:
device: xc7k325t
package: ffg900
speedgrade: '1'
xc7k325tffg900-2:
device: xc7k325t
package: ffg900
speedgrade: '2'
xc7k325tffg900-2L:
device: xc7k325t
package: ffg900
speedgrade: 2L
xc7k325tffg900-3:
device: xc7k325t
package: ffg900
speedgrade: '3'
xc7k325tffv676-1:
device: xc7k325t
package: ffv676
speedgrade: '1'
xc7k325tffv676-2:
device: xc7k325t
package: ffv676
speedgrade: '2'
xc7k325tffv676-2L:
device: xc7k325t
package: ffv676
speedgrade: 2L
xc7k325tffv676-3:
device: xc7k325t
package: ffv676
speedgrade: '3'
xc7k325tffv900-1:
device: xc7k325t
package: ffv900
speedgrade: '1'
xc7k325tffv900-2:
device: xc7k325t
package: ffv900
speedgrade: '2'
xc7k325tffv900-2L:
device: xc7k325t
package: ffv900
speedgrade: 2L
xc7k325tffv900-3:
device: xc7k325t
package: ffv900
speedgrade: '3'
xc7k420tffg1156-1:
device: xc7k420t
package: ffg1156
speedgrade: '1'
xc7k420tffg1156-2:
device: xc7k420t
package: ffg1156
speedgrade: '2'
xc7k420tffg1156-2L:
device: xc7k420t
package: ffg1156
speedgrade: 2L
xc7k420tffg1156-3:
device: xc7k420t
package: ffg1156
speedgrade: '3'
xc7k420tffg901-1:
device: xc7k420t
package: ffg901
speedgrade: '1'
xc7k420tffg901-2:
device: xc7k420t
package: ffg901
speedgrade: '2'
xc7k420tffg901-2L:
device: xc7k420t
package: ffg901
speedgrade: 2L
xc7k420tffg901-3:
device: xc7k420t
package: ffg901
speedgrade: '3'
xc7k420tffv1156-1:
device: xc7k420t
package: ffv1156
speedgrade: '1'
xc7k420tffv1156-2:
device: xc7k420t
package: ffv1156
speedgrade: '2'
xc7k420tffv1156-2L:
device: xc7k420t
package: ffv1156
speedgrade: 2L
xc7k420tffv1156-3:
device: xc7k420t
package: ffv1156
speedgrade: '3'
xc7k420tffv901-1:
device: xc7k420t
package: ffv901
speedgrade: '1'
xc7k420tffv901-2:
device: xc7k420t
package: ffv901
speedgrade: '2'
xc7k420tffv901-2L:
device: xc7k420t
package: ffv901
speedgrade: 2L
xc7k420tffv901-3:
device: xc7k420t
package: ffv901
speedgrade: '3'
xc7k480tffg1156-1:
device: xc7k480t
package: ffg1156
speedgrade: '1'
xc7k480tffg1156-2:
device: xc7k480t
package: ffg1156
speedgrade: '2'
xc7k480tffg1156-2L:
device: xc7k480t
package: ffg1156
speedgrade: 2L
xc7k480tffg1156-3:
device: xc7k480t
package: ffg1156
speedgrade: '3'
xc7k480tffg901-1:
device: xc7k480t
package: ffg901
speedgrade: '1'
xc7k480tffg901-2:
device: xc7k480t
package: ffg901
speedgrade: '2'
xc7k480tffg901-2L:
device: xc7k480t
package: ffg901
speedgrade: 2L
xc7k480tffg901-3:
device: xc7k480t
package: ffg901
speedgrade: '3'
xc7k480tffv1156-1:
device: xc7k480t
package: ffv1156
speedgrade: '1'
xc7k480tffv1156-2:
device: xc7k480t
package: ffv1156
speedgrade: '2'
xc7k480tffv1156-2L:
device: xc7k480t
package: ffv1156
speedgrade: 2L
xc7k480tffv1156-3:
device: xc7k480t
package: ffv1156
speedgrade: '3'
xc7k480tffv901-1:
device: xc7k480t
package: ffv901
speedgrade: '1'
xc7k480tffv901-2:
device: xc7k480t
package: ffv901
speedgrade: '2'
xc7k480tffv901-2L:
device: xc7k480t
package: ffv901
speedgrade: 2L
xc7k480tffv901-3:
device: xc7k480t
package: ffv901
speedgrade: '3'
xc7k70tfbg484-1:
device: xc7k70t
package: fbg484

53332
kintex7/mask_bram_l.block_ram.db
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File diff suppressed because it is too large Load Diff

1794
kintex7/mask_bram_l.db
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File diff suppressed because it is too large Load Diff

53332
kintex7/mask_bram_r.block_ram.db
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File diff suppressed because it is too large Load Diff

1794
kintex7/mask_bram_r.db
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File diff suppressed because it is too large Load Diff

1254
kintex7/mask_clk_bufg_bot_r.db
View File

File diff suppressed because it is too large Load Diff

48
kintex7/mask_clk_bufg_rebuf.db
View File

@ -2,7 +2,19 @@ bit 26_00
bit 26_01
bit 26_02
bit 26_03
bit 26_108
bit 26_109
bit 26_110
bit 26_111
bit 26_112
bit 26_113
bit 26_114
bit 26_115
bit 26_12
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_13
bit 26_14
bit 26_15
@ -50,23 +62,23 @@ bit 26_96
bit 26_97
bit 26_98
bit 26_99
bit 26_108
bit 26_109
bit 26_110
bit 26_111
bit 26_112
bit 26_113
bit 26_114
bit 26_115
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 27_00
bit 27_01
bit 27_02
bit 27_03
bit 27_108
bit 27_109
bit 27_110
bit 27_111
bit 27_112
bit 27_113
bit 27_114
bit 27_115
bit 27_12
bit 27_124
bit 27_125
bit 27_126
bit 27_127
bit 27_13
bit 27_14
bit 27_15
@ -114,15 +126,3 @@ bit 27_96
bit 27_97
bit 27_98
bit 27_99
bit 27_108
bit 27_109
bit 27_110
bit 27_111
bit 27_112
bit 27_113
bit 27_114
bit 27_115
bit 27_124
bit 27_125
bit 27_126
bit 27_127

1254
kintex7/mask_clk_bufg_top_r.db
View File

File diff suppressed because it is too large Load Diff

280
kintex7/mask_clk_hrow_bot_r.db
View File

@ -22,46 +22,6 @@ bit 21_232
bit 21_328
bit 25_232
bit 25_328
bit 26_20
bit 26_24
bit 26_25
bit 26_26
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_36
bit 26_40
bit 26_41
bit 26_42
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_52
bit 26_56
bit 26_57
bit 26_58
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_68
bit 26_72
bit 26_73
bit 26_74
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_84
bit 26_88
bit 26_89
bit 26_90
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_100
bit 26_104
bit 26_105
@ -105,6 +65,7 @@ bit 26_189
bit 26_190
bit 26_191
bit 26_195
bit 26_20
bit 26_200
bit 26_201
bit 26_202
@ -131,17 +92,20 @@ bit 26_236
bit 26_237
bit 26_238
bit 26_239
bit 26_24
bit 26_240
bit 26_241
bit 26_243
bit 26_248
bit 26_249
bit 26_25
bit 26_250
bit 26_251
bit 26_252
bit 26_253
bit 26_254
bit 26_255
bit 26_26
bit 26_270
bit 26_271
bit 26_274
@ -150,6 +114,7 @@ bit 26_276
bit 26_277
bit 26_278
bit 26_279
bit 26_28
bit 26_280
bit 26_281
bit 26_282
@ -158,16 +123,19 @@ bit 26_284
bit 26_285
bit 26_286
bit 26_287
bit 26_29
bit 26_291
bit 26_296
bit 26_297
bit 26_298
bit 26_299
bit 26_30
bit 26_300
bit 26_301
bit 26_302
bit 26_303
bit 26_307
bit 26_31
bit 26_312
bit 26_313
bit 26_314
@ -195,6 +163,7 @@ bit 26_349
bit 26_350
bit 26_351
bit 26_355
bit 26_36
bit 26_360
bit 26_361
bit 26_362
@ -212,14 +181,17 @@ bit 26_380
bit 26_381
bit 26_382
bit 26_383
bit 26_40
bit 26_404
bit 26_408
bit 26_409
bit 26_41
bit 26_410
bit 26_412
bit 26_413
bit 26_414
bit 26_415
bit 26_42
bit 26_420
bit 26_424
bit 26_425
@ -229,6 +201,7 @@ bit 26_429
bit 26_430
bit 26_431
bit 26_436
bit 26_44
bit 26_440
bit 26_441
bit 26_442
@ -236,15 +209,18 @@ bit 26_444
bit 26_445
bit 26_446
bit 26_447
bit 26_45
bit 26_452
bit 26_456
bit 26_457
bit 26_458
bit 26_46
bit 26_460
bit 26_461
bit 26_462
bit 26_463
bit 26_468
bit 26_47
bit 26_472
bit 26_473
bit 26_474
@ -269,6 +245,7 @@ bit 26_509
bit 26_510
bit 26_511
bit 26_516
bit 26_52
bit 26_520
bit 26_521
bit 26_522
@ -276,36 +253,29 @@ bit 26_524
bit 26_525
bit 26_526
bit 26_527
bit 27_24
bit 27_25
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_40
bit 27_41
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_56
bit 27_57
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_72
bit 27_73
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_88
bit 27_89
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 26_56
bit 26_57
bit 26_58
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_68
bit 26_72
bit 26_73
bit 26_74
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_84
bit 26_88
bit 26_89
bit 26_90
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 27_104
bit 27_105
bit 27_108
@ -379,6 +349,7 @@ bit 27_236
bit 27_237
bit 27_238
bit 27_239
bit 27_24
bit 27_240
bit 27_241
bit 27_243
@ -386,6 +357,7 @@ bit 27_246
bit 27_247
bit 27_248
bit 27_249
bit 27_25
bit 27_250
bit 27_251
bit 27_252
@ -400,6 +372,7 @@ bit 27_276
bit 27_277
bit 27_278
bit 27_279
bit 27_28
bit 27_280
bit 27_281
bit 27_282
@ -408,6 +381,7 @@ bit 27_284
bit 27_285
bit 27_286
bit 27_287
bit 27_29
bit 27_291
bit 27_294
bit 27_295
@ -415,11 +389,13 @@ bit 27_296
bit 27_297
bit 27_298
bit 27_299
bit 27_30
bit 27_300
bit 27_301
bit 27_302
bit 27_303
bit 27_307
bit 27_31
bit 27_310
bit 27_311
bit 27_312
@ -474,8 +450,10 @@ bit 27_380
bit 27_381
bit 27_382
bit 27_383
bit 27_40
bit 27_408
bit 27_409
bit 27_41
bit 27_412
bit 27_413
bit 27_414
@ -486,18 +464,22 @@ bit 27_428
bit 27_429
bit 27_430
bit 27_431
bit 27_44
bit 27_440
bit 27_441
bit 27_444
bit 27_445
bit 27_446
bit 27_447
bit 27_45
bit 27_456
bit 27_457
bit 27_46
bit 27_460
bit 27_461
bit 27_462
bit 27_463
bit 27_47
bit 27_472
bit 27_473
bit 27_476
@ -522,46 +504,24 @@ bit 27_524
bit 27_525
bit 27_526
bit 27_527
bit 28_20
bit 28_24
bit 28_25
bit 28_26
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 28_36
bit 28_40
bit 28_41
bit 28_42
bit 28_44
bit 28_45
bit 28_46
bit 28_47
bit 28_52
bit 28_56
bit 28_57
bit 28_58
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_68
bit 28_72
bit 28_73
bit 28_74
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_84
bit 28_88
bit 28_89
bit 28_90
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 27_56
bit 27_57
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_72
bit 27_73
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_88
bit 27_89
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 28_100
bit 28_104
bit 28_105
@ -605,6 +565,7 @@ bit 28_189
bit 28_190
bit 28_191
bit 28_195
bit 28_20
bit 28_200
bit 28_201
bit 28_202
@ -631,17 +592,20 @@ bit 28_236
bit 28_237
bit 28_238
bit 28_239
bit 28_24
bit 28_240
bit 28_241
bit 28_243
bit 28_248
bit 28_249
bit 28_25
bit 28_250
bit 28_251
bit 28_252
bit 28_253
bit 28_254
bit 28_255
bit 28_26
bit 28_270
bit 28_271
bit 28_274
@ -650,6 +614,7 @@ bit 28_276
bit 28_277
bit 28_278
bit 28_279
bit 28_28
bit 28_280
bit 28_281
bit 28_282
@ -658,16 +623,19 @@ bit 28_284
bit 28_285
bit 28_286
bit 28_287
bit 28_29
bit 28_291
bit 28_296
bit 28_297
bit 28_298
bit 28_299
bit 28_30
bit 28_300
bit 28_301
bit 28_302
bit 28_303
bit 28_307
bit 28_31
bit 28_312
bit 28_313
bit 28_314
@ -695,6 +663,7 @@ bit 28_349
bit 28_350
bit 28_351
bit 28_355
bit 28_36
bit 28_360
bit 28_361
bit 28_362
@ -712,14 +681,17 @@ bit 28_380
bit 28_381
bit 28_382
bit 28_383
bit 28_40
bit 28_404
bit 28_408
bit 28_409
bit 28_41
bit 28_410
bit 28_412
bit 28_413
bit 28_414
bit 28_415
bit 28_42
bit 28_420
bit 28_424
bit 28_425
@ -729,6 +701,7 @@ bit 28_429
bit 28_430
bit 28_431
bit 28_436
bit 28_44
bit 28_440
bit 28_441
bit 28_442
@ -736,15 +709,18 @@ bit 28_444
bit 28_445
bit 28_446
bit 28_447
bit 28_45
bit 28_452
bit 28_456
bit 28_457
bit 28_458
bit 28_46
bit 28_460
bit 28_461
bit 28_462
bit 28_463
bit 28_468
bit 28_47
bit 28_472
bit 28_473
bit 28_474
@ -769,6 +745,7 @@ bit 28_509
bit 28_510
bit 28_511
bit 28_516
bit 28_52
bit 28_520
bit 28_521
bit 28_522
@ -776,36 +753,29 @@ bit 28_524
bit 28_525
bit 28_526
bit 28_527
bit 29_24
bit 29_25
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 29_40
bit 29_41
bit 29_44
bit 29_45
bit 29_46
bit 29_47
bit 29_56
bit 29_57
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_72
bit 29_73
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_88
bit 29_89
bit 29_92
bit 29_93
bit 29_94
bit 29_95
bit 28_56
bit 28_57
bit 28_58
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_68
bit 28_72
bit 28_73
bit 28_74
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_84
bit 28_88
bit 28_89
bit 28_90
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 29_104
bit 29_105
bit 29_108
@ -879,6 +849,7 @@ bit 29_236
bit 29_237
bit 29_238
bit 29_239
bit 29_24
bit 29_240
bit 29_241
bit 29_243
@ -886,6 +857,7 @@ bit 29_246
bit 29_247
bit 29_248
bit 29_249
bit 29_25
bit 29_250
bit 29_251
bit 29_252
@ -900,6 +872,7 @@ bit 29_276
bit 29_277
bit 29_278
bit 29_279
bit 29_28
bit 29_280
bit 29_281
bit 29_282
@ -908,6 +881,7 @@ bit 29_284
bit 29_285
bit 29_286
bit 29_287
bit 29_29
bit 29_291
bit 29_294
bit 29_295
@ -915,11 +889,13 @@ bit 29_296
bit 29_297
bit 29_298
bit 29_299
bit 29_30
bit 29_300
bit 29_301
bit 29_302
bit 29_303
bit 29_307
bit 29_31
bit 29_310
bit 29_311
bit 29_312
@ -974,8 +950,10 @@ bit 29_380
bit 29_381
bit 29_382
bit 29_383
bit 29_40
bit 29_408
bit 29_409
bit 29_41
bit 29_412
bit 29_413
bit 29_414
@ -986,18 +964,22 @@ bit 29_428
bit 29_429
bit 29_430
bit 29_431
bit 29_44
bit 29_440
bit 29_441
bit 29_444
bit 29_445
bit 29_446
bit 29_447
bit 29_45
bit 29_456
bit 29_457
bit 29_46
bit 29_460
bit 29_461
bit 29_462
bit 29_463
bit 29_47
bit 29_472
bit 29_473
bit 29_476
@ -1022,3 +1004,21 @@ bit 29_524
bit 29_525
bit 29_526
bit 29_527
bit 29_56
bit 29_57
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_72
bit 29_73
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_88
bit 29_89
bit 29_92
bit 29_93
bit 29_94
bit 29_95

240
kintex7/mask_clk_hrow_top_r.db
View File

@ -22,41 +22,6 @@ bit 21_232
bit 21_328
bit 25_232
bit 25_328
bit 26_20
bit 26_24
bit 26_26
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_36
bit 26_40
bit 26_42
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_52
bit 26_56
bit 26_58
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_68
bit 26_72
bit 26_74
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_84
bit 26_88
bit 26_90
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_100
bit 26_104
bit 26_106
@ -95,6 +60,7 @@ bit 26_189
bit 26_190
bit 26_191
bit 26_195
bit 26_20
bit 26_200
bit 26_202
bit 26_203
@ -118,6 +84,7 @@ bit 26_236
bit 26_237
bit 26_238
bit 26_239
bit 26_24
bit 26_240
bit 26_241
bit 26_243
@ -128,6 +95,7 @@ bit 26_252
bit 26_253
bit 26_254
bit 26_255
bit 26_26
bit 26_270
bit 26_271
bit 26_274
@ -136,6 +104,7 @@ bit 26_276
bit 26_277
bit 26_278
bit 26_279
bit 26_28
bit 26_280
bit 26_281
bit 26_282
@ -144,15 +113,18 @@ bit 26_284
bit 26_285
bit 26_286
bit 26_287
bit 26_29
bit 26_291
bit 26_296
bit 26_298
bit 26_299
bit 26_30
bit 26_300
bit 26_301
bit 26_302
bit 26_303
bit 26_307
bit 26_31
bit 26_312
bit 26_314
bit 26_315
@ -177,6 +149,7 @@ bit 26_349
bit 26_350
bit 26_351
bit 26_355
bit 26_36
bit 26_360
bit 26_362
bit 26_363
@ -192,6 +165,7 @@ bit 26_380
bit 26_381
bit 26_382
bit 26_383
bit 26_40
bit 26_404
bit 26_408
bit 26_410
@ -199,6 +173,7 @@ bit 26_412
bit 26_413
bit 26_414
bit 26_415
bit 26_42
bit 26_420
bit 26_424
bit 26_426
@ -207,20 +182,24 @@ bit 26_429
bit 26_430
bit 26_431
bit 26_436
bit 26_44
bit 26_440
bit 26_442
bit 26_444
bit 26_445
bit 26_446
bit 26_447
bit 26_45
bit 26_452
bit 26_456
bit 26_458
bit 26_46
bit 26_460
bit 26_461
bit 26_462
bit 26_463
bit 26_468
bit 26_47
bit 26_472
bit 26_474
bit 26_476
@ -242,37 +221,33 @@ bit 26_509
bit 26_510
bit 26_511
bit 26_516
bit 26_52
bit 26_520
bit 26_522
bit 26_524
bit 26_525
bit 26_526
bit 26_527
bit 27_24
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_40
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_56
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_72
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_88
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 26_56
bit 26_58
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_68
bit 26_72
bit 26_74
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_84
bit 26_88
bit 26_90
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 27_104
bit 27_108
bit 27_109
@ -343,6 +318,7 @@ bit 27_236
bit 27_237
bit 27_238
bit 27_239
bit 27_24
bit 27_240
bit 27_241
bit 27_243
@ -364,6 +340,7 @@ bit 27_276
bit 27_277
bit 27_278
bit 27_279
bit 27_28
bit 27_280
bit 27_281
bit 27_282
@ -372,6 +349,7 @@ bit 27_284
bit 27_285
bit 27_286
bit 27_287
bit 27_29
bit 27_291
bit 27_294
bit 27_295
@ -379,11 +357,13 @@ bit 27_296
bit 27_297
bit 27_298
bit 27_299
bit 27_30
bit 27_300
bit 27_301
bit 27_302
bit 27_303
bit 27_307
bit 27_31
bit 27_310
bit 27_311
bit 27_312
@ -438,6 +418,7 @@ bit 27_380
bit 27_381
bit 27_382
bit 27_383
bit 27_40
bit 27_408
bit 27_412
bit 27_413
@ -448,16 +429,20 @@ bit 27_428
bit 27_429
bit 27_430
bit 27_431
bit 27_44
bit 27_440
bit 27_444
bit 27_445
bit 27_446
bit 27_447
bit 27_45
bit 27_456
bit 27_46
bit 27_460
bit 27_461
bit 27_462
bit 27_463
bit 27_47
bit 27_472
bit 27_476
bit 27_477
@ -478,41 +463,21 @@ bit 27_524
bit 27_525
bit 27_526
bit 27_527
bit 28_20
bit 28_24
bit 28_26
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 28_36
bit 28_40
bit 28_42
bit 28_44
bit 28_45
bit 28_46
bit 28_47
bit 28_52
bit 28_56
bit 28_58
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_68
bit 28_72
bit 28_74
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_84
bit 28_88
bit 28_90
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 27_56
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_72
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_88
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 28_100
bit 28_104
bit 28_106
@ -551,6 +516,7 @@ bit 28_189
bit 28_190
bit 28_191
bit 28_195
bit 28_20
bit 28_200
bit 28_202
bit 28_203
@ -574,6 +540,7 @@ bit 28_236
bit 28_237
bit 28_238
bit 28_239
bit 28_24
bit 28_243
bit 28_248
bit 28_250
@ -582,7 +549,9 @@ bit 28_252
bit 28_253
bit 28_254
bit 28_255
bit 28_26
bit 28_279
bit 28_28
bit 28_280
bit 28_281
bit 28_282
@ -591,15 +560,18 @@ bit 28_284
bit 28_285
bit 28_286
bit 28_287
bit 28_29
bit 28_291
bit 28_296
bit 28_298
bit 28_299
bit 28_30
bit 28_300
bit 28_301
bit 28_302
bit 28_303
bit 28_307
bit 28_31
bit 28_312
bit 28_314
bit 28_315
@ -624,6 +596,7 @@ bit 28_349
bit 28_350
bit 28_351
bit 28_355
bit 28_36
bit 28_360
bit 28_362
bit 28_363
@ -639,6 +612,7 @@ bit 28_380
bit 28_381
bit 28_382
bit 28_383
bit 28_40
bit 28_404
bit 28_408
bit 28_410
@ -646,6 +620,7 @@ bit 28_412
bit 28_413
bit 28_414
bit 28_415
bit 28_42
bit 28_420
bit 28_424
bit 28_426
@ -654,20 +629,24 @@ bit 28_429
bit 28_430
bit 28_431
bit 28_436
bit 28_44
bit 28_440
bit 28_442
bit 28_444
bit 28_445
bit 28_446
bit 28_447
bit 28_45
bit 28_452
bit 28_456
bit 28_458
bit 28_46
bit 28_460
bit 28_461
bit 28_462
bit 28_463
bit 28_468
bit 28_47
bit 28_472
bit 28_474
bit 28_476
@ -689,37 +668,33 @@ bit 28_509
bit 28_510
bit 28_511
bit 28_516
bit 28_52
bit 28_520
bit 28_522
bit 28_524
bit 28_525
bit 28_526
bit 28_527
bit 29_24
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 29_40
bit 29_44
bit 29_45
bit 29_46
bit 29_47
bit 29_56
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_72
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_88
bit 29_92
bit 29_93
bit 29_94
bit 29_95
bit 28_56
bit 28_58
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_68
bit 28_72
bit 28_74
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_84
bit 28_88
bit 28_90
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 29_104
bit 29_108
bit 29_109
@ -790,6 +765,7 @@ bit 29_236
bit 29_237
bit 29_238
bit 29_239
bit 29_24
bit 29_243
bit 29_246
bit 29_247
@ -802,6 +778,7 @@ bit 29_253
bit 29_254
bit 29_255
bit 29_279
bit 29_28
bit 29_280
bit 29_281
bit 29_282
@ -810,6 +787,7 @@ bit 29_284
bit 29_285
bit 29_286
bit 29_287
bit 29_29
bit 29_291
bit 29_294
bit 29_295
@ -817,11 +795,13 @@ bit 29_296
bit 29_297
bit 29_298
bit 29_299
bit 29_30
bit 29_300
bit 29_301
bit 29_302
bit 29_303
bit 29_307
bit 29_31
bit 29_310
bit 29_311
bit 29_312
@ -876,6 +856,7 @@ bit 29_380
bit 29_381
bit 29_382
bit 29_383
bit 29_40
bit 29_408
bit 29_412
bit 29_413
@ -886,16 +867,20 @@ bit 29_428
bit 29_429
bit 29_430
bit 29_431
bit 29_44
bit 29_440
bit 29_444
bit 29_445
bit 29_446
bit 29_447
bit 29_45
bit 29_456
bit 29_46
bit 29_460
bit 29_461
bit 29_462
bit 29_463
bit 29_47
bit 29_472
bit 29_476
bit 29_477
@ -916,3 +901,18 @@ bit 29_524
bit 29_525
bit 29_526
bit 29_527
bit 29_56
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_72
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_88
bit 29_92
bit 29_93
bit 29_94
bit 29_95

938
kintex7/mask_dsp_l.db
View File

File diff suppressed because it is too large Load Diff

1260
kintex7/mask_dsp_r.db
View File

File diff suppressed because it is too large Load Diff

42
kintex7/mask_liob33.db
View File

@ -4,6 +4,15 @@ bit 38_04
bit 38_06
bit 38_08
bit 38_10
bit 38_100
bit 38_102
bit 38_106
bit 38_110
bit 38_112
bit 38_118
bit 38_120
bit 38_122
bit 38_126
bit 38_14
bit 38_16
bit 38_18
@ -25,19 +34,22 @@ bit 38_86
bit 38_92
bit 38_94
bit 38_98
bit 38_100
bit 38_102
bit 38_106
bit 38_110
bit 38_112
bit 38_118
bit 38_120
bit 38_122
bit 38_126
bit 39_01
bit 39_05
bit 39_07
bit 39_09
bit 39_101
bit 39_105
bit 39_107
bit 39_109
bit 39_111
bit 39_113
bit 39_117
bit 39_119
bit 39_121
bit 39_123
bit 39_125
bit 39_127
bit 39_15
bit 39_17
bit 39_21
@ -58,15 +70,3 @@ bit 39_89
bit 39_93
bit 39_95
bit 39_97
bit 39_101
bit 39_105
bit 39_107
bit 39_109
bit 39_111
bit 39_113
bit 39_117
bit 39_119
bit 39_121
bit 39_123
bit 39_125
bit 39_127

142
kintex7/mask_lioi3.db
View File

@ -1,4 +1,10 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
@ -18,13 +24,15 @@ bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
@ -35,17 +43,15 @@ bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
@ -56,15 +62,16 @@ bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
@ -92,18 +99,18 @@ bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
@ -129,13 +136,6 @@ bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
@ -143,6 +143,11 @@ bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
@ -175,15 +180,23 @@ bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
@ -211,19 +224,9 @@ bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
@ -244,9 +247,8 @@ bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
@ -268,17 +270,7 @@ bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
@ -288,9 +280,19 @@ bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_19
@ -304,22 +306,20 @@ bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_118
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_113
bit 39_119
bit 39_125
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

142
kintex7/mask_lioi3_tbytesrc.db
View File

@ -1,4 +1,10 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
@ -18,13 +24,15 @@ bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
@ -35,17 +43,15 @@ bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
@ -56,15 +62,16 @@ bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
@ -92,18 +99,18 @@ bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
@ -129,13 +136,6 @@ bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
@ -143,6 +143,11 @@ bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
@ -175,15 +180,23 @@ bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
@ -211,19 +224,9 @@ bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
@ -244,9 +247,8 @@ bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
@ -268,17 +270,7 @@ bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
@ -288,9 +280,19 @@ bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_19
@ -304,22 +306,20 @@ bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_118
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_113
bit 39_119
bit 39_125
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

142
kintex7/mask_lioi3_tbyteterm.db
View File

@ -1,4 +1,10 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
@ -18,13 +24,15 @@ bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
@ -35,17 +43,15 @@ bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
@ -56,15 +62,16 @@ bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
@ -92,18 +99,18 @@ bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
@ -129,13 +136,6 @@ bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
@ -143,6 +143,11 @@ bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
@ -175,15 +180,23 @@ bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
@ -211,19 +224,9 @@ bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
@ -244,9 +247,8 @@ bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
@ -268,17 +270,7 @@ bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
@ -288,9 +280,19 @@ bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_19
@ -304,22 +306,20 @@ bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_118
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_113
bit 39_119
bit 39_125
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

75
kintex7/mask_riob18.db Normal file
View File

@ -0,0 +1,75 @@
bit 38_00
bit 38_02
bit 38_04
bit 38_08
bit 38_10
bit 38_104
bit 38_114
bit 38_12
bit 38_124
bit 38_126
bit 38_14
bit 38_16
bit 38_20
bit 38_22
bit 38_24
bit 38_26
bit 38_28
bit 38_30
bit 38_32
bit 38_34
bit 38_38
bit 38_40
bit 38_44
bit 38_46
bit 38_48
bit 38_50
bit 38_62
bit 38_72
bit 38_78
bit 38_80
bit 38_82
bit 38_86
bit 38_88
bit 38_92
bit 38_94
bit 38_96
bit 39_01
bit 39_03
bit 39_101
bit 39_103
bit 39_105
bit 39_107
bit 39_111
bit 39_113
bit 39_115
bit 39_117
bit 39_123
bit 39_125
bit 39_127
bit 39_13
bit 39_15
bit 39_17
bit 39_21
bit 39_23
bit 39_31
bit 39_33
bit 39_35
bit 39_37
bit 39_39
bit 39_41
bit 39_43
bit 39_45
bit 39_47
bit 39_49
bit 39_55
bit 39_65
bit 39_73
bit 39_77
bit 39_79
bit 39_81
bit 39_83
bit 39_89
bit 39_93
bit 39_95
bit 39_97

42
kintex7/mask_riob33.db
View File

@ -4,6 +4,15 @@ bit 38_04
bit 38_06
bit 38_08
bit 38_10
bit 38_100
bit 38_102
bit 38_106
bit 38_110
bit 38_112
bit 38_118
bit 38_120
bit 38_122
bit 38_126
bit 38_14
bit 38_16
bit 38_18
@ -25,19 +34,22 @@ bit 38_86
bit 38_92
bit 38_94
bit 38_98
bit 38_100
bit 38_102
bit 38_106
bit 38_110
bit 38_112
bit 38_118
bit 38_120
bit 38_122
bit 38_126
bit 39_01
bit 39_05
bit 39_07
bit 39_09
bit 39_101
bit 39_105
bit 39_107
bit 39_109
bit 39_111
bit 39_113
bit 39_117
bit 39_119
bit 39_121
bit 39_123
bit 39_125
bit 39_127
bit 39_15
bit 39_17
bit 39_21
@ -58,15 +70,3 @@ bit 39_89
bit 39_93
bit 39_95
bit 39_97
bit 39_101
bit 39_105
bit 39_107
bit 39_109
bit 39_111
bit 39_113
bit 39_117
bit 39_119
bit 39_121
bit 39_123
bit 39_125
bit 39_127

366
kintex7/mask_rioi.db Normal file
View File

@ -0,0 +1,366 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 34_08
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_109
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_55
bit 34_58
bit 34_72
bit 34_73
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_18
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_54
bit 35_55
bit 35_69
bit 35_72
bit 35_81
bit 35_89
bit 36_08
bit 36_100
bit 36_102
bit 36_108
bit 36_110
bit 36_114
bit 36_116
bit 36_120
bit 36_122
bit 36_14
bit 36_38
bit 36_72
bit 36_88
bit 36_94
bit 36_96
bit 37_05
bit 37_07
bit 37_11
bit 37_113
bit 37_119
bit 37_13
bit 37_17
bit 37_19
bit 37_25
bit 37_27
bit 37_31
bit 37_33
bit 37_39
bit 37_55
bit 37_89
bit 38_00
bit 38_12
bit 38_126
bit 38_24
bit 38_32
bit 38_34
bit 38_48
bit 38_52
bit 38_78
bit 38_80
bit 38_94
bit 39_01
bit 39_103
bit 39_115
bit 39_127
bit 39_33
bit 39_47
bit 39_49
bit 39_75
bit 39_79
bit 39_93
bit 39_95

142
kintex7/mask_rioi3.db
View File

@ -1,4 +1,10 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
@ -18,13 +24,15 @@ bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
@ -35,17 +43,15 @@ bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
@ -56,15 +62,16 @@ bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
@ -92,18 +99,18 @@ bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
@ -129,13 +136,6 @@ bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
@ -143,6 +143,11 @@ bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
@ -175,15 +180,23 @@ bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
@ -211,19 +224,9 @@ bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
@ -244,9 +247,8 @@ bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
@ -268,17 +270,7 @@ bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
@ -288,9 +280,19 @@ bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_19
@ -304,22 +306,20 @@ bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_118
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_113
bit 39_119
bit 39_125
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

142
kintex7/mask_rioi3_tbytesrc.db
View File

@ -1,4 +1,10 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
@ -18,13 +24,15 @@ bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
@ -35,17 +43,15 @@ bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
@ -56,15 +62,16 @@ bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
@ -92,18 +99,18 @@ bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
@ -129,13 +136,6 @@ bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
@ -143,6 +143,11 @@ bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
@ -175,15 +180,23 @@ bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
@ -211,19 +224,9 @@ bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
@ -244,9 +247,8 @@ bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
@ -268,17 +270,7 @@ bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
@ -288,9 +280,19 @@ bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_19
@ -304,22 +306,20 @@ bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_118
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_113
bit 39_119
bit 39_125
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

142
kintex7/mask_rioi3_tbyteterm.db
View File

@ -1,4 +1,10 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
@ -18,13 +24,15 @@ bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
@ -35,17 +43,15 @@ bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
@ -56,15 +62,16 @@ bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
@ -92,18 +99,18 @@ bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
@ -129,13 +136,6 @@ bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 29_101
bit 29_103
bit 29_109
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 30_01
bit 30_03
bit 30_04
@ -143,6 +143,11 @@ bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
@ -175,15 +180,23 @@ bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
@ -211,19 +224,9 @@ bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
@ -244,9 +247,8 @@ bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 32_108
bit 32_109
bit 32_112
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
@ -268,17 +270,7 @@ bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 33_107
bit 33_111
bit 34_08
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 34_100
bit 34_102
bit 34_106
@ -288,9 +280,19 @@ bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_58
bit 34_72
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_19
@ -304,22 +306,20 @@ bit 35_55
bit 35_69
bit 35_81
bit 35_89
bit 35_113
bit 35_119
bit 38_02
bit 38_08
bit 38_118
bit 38_14
bit 38_32
bit 38_42
bit 38_86
bit 38_94
bit 38_118
bit 39_09
bit 39_113
bit 39_119
bit 39_125
bit 39_33
bit 39_41
bit 39_85
bit 39_93
bit 39_95
bit 39_113
bit 39_119
bit 39_125

366
kintex7/mask_rioi_tbytesrc.db Normal file
View File

@ -0,0 +1,366 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 34_08
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_109
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_55
bit 34_58
bit 34_72
bit 34_73
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_18
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_54
bit 35_55
bit 35_69
bit 35_72
bit 35_81
bit 35_89
bit 36_08
bit 36_100
bit 36_102
bit 36_108
bit 36_110
bit 36_114
bit 36_116
bit 36_120
bit 36_122
bit 36_14
bit 36_38
bit 36_72
bit 36_88
bit 36_94
bit 36_96
bit 37_05
bit 37_07
bit 37_11
bit 37_113
bit 37_119
bit 37_13
bit 37_17
bit 37_19
bit 37_25
bit 37_27
bit 37_31
bit 37_33
bit 37_39
bit 37_55
bit 37_89
bit 38_00
bit 38_12
bit 38_126
bit 38_24
bit 38_32
bit 38_34
bit 38_48
bit 38_52
bit 38_78
bit 38_80
bit 38_94
bit 39_01
bit 39_103
bit 39_115
bit 39_127
bit 39_33
bit 39_47
bit 39_49
bit 39_75
bit 39_79
bit 39_93
bit 39_95

366
kintex7/mask_rioi_tbyteterm.db Normal file
View File

@ -0,0 +1,366 @@
bit 25_07
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 34_08
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_109
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_55
bit 34_58
bit 34_72
bit 34_73
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_18
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_54
bit 35_55
bit 35_69
bit 35_72
bit 35_81
bit 35_89
bit 36_08
bit 36_100
bit 36_102
bit 36_108
bit 36_110
bit 36_114
bit 36_116
bit 36_120
bit 36_122
bit 36_14
bit 36_38
bit 36_72
bit 36_88
bit 36_94
bit 36_96
bit 37_05
bit 37_07
bit 37_11
bit 37_113
bit 37_119
bit 37_13
bit 37_17
bit 37_19
bit 37_25
bit 37_27
bit 37_31
bit 37_33
bit 37_39
bit 37_55
bit 37_89
bit 38_00
bit 38_12
bit 38_126
bit 38_24
bit 38_32
bit 38_34
bit 38_48
bit 38_52
bit 38_78
bit 38_80
bit 38_94
bit 39_01
bit 39_103
bit 39_115
bit 39_127
bit 39_33
bit 39_47
bit 39_49
bit 39_75
bit 39_79
bit 39_93
bit 39_95

18
kintex7/ppips_bram_int_interface_l.db
View File

@ -1,13 +1,4 @@
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
@ -18,7 +9,16 @@ BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always

18
kintex7/ppips_bram_int_interface_r.db
View File

@ -1,13 +1,4 @@
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
@ -18,7 +9,16 @@ BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 alw
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always

1226
kintex7/ppips_bram_l.db
View File

File diff suppressed because it is too large Load Diff

1302
kintex7/ppips_bram_r.db
View File

File diff suppressed because it is too large Load Diff

116
kintex7/ppips_clbll_l.db
View File

@ -1,3 +1,9 @@
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A3 hint
@ -6,6 +12,12 @@ CLBLL_L.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint
@ -14,6 +26,12 @@ CLBLL_L.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C3 hint
@ -25,6 +43,12 @@ CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D3 hint
@ -34,31 +58,12 @@ CLBLL_L.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint
@ -67,6 +72,12 @@ CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint
@ -75,6 +86,12 @@ CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint
@ -86,6 +103,12 @@ CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint
@ -96,40 +119,7 @@ CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
@ -140,7 +130,17 @@ CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always

116
kintex7/ppips_clbll_r.db
View File

@ -1,3 +1,9 @@
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A3 hint
@ -6,6 +12,12 @@ CLBLL_R.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B3 hint
@ -14,6 +26,12 @@ CLBLL_R.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C3 hint
@ -25,6 +43,12 @@ CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D3 hint
@ -34,31 +58,12 @@ CLBLL_R.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint
@ -67,6 +72,12 @@ CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint
@ -75,6 +86,12 @@ CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint
@ -86,6 +103,12 @@ CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint
@ -96,40 +119,7 @@ CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
@ -140,7 +130,17 @@ CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always

116
kintex7/ppips_clblm_l.db
View File

@ -1,3 +1,9 @@
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A3 hint
@ -6,6 +12,12 @@ CLBLM_L.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B3 hint
@ -14,6 +26,12 @@ CLBLM_L.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C3 hint
@ -25,6 +43,12 @@ CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D3 hint
@ -34,41 +58,7 @@ CLBLM_L.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
@ -79,10 +69,26 @@ CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A3 hint
@ -92,6 +98,12 @@ CLBLM_L.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B3 hint
@ -101,6 +113,12 @@ CLBLM_L.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C3 hint
@ -113,6 +131,12 @@ CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_L.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D3 hint
@ -125,27 +149,3 @@ CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always

116
kintex7/ppips_clblm_r.db
View File

@ -1,3 +1,9 @@
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A3 hint
@ -6,6 +12,12 @@ CLBLM_R.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B3 hint
@ -14,6 +26,12 @@ CLBLM_R.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C3 hint
@ -25,6 +43,12 @@ CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D3 hint
@ -34,41 +58,7 @@ CLBLM_R.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
@ -79,10 +69,26 @@ CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A3 hint
@ -92,6 +98,12 @@ CLBLM_R.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B3 hint
@ -101,6 +113,12 @@ CLBLM_R.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C3 hint
@ -113,6 +131,12 @@ CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_R.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D3 hint
@ -125,27 +149,3 @@ CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always

136
kintex7/ppips_clk_bufg_bot_r.db
View File

@ -1,25 +1,61 @@
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
@ -74,55 +110,19 @@ CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always

136
kintex7/ppips_clk_bufg_top_r.db
View File

@ -1,25 +1,61 @@
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
@ -74,55 +110,19 @@ CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always

68
kintex7/ppips_clk_hrow_bot_r.db
View File

@ -1,4 +1,6 @@
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
@ -8,9 +10,9 @@ CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
@ -20,9 +22,9 @@ CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
@ -32,9 +34,9 @@ CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
@ -44,9 +46,9 @@ CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
@ -56,9 +58,9 @@ CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
@ -68,18 +70,7 @@ CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
@ -90,6 +81,7 @@ CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
@ -100,18 +92,17 @@ CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
@ -122,6 +113,7 @@ CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
@ -132,9 +124,19 @@ CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
@ -144,9 +146,9 @@ CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
@ -156,8 +158,6 @@ CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always

68
kintex7/ppips_clk_hrow_top_r.db
View File

@ -1,4 +1,6 @@
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
@ -8,9 +10,9 @@ CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
@ -20,9 +22,9 @@ CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
@ -32,9 +34,9 @@ CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
@ -44,9 +46,9 @@ CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
@ -56,9 +58,9 @@ CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
@ -68,18 +70,7 @@ CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
@ -90,6 +81,7 @@ CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
@ -100,18 +92,17 @@ CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
@ -122,6 +113,7 @@ CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
@ -132,9 +124,19 @@ CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
@ -144,9 +146,9 @@ CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
@ -156,8 +158,6 @@ CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always

102
kintex7/ppips_cmt_top_l_lower_b.db
View File

@ -6,6 +6,10 @@ CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
@ -15,20 +19,8 @@ CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
@ -36,7 +28,15 @@ CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
@ -46,18 +46,24 @@ CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
@ -67,13 +73,13 @@ CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
@ -83,19 +89,8 @@ CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
@ -110,14 +105,26 @@ CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
@ -126,14 +133,13 @@ CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
@ -143,12 +149,6 @@ CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always

164
kintex7/ppips_cmt_top_l_lower_t.db
View File

@ -1,85 +1,91 @@
CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
@ -87,18 +93,6 @@ CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
@ -108,24 +102,24 @@ CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
@ -135,14 +129,20 @@ CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
@ -162,27 +162,10 @@ CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
@ -205,6 +188,7 @@ CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
@ -213,8 +197,25 @@ CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW alwa
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
@ -222,7 +223,6 @@ CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always

278
kintex7/ppips_cmt_top_l_upper_b.db
View File

@ -4,92 +4,83 @@ CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_R_PHASER_IN_C_WRCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_R_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_R_PHASER_IN_C_WRCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_R_PHASER_OUT_C_RDCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_R_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
@ -99,28 +90,28 @@ CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_R_PHASER_OUT_C_RDCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
@ -130,34 +121,33 @@ CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
@ -172,20 +162,14 @@ CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
@ -196,6 +180,7 @@ CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
@ -206,8 +191,23 @@ CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO.CMT_PHASER_OUT_CA_OCLKDIV always
@ -215,6 +215,8 @@ CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDENABLE_FIFO.CMT_PHASER_OUT_CA_RDENABLE al
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
@ -224,9 +226,9 @@ CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
@ -236,12 +238,46 @@ CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
@ -262,44 +298,11 @@ CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 al
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
@ -308,10 +311,9 @@ CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
@ -321,5 +323,3 @@ CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always

98
kintex7/ppips_cmt_top_l_upper_t.db
View File

@ -1,10 +1,13 @@
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
@ -14,10 +17,10 @@ CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
@ -27,32 +30,9 @@ CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
@ -66,12 +46,36 @@ CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
@ -80,11 +84,10 @@ CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
@ -94,15 +97,7 @@ CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
@ -110,7 +105,15 @@ CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
@ -120,12 +123,9 @@ CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always

102
kintex7/ppips_cmt_top_r_lower_b.db
View File

@ -1,13 +1,5 @@
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
@ -15,7 +7,15 @@ CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
@ -25,17 +25,17 @@ CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
@ -44,6 +44,10 @@ CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
@ -53,11 +57,13 @@ CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
@ -67,13 +73,13 @@ CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
@ -83,19 +89,8 @@ CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
@ -110,14 +105,26 @@ CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
@ -126,14 +133,13 @@ CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
@ -143,12 +149,6 @@ CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always

164
kintex7/ppips_cmt_top_r_lower_t.db
View File

@ -1,85 +1,91 @@
CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
@ -87,18 +93,6 @@ CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
@ -108,24 +102,24 @@ CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
@ -135,14 +129,20 @@ CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
@ -162,27 +162,10 @@ CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
@ -205,6 +188,7 @@ CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
@ -213,8 +197,25 @@ CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW alwa
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
@ -222,7 +223,6 @@ CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always

290
kintex7/ppips_cmt_top_r_upper_b.db
View File

@ -2,96 +2,85 @@ CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_PHASER_IN_C_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_PHASER_IN_C_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_PHASER_OUT_C_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDENABLE_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
@ -101,30 +90,30 @@ CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_PHASER_OUT_C_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDENABLE_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
@ -134,34 +123,35 @@ CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
@ -176,20 +166,14 @@ CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
@ -200,6 +184,7 @@ CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
@ -210,11 +195,28 @@ CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
@ -224,9 +226,9 @@ CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
@ -236,12 +238,46 @@ CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
@ -262,44 +298,11 @@ CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 al
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
@ -308,10 +311,9 @@ CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
@ -321,5 +323,3 @@ CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always

76
kintex7/ppips_cmt_top_r_upper_t.db
View File

@ -1,10 +1,13 @@
CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
@ -14,10 +17,10 @@ CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
@ -27,16 +30,8 @@ CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
@ -50,12 +45,21 @@ CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
@ -64,11 +68,10 @@ CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
@ -78,14 +81,7 @@ CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
@ -94,15 +90,14 @@ CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 alwa
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
@ -110,7 +105,15 @@ CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
@ -120,12 +123,9 @@ CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always

468
kintex7/ppips_dsp_l.db
View File

@ -1,29 +1,4 @@
DSP_L.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_L.DSP_0_CEC.DSP_IMUX40_2 always
DSP_L.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_L.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_L.DSP_0_CEM.DSP_IMUX1_2 always
DSP_L.DSP_0_CEP.DSP_IMUX34_2 always
DSP_L.DSP_0_CLK.DSP_CLK0_1 always
DSP_L.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_L.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_L.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_L.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_L.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_L.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_L.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_L.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_L.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_L.DSP_0_A0.DSP_IMUX23_0 always
DSP_L.DSP_0_A1.DSP_IMUX19_0 always
DSP_L.DSP_0_A2.DSP_IMUX21_0 always
DSP_L.DSP_0_A3.DSP_IMUX17_0 always
DSP_L.DSP_0_A4.DSP_IMUX23_1 always
DSP_L.DSP_0_A5.DSP_IMUX19_1 always
DSP_L.DSP_0_A6.DSP_IMUX21_1 always
DSP_L.DSP_0_A7.DSP_IMUX17_1 always
DSP_L.DSP_0_A8.DSP_IMUX23_2 always
DSP_L.DSP_0_A9.DSP_IMUX19_2 always
DSP_L.DSP_0_A10.DSP_IMUX21_2 always
DSP_L.DSP_0_A11.DSP_IMUX17_2 always
DSP_L.DSP_0_A12.DSP_IMUX47_3 always
@ -34,6 +9,7 @@ DSP_L.DSP_0_A16.DSP_IMUX47_4 always
DSP_L.DSP_0_A17.DSP_IMUX7_4 always
DSP_L.DSP_0_A18.DSP_IMUX46_4 always
DSP_L.DSP_0_A19.DSP_IMUX6_4 always
DSP_L.DSP_0_A1.DSP_IMUX19_0 always
DSP_L.DSP_0_A20.DSP_IMUX47_0 always
DSP_L.DSP_0_A21.DSP_IMUX7_0 always
DSP_L.DSP_0_A22.DSP_IMUX46_0 always
@ -44,9 +20,25 @@ DSP_L.DSP_0_A26.DSP_IMUX46_1 always
DSP_L.DSP_0_A27.DSP_IMUX6_1 always
DSP_L.DSP_0_A28.DSP_IMUX47_2 always
DSP_L.DSP_0_A29.DSP_IMUX7_2 always
DSP_L.DSP_0_A2.DSP_IMUX21_0 always
DSP_L.DSP_0_A3.DSP_IMUX17_0 always
DSP_L.DSP_0_A4.DSP_IMUX23_1 always
DSP_L.DSP_0_A5.DSP_IMUX19_1 always
DSP_L.DSP_0_A6.DSP_IMUX21_1 always
DSP_L.DSP_0_A7.DSP_IMUX17_1 always
DSP_L.DSP_0_A8.DSP_IMUX23_2 always
DSP_L.DSP_0_A9.DSP_IMUX19_2 always
DSP_L.DSP_0_ALUMODE0.DSP_IMUX21_3 always
DSP_L.DSP_0_ALUMODE1.DSP_IMUX13_3 always
DSP_L.DSP_0_B0.DSP_IMUX22_0 always
DSP_L.DSP_0_B10.DSP_IMUX36_2 always
DSP_L.DSP_0_B11.DSP_IMUX16_2 always
DSP_L.DSP_0_B12.DSP_IMUX43_3 always
DSP_L.DSP_0_B13.DSP_IMUX3_3 always
DSP_L.DSP_0_B14.DSP_IMUX42_3 always
DSP_L.DSP_0_B15.DSP_IMUX2_3 always
DSP_L.DSP_0_B16.DSP_IMUX43_4 always
DSP_L.DSP_0_B17.DSP_IMUX3_4 always
DSP_L.DSP_0_B1.DSP_IMUX34_0 always
DSP_L.DSP_0_B2.DSP_IMUX36_0 always
DSP_L.DSP_0_B3.DSP_IMUX40_0 always
@ -56,24 +48,7 @@ DSP_L.DSP_0_B6.DSP_IMUX36_1 always
DSP_L.DSP_0_B7.DSP_IMUX16_1 always
DSP_L.DSP_0_B8.DSP_IMUX22_2 always
DSP_L.DSP_0_B9.DSP_IMUX18_2 always
DSP_L.DSP_0_B10.DSP_IMUX36_2 always
DSP_L.DSP_0_B11.DSP_IMUX16_2 always
DSP_L.DSP_0_B12.DSP_IMUX43_3 always
DSP_L.DSP_0_B13.DSP_IMUX3_3 always
DSP_L.DSP_0_B14.DSP_IMUX42_3 always
DSP_L.DSP_0_B15.DSP_IMUX2_3 always
DSP_L.DSP_0_B16.DSP_IMUX43_4 always
DSP_L.DSP_0_B17.DSP_IMUX3_4 always
DSP_L.DSP_0_C0.DSP_IMUX39_0 always
DSP_L.DSP_0_C1.DSP_IMUX3_0 always
DSP_L.DSP_0_C2.DSP_IMUX37_0 always
DSP_L.DSP_0_C3.DSP_IMUX1_0 always
DSP_L.DSP_0_C4.DSP_IMUX39_1 always
DSP_L.DSP_0_C5.DSP_IMUX35_1 always
DSP_L.DSP_0_C6.DSP_IMUX37_1 always
DSP_L.DSP_0_C7.DSP_IMUX33_1 always
DSP_L.DSP_0_C8.DSP_IMUX39_2 always
DSP_L.DSP_0_C9.DSP_IMUX3_2 always
DSP_L.DSP_0_C10.DSP_IMUX37_2 always
DSP_L.DSP_0_C11.DSP_IMUX33_2 always
DSP_L.DSP_0_C12.DSP_IMUX39_3 always
@ -84,6 +59,7 @@ DSP_L.DSP_0_C16.DSP_IMUX39_4 always
DSP_L.DSP_0_C17.DSP_IMUX35_4 always
DSP_L.DSP_0_C18.DSP_IMUX21_4 always
DSP_L.DSP_0_C19.DSP_IMUX1_4 always
DSP_L.DSP_0_C1.DSP_IMUX3_0 always
DSP_L.DSP_0_C20.DSP_IMUX38_0 always
DSP_L.DSP_0_C21.DSP_IMUX18_0 always
DSP_L.DSP_0_C22.DSP_IMUX20_0 always
@ -94,6 +70,7 @@ DSP_L.DSP_0_C26.DSP_IMUX20_1 always
DSP_L.DSP_0_C27.DSP_IMUX32_1 always
DSP_L.DSP_0_C28.DSP_IMUX6_2 always
DSP_L.DSP_0_C29.DSP_IMUX2_2 always
DSP_L.DSP_0_C2.DSP_IMUX37_0 always
DSP_L.DSP_0_C30.DSP_IMUX4_2 always
DSP_L.DSP_0_C31.DSP_IMUX32_2 always
DSP_L.DSP_0_C32.DSP_IMUX38_3 always
@ -104,6 +81,7 @@ DSP_L.DSP_0_C36.DSP_IMUX38_4 always
DSP_L.DSP_0_C37.DSP_IMUX32_4 always
DSP_L.DSP_0_C38.DSP_IMUX20_4 always
DSP_L.DSP_0_C39.DSP_IMUX18_4 always
DSP_L.DSP_0_C3.DSP_IMUX1_0 always
DSP_L.DSP_0_C40.DSP_IMUX35_0 always
DSP_L.DSP_0_C41.DSP_IMUX16_0 always
DSP_L.DSP_0_C42.DSP_IMUX42_0 always
@ -112,46 +90,41 @@ DSP_L.DSP_0_C44.DSP_IMUX34_4 always
DSP_L.DSP_0_C45.DSP_IMUX37_4 always
DSP_L.DSP_0_C46.DSP_IMUX19_4 always
DSP_L.DSP_0_C47.DSP_IMUX33_4 always
DSP_L.DSP_0_C4.DSP_IMUX39_1 always
DSP_L.DSP_0_C5.DSP_IMUX35_1 always
DSP_L.DSP_0_C6.DSP_IMUX37_1 always
DSP_L.DSP_0_C7.DSP_IMUX33_1 always
DSP_L.DSP_0_C8.DSP_IMUX39_2 always
DSP_L.DSP_0_C9.DSP_IMUX3_2 always
DSP_L.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_L.DSP_0_CARRYINSEL0.DSP_IMUX30_3 always
DSP_L.DSP_0_CARRYINSEL1.DSP_IMUX14_3 always
DSP_L.DSP_0_CEA1.DSP_IMUX40_1 always
DSP_L.DSP_0_CEA2.DSP_IMUX0_1 always
DSP_L.DSP_0_CEB1.DSP_IMUX41_1 always
DSP_L.DSP_0_CEB2.DSP_IMUX1_1 always
DSP_L.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_L.DSP_0_CEC.DSP_IMUX40_2 always
DSP_L.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_L.DSP_0_CEM.DSP_IMUX1_2 always
DSP_L.DSP_0_CEP.DSP_IMUX34_2 always
DSP_L.DSP_0_CLK.DSP_CLK0_1 always
DSP_L.DSP_0_OPMODE0.DSP_IMUX35_2 always
DSP_L.DSP_0_OPMODE1.DSP_IMUX30_2 always
DSP_L.DSP_0_OPMODE2.DSP_IMUX27_2 always
DSP_L.DSP_0_OPMODE3.DSP_IMUX38_2 always
DSP_L.DSP_0_OPMODE4.DSP_IMUX20_2 always
DSP_L.DSP_0_OPMODE5.DSP_IMUX12_2 always
DSP_L.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_L.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_L.DSP_1_CEC.DSP_IMUX34_3 always
DSP_L.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_L.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_L.DSP_1_CEM.DSP_IMUX19_3 always
DSP_L.DSP_1_CEP.DSP_IMUX26_2 always
DSP_L.DSP_1_CLK.DSP_CLK0_3 always
DSP_L.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_L.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_L.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_L.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_L.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_L.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_L.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_L.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_L.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_L.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_L.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_L.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_L.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_L.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_L.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_L.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_L.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_L.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_L.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_L.DSP_1_A0.DSP_IMUX15_0 always
DSP_L.DSP_1_A1.DSP_IMUX11_0 always
DSP_L.DSP_1_A2.DSP_IMUX13_0 always
DSP_L.DSP_1_A3.DSP_IMUX9_0 always
DSP_L.DSP_1_A4.DSP_IMUX15_1 always
DSP_L.DSP_1_A5.DSP_IMUX11_1 always
DSP_L.DSP_1_A6.DSP_IMUX13_1 always
DSP_L.DSP_1_A7.DSP_IMUX9_1 always
DSP_L.DSP_1_A8.DSP_IMUX15_2 always
DSP_L.DSP_1_A9.DSP_IMUX11_2 always
DSP_L.DSP_1_A10.DSP_IMUX13_2 always
DSP_L.DSP_1_A11.DSP_IMUX9_2 always
DSP_L.DSP_1_A12.DSP_IMUX45_3 always
@ -162,6 +135,7 @@ DSP_L.DSP_1_A16.DSP_IMUX45_4 always
DSP_L.DSP_1_A17.DSP_IMUX5_4 always
DSP_L.DSP_1_A18.DSP_IMUX44_4 always
DSP_L.DSP_1_A19.DSP_IMUX4_4 always
DSP_L.DSP_1_A1.DSP_IMUX11_0 always
DSP_L.DSP_1_A20.DSP_IMUX45_0 always
DSP_L.DSP_1_A21.DSP_IMUX5_0 always
DSP_L.DSP_1_A22.DSP_IMUX44_0 always
@ -172,16 +146,15 @@ DSP_L.DSP_1_A26.DSP_IMUX44_1 always
DSP_L.DSP_1_A27.DSP_IMUX4_1 always
DSP_L.DSP_1_A28.DSP_IMUX45_2 always
DSP_L.DSP_1_A29.DSP_IMUX5_2 always
DSP_L.DSP_1_A2.DSP_IMUX13_0 always
DSP_L.DSP_1_A3.DSP_IMUX9_0 always
DSP_L.DSP_1_A4.DSP_IMUX15_1 always
DSP_L.DSP_1_A5.DSP_IMUX11_1 always
DSP_L.DSP_1_A6.DSP_IMUX13_1 always
DSP_L.DSP_1_A7.DSP_IMUX9_1 always
DSP_L.DSP_1_A8.DSP_IMUX15_2 always
DSP_L.DSP_1_A9.DSP_IMUX11_2 always
DSP_L.DSP_1_ACIN0.DSP_0_ACOUT0 always
DSP_L.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_L.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_L.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_L.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_L.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_L.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_L.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_L.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_L.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_L.DSP_1_ACIN10.DSP_0_ACOUT10 always
DSP_L.DSP_1_ACIN11.DSP_0_ACOUT11 always
DSP_L.DSP_1_ACIN12.DSP_0_ACOUT12 always
@ -192,6 +165,7 @@ DSP_L.DSP_1_ACIN16.DSP_0_ACOUT16 always
DSP_L.DSP_1_ACIN17.DSP_0_ACOUT17 always
DSP_L.DSP_1_ACIN18.DSP_0_ACOUT18 always
DSP_L.DSP_1_ACIN19.DSP_0_ACOUT19 always
DSP_L.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_L.DSP_1_ACIN20.DSP_0_ACOUT20 always
DSP_L.DSP_1_ACIN21.DSP_0_ACOUT21 always
DSP_L.DSP_1_ACIN22.DSP_0_ACOUT22 always
@ -202,9 +176,25 @@ DSP_L.DSP_1_ACIN26.DSP_0_ACOUT26 always
DSP_L.DSP_1_ACIN27.DSP_0_ACOUT27 always
DSP_L.DSP_1_ACIN28.DSP_0_ACOUT28 always
DSP_L.DSP_1_ACIN29.DSP_0_ACOUT29 always
DSP_L.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_L.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_L.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_L.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_L.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_L.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_L.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_L.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_L.DSP_1_ALUMODE0.DSP_IMUX0_4 always
DSP_L.DSP_1_ALUMODE1.DSP_IMUX40_4 always
DSP_L.DSP_1_B0.DSP_IMUX14_0 always
DSP_L.DSP_1_B10.DSP_IMUX44_2 always
DSP_L.DSP_1_B11.DSP_IMUX8_2 always
DSP_L.DSP_1_B12.DSP_IMUX41_3 always
DSP_L.DSP_1_B13.DSP_IMUX1_3 always
DSP_L.DSP_1_B14.DSP_IMUX40_3 always
DSP_L.DSP_1_B15.DSP_IMUX0_3 always
DSP_L.DSP_1_B16.DSP_IMUX42_4 always
DSP_L.DSP_1_B17.DSP_IMUX2_4 always
DSP_L.DSP_1_B1.DSP_IMUX26_0 always
DSP_L.DSP_1_B2.DSP_IMUX28_0 always
DSP_L.DSP_1_B3.DSP_IMUX0_0 always
@ -214,15 +204,15 @@ DSP_L.DSP_1_B6.DSP_IMUX28_1 always
DSP_L.DSP_1_B7.DSP_IMUX8_1 always
DSP_L.DSP_1_B8.DSP_IMUX14_2 always
DSP_L.DSP_1_B9.DSP_IMUX42_2 always
DSP_L.DSP_1_B10.DSP_IMUX44_2 always
DSP_L.DSP_1_B11.DSP_IMUX8_2 always
DSP_L.DSP_1_B12.DSP_IMUX41_3 always
DSP_L.DSP_1_B13.DSP_IMUX1_3 always
DSP_L.DSP_1_B14.DSP_IMUX40_3 always
DSP_L.DSP_1_B15.DSP_IMUX0_3 always
DSP_L.DSP_1_B16.DSP_IMUX42_4 always
DSP_L.DSP_1_B17.DSP_IMUX2_4 always
DSP_L.DSP_1_BCIN0.DSP_0_BCOUT0 always
DSP_L.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_L.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_L.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_L.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_L.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_L.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_L.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_L.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_L.DSP_1_BCIN1.DSP_0_BCOUT1 always
DSP_L.DSP_1_BCIN2.DSP_0_BCOUT2 always
DSP_L.DSP_1_BCIN3.DSP_0_BCOUT3 always
@ -232,24 +222,7 @@ DSP_L.DSP_1_BCIN6.DSP_0_BCOUT6 always
DSP_L.DSP_1_BCIN7.DSP_0_BCOUT7 always
DSP_L.DSP_1_BCIN8.DSP_0_BCOUT8 always
DSP_L.DSP_1_BCIN9.DSP_0_BCOUT9 always
DSP_L.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_L.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_L.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_L.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_L.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_L.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_L.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_L.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_L.DSP_1_C0.DSP_IMUX31_0 always
DSP_L.DSP_1_C1.DSP_IMUX43_0 always
DSP_L.DSP_1_C2.DSP_IMUX29_0 always
DSP_L.DSP_1_C3.DSP_IMUX41_0 always
DSP_L.DSP_1_C4.DSP_IMUX31_1 always
DSP_L.DSP_1_C5.DSP_IMUX27_1 always
DSP_L.DSP_1_C6.DSP_IMUX29_1 always
DSP_L.DSP_1_C7.DSP_IMUX25_1 always
DSP_L.DSP_1_C8.DSP_IMUX31_2 always
DSP_L.DSP_1_C9.DSP_IMUX43_2 always
DSP_L.DSP_1_C10.DSP_IMUX29_2 always
DSP_L.DSP_1_C11.DSP_IMUX25_2 always
DSP_L.DSP_1_C12.DSP_IMUX31_3 always
@ -260,6 +233,7 @@ DSP_L.DSP_1_C16.DSP_IMUX31_4 always
DSP_L.DSP_1_C17.DSP_IMUX27_4 always
DSP_L.DSP_1_C18.DSP_IMUX13_4 always
DSP_L.DSP_1_C19.DSP_IMUX41_4 always
DSP_L.DSP_1_C1.DSP_IMUX43_0 always
DSP_L.DSP_1_C20.DSP_IMUX30_0 always
DSP_L.DSP_1_C21.DSP_IMUX10_0 always
DSP_L.DSP_1_C22.DSP_IMUX12_0 always
@ -270,6 +244,7 @@ DSP_L.DSP_1_C26.DSP_IMUX12_1 always
DSP_L.DSP_1_C27.DSP_IMUX24_1 always
DSP_L.DSP_1_C28.DSP_IMUX46_2 always
DSP_L.DSP_1_C29.DSP_IMUX10_2 always
DSP_L.DSP_1_C2.DSP_IMUX29_0 always
DSP_L.DSP_1_C30.DSP_IMUX28_2 always
DSP_L.DSP_1_C31.DSP_IMUX24_2 always
DSP_L.DSP_1_C32.DSP_IMUX22_3 always
@ -280,6 +255,7 @@ DSP_L.DSP_1_C36.DSP_IMUX30_4 always
DSP_L.DSP_1_C37.DSP_IMUX24_4 always
DSP_L.DSP_1_C38.DSP_IMUX12_4 always
DSP_L.DSP_1_C39.DSP_IMUX10_4 always
DSP_L.DSP_1_C3.DSP_IMUX41_0 always
DSP_L.DSP_1_C40.DSP_IMUX27_0 always
DSP_L.DSP_1_C41.DSP_IMUX8_0 always
DSP_L.DSP_1_C42.DSP_IMUX2_0 always
@ -288,12 +264,27 @@ DSP_L.DSP_1_C44.DSP_IMUX26_4 always
DSP_L.DSP_1_C45.DSP_IMUX29_4 always
DSP_L.DSP_1_C46.DSP_IMUX11_4 always
DSP_L.DSP_1_C47.DSP_IMUX25_4 always
DSP_L.DSP_1_C4.DSP_IMUX31_1 always
DSP_L.DSP_1_C5.DSP_IMUX27_1 always
DSP_L.DSP_1_C6.DSP_IMUX29_1 always
DSP_L.DSP_1_C7.DSP_IMUX25_1 always
DSP_L.DSP_1_C8.DSP_IMUX31_2 always
DSP_L.DSP_1_C9.DSP_IMUX43_2 always
DSP_L.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_L.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_L.DSP_1_CARRYINSEL0.DSP_IMUX36_4 always
DSP_L.DSP_1_CARRYINSEL1.DSP_IMUX28_4 always
DSP_L.DSP_1_CEA1.DSP_IMUX9_3 always
DSP_L.DSP_1_CEA2.DSP_IMUX17_3 always
DSP_L.DSP_1_CEB1.DSP_IMUX8_3 always
DSP_L.DSP_1_CEB2.DSP_IMUX16_3 always
DSP_L.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_L.DSP_1_CEC.DSP_IMUX34_3 always
DSP_L.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_L.DSP_1_CEM.DSP_IMUX19_3 always
DSP_L.DSP_1_CEP.DSP_IMUX26_2 always
DSP_L.DSP_1_CLK.DSP_CLK0_3 always
DSP_L.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_L.DSP_1_OPMODE0.DSP_IMUX28_3 always
DSP_L.DSP_1_OPMODE1.DSP_IMUX8_4 always
DSP_L.DSP_1_OPMODE2.DSP_IMUX36_3 always
@ -301,15 +292,6 @@ DSP_L.DSP_1_OPMODE3.DSP_IMUX16_4 always
DSP_L.DSP_1_OPMODE4.DSP_IMUX17_4 always
DSP_L.DSP_1_OPMODE5.DSP_IMUX9_4 always
DSP_L.DSP_1_PCIN0.DSP_0_PCOUT0 always
DSP_L.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_L.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_L.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_L.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_L.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_L.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_L.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_L.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_L.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_L.DSP_1_PCIN10.DSP_0_PCOUT10 always
DSP_L.DSP_1_PCIN11.DSP_0_PCOUT11 always
DSP_L.DSP_1_PCIN12.DSP_0_PCOUT12 always
@ -320,6 +302,7 @@ DSP_L.DSP_1_PCIN16.DSP_0_PCOUT16 always
DSP_L.DSP_1_PCIN17.DSP_0_PCOUT17 always
DSP_L.DSP_1_PCIN18.DSP_0_PCOUT18 always
DSP_L.DSP_1_PCIN19.DSP_0_PCOUT19 always
DSP_L.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_L.DSP_1_PCIN20.DSP_0_PCOUT20 always
DSP_L.DSP_1_PCIN21.DSP_0_PCOUT21 always
DSP_L.DSP_1_PCIN22.DSP_0_PCOUT22 always
@ -330,6 +313,7 @@ DSP_L.DSP_1_PCIN26.DSP_0_PCOUT26 always
DSP_L.DSP_1_PCIN27.DSP_0_PCOUT27 always
DSP_L.DSP_1_PCIN28.DSP_0_PCOUT28 always
DSP_L.DSP_1_PCIN29.DSP_0_PCOUT29 always
DSP_L.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_L.DSP_1_PCIN30.DSP_0_PCOUT30 always
DSP_L.DSP_1_PCIN31.DSP_0_PCOUT31 always
DSP_L.DSP_1_PCIN32.DSP_0_PCOUT32 always
@ -340,6 +324,7 @@ DSP_L.DSP_1_PCIN36.DSP_0_PCOUT36 always
DSP_L.DSP_1_PCIN37.DSP_0_PCOUT37 always
DSP_L.DSP_1_PCIN38.DSP_0_PCOUT38 always
DSP_L.DSP_1_PCIN39.DSP_0_PCOUT39 always
DSP_L.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_L.DSP_1_PCIN40.DSP_0_PCOUT40 always
DSP_L.DSP_1_PCIN41.DSP_0_PCOUT41 always
DSP_L.DSP_1_PCIN42.DSP_0_PCOUT42 always
@ -348,20 +333,148 @@ DSP_L.DSP_1_PCIN44.DSP_0_PCOUT44 always
DSP_L.DSP_1_PCIN45.DSP_0_PCOUT45 always
DSP_L.DSP_1_PCIN46.DSP_0_PCOUT46 always
DSP_L.DSP_1_PCIN47.DSP_0_PCOUT47 always
DSP_L.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_L.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_L.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_L.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_L.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_L.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_L.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_L.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_L.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_L.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_L.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_L.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_L.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_L.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_L.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_L.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_L.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_L.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_L.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_L.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_L.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_L.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_L.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_L.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_L.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_L.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_L.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_L.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_L.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_L.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_L.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_L.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_L.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_L.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_L.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_L.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_L.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_L.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_L.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_L.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_L.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_L.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_L.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_L.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_L.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_L.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_L.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_L.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_L.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_L.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_L.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_L.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_L.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_L.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_L.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_L.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_L.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_L.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_L.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_L.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_L.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_L.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_L.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_L.DSP_CARRYCASCOUT.DSP_1_CARRYCASCOUT always
DSP_L.DSP_LOGIC_OUTS_B0_0.DSP_1_P23 always
DSP_L.DSP_LOGIC_OUTS_B0_1.DSP_1_P27 always
DSP_L.DSP_LOGIC_OUTS_B0_2.DSP_1_P31 always
DSP_L.DSP_LOGIC_OUTS_B0_3.DSP_1_P35 always
DSP_L.DSP_LOGIC_OUTS_B0_4.DSP_1_P37 always
DSP_L.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_L.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_L.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_L.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_L.DSP_LOGIC_OUTS_B1_0.DSP_1_P1 always
DSP_L.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_L.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_L.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_L.DSP_LOGIC_OUTS_B1_1.DSP_1_P5 always
DSP_L.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_L.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_L.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_L.DSP_LOGIC_OUTS_B1_2.DSP_1_P9 always
DSP_L.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_L.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_L.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_L.DSP_LOGIC_OUTS_B1_3.DSP_1_P13 always
DSP_L.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_L.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_L.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_L.DSP_LOGIC_OUTS_B1_4.DSP_1_P17 always
DSP_L.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_L.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_L.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_L.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_L.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_L.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_L.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_L.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_L.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_L.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_L.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_L.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_L.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_L.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_L.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_L.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_L.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_L.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_L.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_L.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_L.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_L.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_L.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_L.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_L.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_L.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_L.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_L.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_L.DSP_LOGIC_OUTS_B2_0.DSP_1_P22 always
DSP_L.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_L.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_L.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_L.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_L.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_L.DSP_LOGIC_OUTS_B2_1.DSP_1_P26 always
DSP_L.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_L.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_L.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_L.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_L.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_L.DSP_LOGIC_OUTS_B2_2.DSP_1_P30 always
DSP_L.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_L.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_L.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_L.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_L.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_L.DSP_LOGIC_OUTS_B2_3.DSP_1_P34 always
DSP_L.DSP_LOGIC_OUTS_B2_4.DSP_1_P38 always
DSP_L.DSP_LOGIC_OUTS_B3_0.DSP_1_P0 always
@ -396,130 +509,8 @@ DSP_L.DSP_LOGIC_OUTS_B8_4.DSP_0_P47 always
DSP_L.DSP_LOGIC_OUTS_B9_0.DSP_0_P42 always
DSP_L.DSP_LOGIC_OUTS_B9_2.DSP_0_UNDERFLOW always
DSP_L.DSP_LOGIC_OUTS_B9_4.DSP_0_P44 always
DSP_L.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_L.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_L.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_L.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_L.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_L.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_L.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_L.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_L.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_L.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_L.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_L.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_L.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_L.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_L.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_L.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_L.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_L.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_L.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_L.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_L.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_L.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_L.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_L.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_L.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_L.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_L.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_L.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_L.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_L.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_L.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_L.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_L.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_L.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_L.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_L.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_L.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_L.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_L.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_L.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_L.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_L.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_L.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_L.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_L.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_L.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_L.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_L.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_L.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_L.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_L.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_L.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_L.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_L.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_L.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_L.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_L.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_L.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_L.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_L.DSP_MULTSIGNOUT.DSP_1_MULTSIGNOUT always
DSP_L.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_L.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_L.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_L.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_L.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_L.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_L.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_L.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_L.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_L.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_L.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_L.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_L.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_L.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_L.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_L.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_L.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_L.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_L.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_L.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_L.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_L.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_L.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_L.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_L.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_L.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_L.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_L.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_L.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_L.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_L.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_L.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_L.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_L.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_L.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_L.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_L.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_L.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_L.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_L.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_L.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_L.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_L.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_L.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_L.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_L.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_L.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_L.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_L.DSP_PCOUT0.DSP_1_PCOUT0 always
DSP_L.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_L.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_L.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_L.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_L.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_L.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_L.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_L.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_L.DSP_PCOUT9.DSP_1_PCOUT9 always
DSP_L.DSP_PCOUT10.DSP_1_PCOUT10 always
DSP_L.DSP_PCOUT11.DSP_1_PCOUT11 always
DSP_L.DSP_PCOUT12.DSP_1_PCOUT12 always
@ -530,6 +521,7 @@ DSP_L.DSP_PCOUT16.DSP_1_PCOUT16 always
DSP_L.DSP_PCOUT17.DSP_1_PCOUT17 always
DSP_L.DSP_PCOUT18.DSP_1_PCOUT18 always
DSP_L.DSP_PCOUT19.DSP_1_PCOUT19 always
DSP_L.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_L.DSP_PCOUT20.DSP_1_PCOUT20 always
DSP_L.DSP_PCOUT21.DSP_1_PCOUT21 always
DSP_L.DSP_PCOUT22.DSP_1_PCOUT22 always
@ -540,6 +532,7 @@ DSP_L.DSP_PCOUT26.DSP_1_PCOUT26 always
DSP_L.DSP_PCOUT27.DSP_1_PCOUT27 always
DSP_L.DSP_PCOUT28.DSP_1_PCOUT28 always
DSP_L.DSP_PCOUT29.DSP_1_PCOUT29 always
DSP_L.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_L.DSP_PCOUT30.DSP_1_PCOUT30 always
DSP_L.DSP_PCOUT31.DSP_1_PCOUT31 always
DSP_L.DSP_PCOUT32.DSP_1_PCOUT32 always
@ -550,6 +543,7 @@ DSP_L.DSP_PCOUT36.DSP_1_PCOUT36 always
DSP_L.DSP_PCOUT37.DSP_1_PCOUT37 always
DSP_L.DSP_PCOUT38.DSP_1_PCOUT38 always
DSP_L.DSP_PCOUT39.DSP_1_PCOUT39 always
DSP_L.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_L.DSP_PCOUT40.DSP_1_PCOUT40 always
DSP_L.DSP_PCOUT41.DSP_1_PCOUT41 always
DSP_L.DSP_PCOUT42.DSP_1_PCOUT42 always
@ -558,3 +552,9 @@ DSP_L.DSP_PCOUT44.DSP_1_PCOUT44 always
DSP_L.DSP_PCOUT45.DSP_1_PCOUT45 always
DSP_L.DSP_PCOUT46.DSP_1_PCOUT46 always
DSP_L.DSP_PCOUT47.DSP_1_PCOUT47 always
DSP_L.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_L.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_L.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_L.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_L.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_L.DSP_PCOUT9.DSP_1_PCOUT9 always

468
kintex7/ppips_dsp_r.db
View File

@ -1,29 +1,4 @@
DSP_R.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_R.DSP_0_CEC.DSP_IMUX40_2 always
DSP_R.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_R.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_R.DSP_0_CEM.DSP_IMUX1_2 always
DSP_R.DSP_0_CEP.DSP_IMUX34_2 always
DSP_R.DSP_0_CLK.DSP_CLK0_1 always
DSP_R.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_R.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_R.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_R.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_R.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_R.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_R.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_R.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_R.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_R.DSP_0_A0.DSP_IMUX23_0 always
DSP_R.DSP_0_A1.DSP_IMUX19_0 always
DSP_R.DSP_0_A2.DSP_IMUX21_0 always
DSP_R.DSP_0_A3.DSP_IMUX17_0 always
DSP_R.DSP_0_A4.DSP_IMUX23_1 always
DSP_R.DSP_0_A5.DSP_IMUX19_1 always
DSP_R.DSP_0_A6.DSP_IMUX21_1 always
DSP_R.DSP_0_A7.DSP_IMUX17_1 always
DSP_R.DSP_0_A8.DSP_IMUX23_2 always
DSP_R.DSP_0_A9.DSP_IMUX19_2 always
DSP_R.DSP_0_A10.DSP_IMUX21_2 always
DSP_R.DSP_0_A11.DSP_IMUX17_2 always
DSP_R.DSP_0_A12.DSP_IMUX47_3 always
@ -34,6 +9,7 @@ DSP_R.DSP_0_A16.DSP_IMUX47_4 always
DSP_R.DSP_0_A17.DSP_IMUX7_4 always
DSP_R.DSP_0_A18.DSP_IMUX46_4 always
DSP_R.DSP_0_A19.DSP_IMUX6_4 always
DSP_R.DSP_0_A1.DSP_IMUX19_0 always
DSP_R.DSP_0_A20.DSP_IMUX47_0 always
DSP_R.DSP_0_A21.DSP_IMUX7_0 always
DSP_R.DSP_0_A22.DSP_IMUX46_0 always
@ -44,9 +20,25 @@ DSP_R.DSP_0_A26.DSP_IMUX46_1 always
DSP_R.DSP_0_A27.DSP_IMUX6_1 always
DSP_R.DSP_0_A28.DSP_IMUX47_2 always
DSP_R.DSP_0_A29.DSP_IMUX7_2 always
DSP_R.DSP_0_A2.DSP_IMUX21_0 always
DSP_R.DSP_0_A3.DSP_IMUX17_0 always
DSP_R.DSP_0_A4.DSP_IMUX23_1 always
DSP_R.DSP_0_A5.DSP_IMUX19_1 always
DSP_R.DSP_0_A6.DSP_IMUX21_1 always
DSP_R.DSP_0_A7.DSP_IMUX17_1 always
DSP_R.DSP_0_A8.DSP_IMUX23_2 always
DSP_R.DSP_0_A9.DSP_IMUX19_2 always
DSP_R.DSP_0_ALUMODE0.DSP_IMUX21_3 always
DSP_R.DSP_0_ALUMODE1.DSP_IMUX13_3 always
DSP_R.DSP_0_B0.DSP_IMUX22_0 always
DSP_R.DSP_0_B10.DSP_IMUX36_2 always
DSP_R.DSP_0_B11.DSP_IMUX16_2 always
DSP_R.DSP_0_B12.DSP_IMUX43_3 always
DSP_R.DSP_0_B13.DSP_IMUX3_3 always
DSP_R.DSP_0_B14.DSP_IMUX42_3 always
DSP_R.DSP_0_B15.DSP_IMUX2_3 always
DSP_R.DSP_0_B16.DSP_IMUX43_4 always
DSP_R.DSP_0_B17.DSP_IMUX3_4 always
DSP_R.DSP_0_B1.DSP_IMUX34_0 always
DSP_R.DSP_0_B2.DSP_IMUX36_0 always
DSP_R.DSP_0_B3.DSP_IMUX40_0 always
@ -56,24 +48,7 @@ DSP_R.DSP_0_B6.DSP_IMUX36_1 always
DSP_R.DSP_0_B7.DSP_IMUX16_1 always
DSP_R.DSP_0_B8.DSP_IMUX22_2 always
DSP_R.DSP_0_B9.DSP_IMUX18_2 always
DSP_R.DSP_0_B10.DSP_IMUX36_2 always
DSP_R.DSP_0_B11.DSP_IMUX16_2 always
DSP_R.DSP_0_B12.DSP_IMUX43_3 always
DSP_R.DSP_0_B13.DSP_IMUX3_3 always
DSP_R.DSP_0_B14.DSP_IMUX42_3 always
DSP_R.DSP_0_B15.DSP_IMUX2_3 always
DSP_R.DSP_0_B16.DSP_IMUX43_4 always
DSP_R.DSP_0_B17.DSP_IMUX3_4 always
DSP_R.DSP_0_C0.DSP_IMUX39_0 always
DSP_R.DSP_0_C1.DSP_IMUX3_0 always
DSP_R.DSP_0_C2.DSP_IMUX37_0 always
DSP_R.DSP_0_C3.DSP_IMUX1_0 always
DSP_R.DSP_0_C4.DSP_IMUX39_1 always
DSP_R.DSP_0_C5.DSP_IMUX35_1 always
DSP_R.DSP_0_C6.DSP_IMUX37_1 always
DSP_R.DSP_0_C7.DSP_IMUX33_1 always
DSP_R.DSP_0_C8.DSP_IMUX39_2 always
DSP_R.DSP_0_C9.DSP_IMUX3_2 always
DSP_R.DSP_0_C10.DSP_IMUX37_2 always
DSP_R.DSP_0_C11.DSP_IMUX33_2 always
DSP_R.DSP_0_C12.DSP_IMUX39_3 always
@ -84,6 +59,7 @@ DSP_R.DSP_0_C16.DSP_IMUX39_4 always
DSP_R.DSP_0_C17.DSP_IMUX35_4 always
DSP_R.DSP_0_C18.DSP_IMUX21_4 always
DSP_R.DSP_0_C19.DSP_IMUX1_4 always
DSP_R.DSP_0_C1.DSP_IMUX3_0 always
DSP_R.DSP_0_C20.DSP_IMUX38_0 always
DSP_R.DSP_0_C21.DSP_IMUX18_0 always
DSP_R.DSP_0_C22.DSP_IMUX20_0 always
@ -94,6 +70,7 @@ DSP_R.DSP_0_C26.DSP_IMUX20_1 always
DSP_R.DSP_0_C27.DSP_IMUX32_1 always
DSP_R.DSP_0_C28.DSP_IMUX6_2 always
DSP_R.DSP_0_C29.DSP_IMUX2_2 always
DSP_R.DSP_0_C2.DSP_IMUX37_0 always
DSP_R.DSP_0_C30.DSP_IMUX4_2 always
DSP_R.DSP_0_C31.DSP_IMUX32_2 always
DSP_R.DSP_0_C32.DSP_IMUX38_3 always
@ -104,6 +81,7 @@ DSP_R.DSP_0_C36.DSP_IMUX38_4 always
DSP_R.DSP_0_C37.DSP_IMUX32_4 always
DSP_R.DSP_0_C38.DSP_IMUX20_4 always
DSP_R.DSP_0_C39.DSP_IMUX18_4 always
DSP_R.DSP_0_C3.DSP_IMUX1_0 always
DSP_R.DSP_0_C40.DSP_IMUX35_0 always
DSP_R.DSP_0_C41.DSP_IMUX16_0 always
DSP_R.DSP_0_C42.DSP_IMUX42_0 always
@ -112,46 +90,41 @@ DSP_R.DSP_0_C44.DSP_IMUX34_4 always
DSP_R.DSP_0_C45.DSP_IMUX37_4 always
DSP_R.DSP_0_C46.DSP_IMUX19_4 always
DSP_R.DSP_0_C47.DSP_IMUX33_4 always
DSP_R.DSP_0_C4.DSP_IMUX39_1 always
DSP_R.DSP_0_C5.DSP_IMUX35_1 always
DSP_R.DSP_0_C6.DSP_IMUX37_1 always
DSP_R.DSP_0_C7.DSP_IMUX33_1 always
DSP_R.DSP_0_C8.DSP_IMUX39_2 always
DSP_R.DSP_0_C9.DSP_IMUX3_2 always
DSP_R.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_R.DSP_0_CARRYINSEL0.DSP_IMUX30_3 always
DSP_R.DSP_0_CARRYINSEL1.DSP_IMUX14_3 always
DSP_R.DSP_0_CEA1.DSP_IMUX40_1 always
DSP_R.DSP_0_CEA2.DSP_IMUX0_1 always
DSP_R.DSP_0_CEB1.DSP_IMUX41_1 always
DSP_R.DSP_0_CEB2.DSP_IMUX1_1 always
DSP_R.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_R.DSP_0_CEC.DSP_IMUX40_2 always
DSP_R.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_R.DSP_0_CEM.DSP_IMUX1_2 always
DSP_R.DSP_0_CEP.DSP_IMUX34_2 always
DSP_R.DSP_0_CLK.DSP_CLK0_1 always
DSP_R.DSP_0_OPMODE0.DSP_IMUX35_2 always
DSP_R.DSP_0_OPMODE1.DSP_IMUX30_2 always
DSP_R.DSP_0_OPMODE2.DSP_IMUX27_2 always
DSP_R.DSP_0_OPMODE3.DSP_IMUX38_2 always
DSP_R.DSP_0_OPMODE4.DSP_IMUX20_2 always
DSP_R.DSP_0_OPMODE5.DSP_IMUX12_2 always
DSP_R.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_R.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_R.DSP_1_CEC.DSP_IMUX34_3 always
DSP_R.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_R.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_R.DSP_1_CEM.DSP_IMUX19_3 always
DSP_R.DSP_1_CEP.DSP_IMUX26_2 always
DSP_R.DSP_1_CLK.DSP_CLK0_3 always
DSP_R.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_R.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_R.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_R.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_R.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_R.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_R.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_R.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_R.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_R.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_R.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_R.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_R.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_R.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_R.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_R.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_R.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_R.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_R.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_R.DSP_1_A0.DSP_IMUX15_0 always
DSP_R.DSP_1_A1.DSP_IMUX11_0 always
DSP_R.DSP_1_A2.DSP_IMUX13_0 always
DSP_R.DSP_1_A3.DSP_IMUX9_0 always
DSP_R.DSP_1_A4.DSP_IMUX15_1 always
DSP_R.DSP_1_A5.DSP_IMUX11_1 always
DSP_R.DSP_1_A6.DSP_IMUX13_1 always
DSP_R.DSP_1_A7.DSP_IMUX9_1 always
DSP_R.DSP_1_A8.DSP_IMUX15_2 always
DSP_R.DSP_1_A9.DSP_IMUX11_2 always
DSP_R.DSP_1_A10.DSP_IMUX13_2 always
DSP_R.DSP_1_A11.DSP_IMUX9_2 always
DSP_R.DSP_1_A12.DSP_IMUX45_3 always
@ -162,6 +135,7 @@ DSP_R.DSP_1_A16.DSP_IMUX45_4 always
DSP_R.DSP_1_A17.DSP_IMUX5_4 always
DSP_R.DSP_1_A18.DSP_IMUX44_4 always
DSP_R.DSP_1_A19.DSP_IMUX4_4 always
DSP_R.DSP_1_A1.DSP_IMUX11_0 always
DSP_R.DSP_1_A20.DSP_IMUX45_0 always
DSP_R.DSP_1_A21.DSP_IMUX5_0 always
DSP_R.DSP_1_A22.DSP_IMUX44_0 always
@ -172,16 +146,15 @@ DSP_R.DSP_1_A26.DSP_IMUX44_1 always
DSP_R.DSP_1_A27.DSP_IMUX4_1 always
DSP_R.DSP_1_A28.DSP_IMUX45_2 always
DSP_R.DSP_1_A29.DSP_IMUX5_2 always
DSP_R.DSP_1_A2.DSP_IMUX13_0 always
DSP_R.DSP_1_A3.DSP_IMUX9_0 always
DSP_R.DSP_1_A4.DSP_IMUX15_1 always
DSP_R.DSP_1_A5.DSP_IMUX11_1 always
DSP_R.DSP_1_A6.DSP_IMUX13_1 always
DSP_R.DSP_1_A7.DSP_IMUX9_1 always
DSP_R.DSP_1_A8.DSP_IMUX15_2 always
DSP_R.DSP_1_A9.DSP_IMUX11_2 always
DSP_R.DSP_1_ACIN0.DSP_0_ACOUT0 always
DSP_R.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_R.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_R.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_R.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_R.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_R.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_R.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_R.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_R.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_R.DSP_1_ACIN10.DSP_0_ACOUT10 always
DSP_R.DSP_1_ACIN11.DSP_0_ACOUT11 always
DSP_R.DSP_1_ACIN12.DSP_0_ACOUT12 always
@ -192,6 +165,7 @@ DSP_R.DSP_1_ACIN16.DSP_0_ACOUT16 always
DSP_R.DSP_1_ACIN17.DSP_0_ACOUT17 always
DSP_R.DSP_1_ACIN18.DSP_0_ACOUT18 always
DSP_R.DSP_1_ACIN19.DSP_0_ACOUT19 always
DSP_R.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_R.DSP_1_ACIN20.DSP_0_ACOUT20 always
DSP_R.DSP_1_ACIN21.DSP_0_ACOUT21 always
DSP_R.DSP_1_ACIN22.DSP_0_ACOUT22 always
@ -202,9 +176,25 @@ DSP_R.DSP_1_ACIN26.DSP_0_ACOUT26 always
DSP_R.DSP_1_ACIN27.DSP_0_ACOUT27 always
DSP_R.DSP_1_ACIN28.DSP_0_ACOUT28 always
DSP_R.DSP_1_ACIN29.DSP_0_ACOUT29 always
DSP_R.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_R.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_R.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_R.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_R.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_R.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_R.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_R.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_R.DSP_1_ALUMODE0.DSP_IMUX0_4 always
DSP_R.DSP_1_ALUMODE1.DSP_IMUX40_4 always
DSP_R.DSP_1_B0.DSP_IMUX14_0 always
DSP_R.DSP_1_B10.DSP_IMUX44_2 always
DSP_R.DSP_1_B11.DSP_IMUX8_2 always
DSP_R.DSP_1_B12.DSP_IMUX41_3 always
DSP_R.DSP_1_B13.DSP_IMUX1_3 always
DSP_R.DSP_1_B14.DSP_IMUX40_3 always
DSP_R.DSP_1_B15.DSP_IMUX0_3 always
DSP_R.DSP_1_B16.DSP_IMUX42_4 always
DSP_R.DSP_1_B17.DSP_IMUX2_4 always
DSP_R.DSP_1_B1.DSP_IMUX26_0 always
DSP_R.DSP_1_B2.DSP_IMUX28_0 always
DSP_R.DSP_1_B3.DSP_IMUX0_0 always
@ -214,15 +204,15 @@ DSP_R.DSP_1_B6.DSP_IMUX28_1 always
DSP_R.DSP_1_B7.DSP_IMUX8_1 always
DSP_R.DSP_1_B8.DSP_IMUX14_2 always
DSP_R.DSP_1_B9.DSP_IMUX42_2 always
DSP_R.DSP_1_B10.DSP_IMUX44_2 always
DSP_R.DSP_1_B11.DSP_IMUX8_2 always
DSP_R.DSP_1_B12.DSP_IMUX41_3 always
DSP_R.DSP_1_B13.DSP_IMUX1_3 always
DSP_R.DSP_1_B14.DSP_IMUX40_3 always
DSP_R.DSP_1_B15.DSP_IMUX0_3 always
DSP_R.DSP_1_B16.DSP_IMUX42_4 always
DSP_R.DSP_1_B17.DSP_IMUX2_4 always
DSP_R.DSP_1_BCIN0.DSP_0_BCOUT0 always
DSP_R.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_R.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_R.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_R.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_R.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_R.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_R.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_R.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_R.DSP_1_BCIN1.DSP_0_BCOUT1 always
DSP_R.DSP_1_BCIN2.DSP_0_BCOUT2 always
DSP_R.DSP_1_BCIN3.DSP_0_BCOUT3 always
@ -232,24 +222,7 @@ DSP_R.DSP_1_BCIN6.DSP_0_BCOUT6 always
DSP_R.DSP_1_BCIN7.DSP_0_BCOUT7 always
DSP_R.DSP_1_BCIN8.DSP_0_BCOUT8 always
DSP_R.DSP_1_BCIN9.DSP_0_BCOUT9 always
DSP_R.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_R.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_R.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_R.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_R.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_R.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_R.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_R.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_R.DSP_1_C0.DSP_IMUX31_0 always
DSP_R.DSP_1_C1.DSP_IMUX43_0 always
DSP_R.DSP_1_C2.DSP_IMUX29_0 always
DSP_R.DSP_1_C3.DSP_IMUX41_0 always
DSP_R.DSP_1_C4.DSP_IMUX31_1 always
DSP_R.DSP_1_C5.DSP_IMUX27_1 always
DSP_R.DSP_1_C6.DSP_IMUX29_1 always
DSP_R.DSP_1_C7.DSP_IMUX25_1 always
DSP_R.DSP_1_C8.DSP_IMUX31_2 always
DSP_R.DSP_1_C9.DSP_IMUX43_2 always
DSP_R.DSP_1_C10.DSP_IMUX29_2 always
DSP_R.DSP_1_C11.DSP_IMUX25_2 always
DSP_R.DSP_1_C12.DSP_IMUX31_3 always
@ -260,6 +233,7 @@ DSP_R.DSP_1_C16.DSP_IMUX31_4 always
DSP_R.DSP_1_C17.DSP_IMUX27_4 always
DSP_R.DSP_1_C18.DSP_IMUX13_4 always
DSP_R.DSP_1_C19.DSP_IMUX41_4 always
DSP_R.DSP_1_C1.DSP_IMUX43_0 always
DSP_R.DSP_1_C20.DSP_IMUX30_0 always
DSP_R.DSP_1_C21.DSP_IMUX10_0 always
DSP_R.DSP_1_C22.DSP_IMUX12_0 always
@ -270,6 +244,7 @@ DSP_R.DSP_1_C26.DSP_IMUX12_1 always
DSP_R.DSP_1_C27.DSP_IMUX24_1 always
DSP_R.DSP_1_C28.DSP_IMUX46_2 always
DSP_R.DSP_1_C29.DSP_IMUX10_2 always
DSP_R.DSP_1_C2.DSP_IMUX29_0 always
DSP_R.DSP_1_C30.DSP_IMUX28_2 always
DSP_R.DSP_1_C31.DSP_IMUX24_2 always
DSP_R.DSP_1_C32.DSP_IMUX22_3 always
@ -280,6 +255,7 @@ DSP_R.DSP_1_C36.DSP_IMUX30_4 always
DSP_R.DSP_1_C37.DSP_IMUX24_4 always
DSP_R.DSP_1_C38.DSP_IMUX12_4 always
DSP_R.DSP_1_C39.DSP_IMUX10_4 always
DSP_R.DSP_1_C3.DSP_IMUX41_0 always
DSP_R.DSP_1_C40.DSP_IMUX27_0 always
DSP_R.DSP_1_C41.DSP_IMUX8_0 always
DSP_R.DSP_1_C42.DSP_IMUX2_0 always
@ -288,12 +264,27 @@ DSP_R.DSP_1_C44.DSP_IMUX26_4 always
DSP_R.DSP_1_C45.DSP_IMUX29_4 always
DSP_R.DSP_1_C46.DSP_IMUX11_4 always
DSP_R.DSP_1_C47.DSP_IMUX25_4 always
DSP_R.DSP_1_C4.DSP_IMUX31_1 always
DSP_R.DSP_1_C5.DSP_IMUX27_1 always
DSP_R.DSP_1_C6.DSP_IMUX29_1 always
DSP_R.DSP_1_C7.DSP_IMUX25_1 always
DSP_R.DSP_1_C8.DSP_IMUX31_2 always
DSP_R.DSP_1_C9.DSP_IMUX43_2 always
DSP_R.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_R.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_R.DSP_1_CARRYINSEL0.DSP_IMUX36_4 always
DSP_R.DSP_1_CARRYINSEL1.DSP_IMUX28_4 always
DSP_R.DSP_1_CEA1.DSP_IMUX9_3 always
DSP_R.DSP_1_CEA2.DSP_IMUX17_3 always
DSP_R.DSP_1_CEB1.DSP_IMUX8_3 always
DSP_R.DSP_1_CEB2.DSP_IMUX16_3 always
DSP_R.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_R.DSP_1_CEC.DSP_IMUX34_3 always
DSP_R.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_R.DSP_1_CEM.DSP_IMUX19_3 always
DSP_R.DSP_1_CEP.DSP_IMUX26_2 always
DSP_R.DSP_1_CLK.DSP_CLK0_3 always
DSP_R.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_R.DSP_1_OPMODE0.DSP_IMUX28_3 always
DSP_R.DSP_1_OPMODE1.DSP_IMUX8_4 always
DSP_R.DSP_1_OPMODE2.DSP_IMUX36_3 always
@ -301,15 +292,6 @@ DSP_R.DSP_1_OPMODE3.DSP_IMUX16_4 always
DSP_R.DSP_1_OPMODE4.DSP_IMUX17_4 always
DSP_R.DSP_1_OPMODE5.DSP_IMUX9_4 always
DSP_R.DSP_1_PCIN0.DSP_0_PCOUT0 always
DSP_R.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_R.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_R.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_R.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_R.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_R.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_R.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_R.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_R.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_R.DSP_1_PCIN10.DSP_0_PCOUT10 always
DSP_R.DSP_1_PCIN11.DSP_0_PCOUT11 always
DSP_R.DSP_1_PCIN12.DSP_0_PCOUT12 always
@ -320,6 +302,7 @@ DSP_R.DSP_1_PCIN16.DSP_0_PCOUT16 always
DSP_R.DSP_1_PCIN17.DSP_0_PCOUT17 always
DSP_R.DSP_1_PCIN18.DSP_0_PCOUT18 always
DSP_R.DSP_1_PCIN19.DSP_0_PCOUT19 always
DSP_R.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_R.DSP_1_PCIN20.DSP_0_PCOUT20 always
DSP_R.DSP_1_PCIN21.DSP_0_PCOUT21 always
DSP_R.DSP_1_PCIN22.DSP_0_PCOUT22 always
@ -330,6 +313,7 @@ DSP_R.DSP_1_PCIN26.DSP_0_PCOUT26 always
DSP_R.DSP_1_PCIN27.DSP_0_PCOUT27 always
DSP_R.DSP_1_PCIN28.DSP_0_PCOUT28 always
DSP_R.DSP_1_PCIN29.DSP_0_PCOUT29 always
DSP_R.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_R.DSP_1_PCIN30.DSP_0_PCOUT30 always
DSP_R.DSP_1_PCIN31.DSP_0_PCOUT31 always
DSP_R.DSP_1_PCIN32.DSP_0_PCOUT32 always
@ -340,6 +324,7 @@ DSP_R.DSP_1_PCIN36.DSP_0_PCOUT36 always
DSP_R.DSP_1_PCIN37.DSP_0_PCOUT37 always
DSP_R.DSP_1_PCIN38.DSP_0_PCOUT38 always
DSP_R.DSP_1_PCIN39.DSP_0_PCOUT39 always
DSP_R.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_R.DSP_1_PCIN40.DSP_0_PCOUT40 always
DSP_R.DSP_1_PCIN41.DSP_0_PCOUT41 always
DSP_R.DSP_1_PCIN42.DSP_0_PCOUT42 always
@ -348,20 +333,148 @@ DSP_R.DSP_1_PCIN44.DSP_0_PCOUT44 always
DSP_R.DSP_1_PCIN45.DSP_0_PCOUT45 always
DSP_R.DSP_1_PCIN46.DSP_0_PCOUT46 always
DSP_R.DSP_1_PCIN47.DSP_0_PCOUT47 always
DSP_R.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_R.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_R.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_R.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_R.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_R.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_R.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_R.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_R.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_R.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_R.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_R.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_R.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_R.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_R.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_R.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_R.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_R.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_R.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_R.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_R.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_R.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_R.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_R.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_R.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_R.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_R.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_R.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_R.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_R.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_R.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_R.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_R.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_R.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_R.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_R.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_R.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_R.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_R.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_R.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_R.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_R.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_R.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_R.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_R.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_R.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_R.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_R.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_R.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_R.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_R.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_R.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_R.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_R.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_R.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_R.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_R.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_R.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_R.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_R.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_R.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_R.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_R.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_R.DSP_CARRYCASCOUT.DSP_1_CARRYCASCOUT always
DSP_R.DSP_LOGIC_OUTS_B0_0.DSP_1_P23 always
DSP_R.DSP_LOGIC_OUTS_B0_1.DSP_1_P27 always
DSP_R.DSP_LOGIC_OUTS_B0_2.DSP_1_P31 always
DSP_R.DSP_LOGIC_OUTS_B0_3.DSP_1_P35 always
DSP_R.DSP_LOGIC_OUTS_B0_4.DSP_1_P37 always
DSP_R.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_R.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_R.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_R.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_R.DSP_LOGIC_OUTS_B1_0.DSP_1_P1 always
DSP_R.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_R.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_R.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_R.DSP_LOGIC_OUTS_B1_1.DSP_1_P5 always
DSP_R.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_R.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_R.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_R.DSP_LOGIC_OUTS_B1_2.DSP_1_P9 always
DSP_R.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_R.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_R.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_R.DSP_LOGIC_OUTS_B1_3.DSP_1_P13 always
DSP_R.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_R.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_R.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_R.DSP_LOGIC_OUTS_B1_4.DSP_1_P17 always
DSP_R.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_R.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_R.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_R.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_R.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_R.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_R.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_R.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_R.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_R.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_R.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_R.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_R.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_R.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_R.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_R.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_R.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_R.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_R.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_R.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_R.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_R.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_R.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_R.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_R.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_R.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_R.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_R.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_R.DSP_LOGIC_OUTS_B2_0.DSP_1_P22 always
DSP_R.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_R.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_R.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_R.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_R.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_R.DSP_LOGIC_OUTS_B2_1.DSP_1_P26 always
DSP_R.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_R.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_R.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_R.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_R.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_R.DSP_LOGIC_OUTS_B2_2.DSP_1_P30 always
DSP_R.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_R.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_R.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_R.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_R.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_R.DSP_LOGIC_OUTS_B2_3.DSP_1_P34 always
DSP_R.DSP_LOGIC_OUTS_B2_4.DSP_1_P38 always
DSP_R.DSP_LOGIC_OUTS_B3_0.DSP_1_P0 always
@ -396,130 +509,8 @@ DSP_R.DSP_LOGIC_OUTS_B8_4.DSP_0_P47 always
DSP_R.DSP_LOGIC_OUTS_B9_0.DSP_0_P42 always
DSP_R.DSP_LOGIC_OUTS_B9_2.DSP_0_UNDERFLOW always
DSP_R.DSP_LOGIC_OUTS_B9_4.DSP_0_P44 always
DSP_R.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_R.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_R.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_R.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_R.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_R.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_R.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_R.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_R.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_R.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_R.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_R.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_R.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_R.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_R.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_R.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_R.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_R.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_R.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_R.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_R.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_R.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_R.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_R.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_R.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_R.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_R.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_R.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_R.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_R.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_R.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_R.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_R.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_R.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_R.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_R.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_R.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_R.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_R.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_R.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_R.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_R.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_R.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_R.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_R.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_R.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_R.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_R.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_R.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_R.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_R.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_R.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_R.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_R.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_R.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_R.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_R.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_R.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_R.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_R.DSP_MULTSIGNOUT.DSP_1_MULTSIGNOUT always
DSP_R.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_R.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_R.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_R.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_R.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_R.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_R.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_R.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_R.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_R.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_R.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_R.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_R.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_R.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_R.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_R.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_R.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_R.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_R.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_R.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_R.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_R.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_R.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_R.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_R.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_R.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_R.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_R.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_R.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_R.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_R.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_R.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_R.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_R.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_R.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_R.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_R.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_R.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_R.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_R.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_R.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_R.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_R.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_R.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_R.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_R.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_R.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_R.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_R.DSP_PCOUT0.DSP_1_PCOUT0 always
DSP_R.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_R.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_R.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_R.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_R.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_R.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_R.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_R.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_R.DSP_PCOUT9.DSP_1_PCOUT9 always
DSP_R.DSP_PCOUT10.DSP_1_PCOUT10 always
DSP_R.DSP_PCOUT11.DSP_1_PCOUT11 always
DSP_R.DSP_PCOUT12.DSP_1_PCOUT12 always
@ -530,6 +521,7 @@ DSP_R.DSP_PCOUT16.DSP_1_PCOUT16 always
DSP_R.DSP_PCOUT17.DSP_1_PCOUT17 always
DSP_R.DSP_PCOUT18.DSP_1_PCOUT18 always
DSP_R.DSP_PCOUT19.DSP_1_PCOUT19 always
DSP_R.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_R.DSP_PCOUT20.DSP_1_PCOUT20 always
DSP_R.DSP_PCOUT21.DSP_1_PCOUT21 always
DSP_R.DSP_PCOUT22.DSP_1_PCOUT22 always
@ -540,6 +532,7 @@ DSP_R.DSP_PCOUT26.DSP_1_PCOUT26 always
DSP_R.DSP_PCOUT27.DSP_1_PCOUT27 always
DSP_R.DSP_PCOUT28.DSP_1_PCOUT28 always
DSP_R.DSP_PCOUT29.DSP_1_PCOUT29 always
DSP_R.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_R.DSP_PCOUT30.DSP_1_PCOUT30 always
DSP_R.DSP_PCOUT31.DSP_1_PCOUT31 always
DSP_R.DSP_PCOUT32.DSP_1_PCOUT32 always
@ -550,6 +543,7 @@ DSP_R.DSP_PCOUT36.DSP_1_PCOUT36 always
DSP_R.DSP_PCOUT37.DSP_1_PCOUT37 always
DSP_R.DSP_PCOUT38.DSP_1_PCOUT38 always
DSP_R.DSP_PCOUT39.DSP_1_PCOUT39 always
DSP_R.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_R.DSP_PCOUT40.DSP_1_PCOUT40 always
DSP_R.DSP_PCOUT41.DSP_1_PCOUT41 always
DSP_R.DSP_PCOUT42.DSP_1_PCOUT42 always
@ -558,3 +552,9 @@ DSP_R.DSP_PCOUT44.DSP_1_PCOUT44 always
DSP_R.DSP_PCOUT45.DSP_1_PCOUT45 always
DSP_R.DSP_PCOUT46.DSP_1_PCOUT46 always
DSP_R.DSP_PCOUT47.DSP_1_PCOUT47 always
DSP_R.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_R.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_R.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_R.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_R.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_R.DSP_PCOUT9.DSP_1_PCOUT9 always

4
kintex7/ppips_hclk_cmt.db
View File

@ -1,4 +1,4 @@
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF0.HCLK_CMT_BUFMRCE_O0 always
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF1.HCLK_CMT_BUFMRCE_O1 always
HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP0.HCLK_CMT_BUFMR_CE0 always
HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP1.HCLK_CMT_BUFMR_CE1 always
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF0.HCLK_CMT_BUFMRCE_O0 always
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF1.HCLK_CMT_BUFMRCE_O1 always

26
kintex7/ppips_hclk_ioi3.db
View File

@ -1,15 +1,3 @@
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0.HCLK_IOI_RCLK2RCLK0 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1.HCLK_IOI_RCLK2RCLK1 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2.HCLK_IOI_RCLK2RCLK2 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3.HCLK_IOI_RCLK2RCLK3 always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK_OUT0.HCLK_IOI_RCLK_BEFORE_DIV0 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT1.HCLK_IOI_RCLK_BEFORE_DIV1 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT2.HCLK_IOI_RCLK_BEFORE_DIV2 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT3.HCLK_IOI_RCLK_BEFORE_DIV3 always
HCLK_IOI3.HCLK_IOI_BUFR0_CE.HCLK_RCLK_DIV_CE0 always
HCLK_IOI3.HCLK_IOI_BUFR0_CLR.HCLK_RCLK_DIV_CLR0 always
HCLK_IOI3.HCLK_IOI_BUFR1_CE.HCLK_RCLK_DIV_CE1 always
@ -18,14 +6,21 @@ HCLK_IOI3.HCLK_IOI_BUFR2_CE.HCLK_RCLK_DIV_CE2 always
HCLK_IOI3.HCLK_IOI_BUFR2_CLR.HCLK_RCLK_DIV_CLR2 always
HCLK_IOI3.HCLK_IOI_BUFR3_CE.HCLK_RCLK_DIV_CE3 always
HCLK_IOI3.HCLK_IOI_BUFR3_CLR.HCLK_RCLK_DIV_CLR3 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0.HCLK_IOI_RCLK2RCLK0 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1.HCLK_IOI_RCLK2RCLK1 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2.HCLK_IOI_RCLK2RCLK2 always
HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3.HCLK_IOI_RCLK2RCLK3 always
HCLK_IOI3.HCLK_IOI_IOCLK0.HCLK_IOI_BUFIO_O0 always
HCLK_IOI3.HCLK_IOI_IOCLK1.HCLK_IOI_BUFIO_O1 always
HCLK_IOI3.HCLK_IOI_IOCLK2.HCLK_IOI_BUFIO_O2 always
HCLK_IOI3.HCLK_IOI_IOCLK3.HCLK_IOI_BUFIO_O3 always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 always
HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 always
HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 always
@ -34,3 +29,8 @@ HCLK_IOI3.HCLK_IOI_RCLK2RCLK0.HCLK_IOI_RCLK_OUT0 always
HCLK_IOI3.HCLK_IOI_RCLK2RCLK1.HCLK_IOI_RCLK_OUT1 always
HCLK_IOI3.HCLK_IOI_RCLK2RCLK2.HCLK_IOI_RCLK_OUT2 always
HCLK_IOI3.HCLK_IOI_RCLK2RCLK3.HCLK_IOI_RCLK_OUT3 always
HCLK_IOI3.HCLK_IOI_RCLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
HCLK_IOI3.HCLK_IOI_RCLK_OUT0.HCLK_IOI_RCLK_BEFORE_DIV0 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT1.HCLK_IOI_RCLK_BEFORE_DIV1 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT2.HCLK_IOI_RCLK_BEFORE_DIV2 always
HCLK_IOI3.HCLK_IOI_RCLK_OUT3.HCLK_IOI_RCLK_BEFORE_DIV3 always

18
kintex7/ppips_int_interface_l.db
View File

@ -1,13 +1,4 @@
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
@ -18,7 +9,16 @@ INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 alwa
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always

18
kintex7/ppips_int_interface_r.db
View File

@ -1,13 +1,4 @@
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
@ -18,7 +9,16 @@ INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always

26
kintex7/ppips_int_l.db
View File

@ -46,6 +46,10 @@ INT_L.FAN_L4.FAN_ALT4 always
INT_L.FAN_L5.FAN_ALT5 always
INT_L.FAN_L6.FAN_ALT6 always
INT_L.FAN_L7.FAN_ALT7 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.GCLK_L_B6_EAST.GCLK_L_B6 always
INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always
INT_L.GCLK_L_B7_EAST.GCLK_L_B7 always
@ -54,20 +58,7 @@ INT_L.GCLK_L_B8_EAST.GCLK_L_B8 always
INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always
INT_L.GCLK_L_B9_EAST.GCLK_L_B9 always
INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.IMUX_L0.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default
INT_L.IMUX_L10.VCC_WIRE default
INT_L.IMUX_L11.VCC_WIRE default
INT_L.IMUX_L12.VCC_WIRE default
@ -78,6 +69,7 @@ INT_L.IMUX_L16.VCC_WIRE default
INT_L.IMUX_L17.VCC_WIRE default
INT_L.IMUX_L18.VCC_WIRE default
INT_L.IMUX_L19.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L20.VCC_WIRE default
INT_L.IMUX_L21.VCC_WIRE default
INT_L.IMUX_L22.VCC_WIRE default
@ -88,6 +80,7 @@ INT_L.IMUX_L26.VCC_WIRE default
INT_L.IMUX_L27.VCC_WIRE default
INT_L.IMUX_L28.VCC_WIRE default
INT_L.IMUX_L29.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L30.VCC_WIRE default
INT_L.IMUX_L31.VCC_WIRE default
INT_L.IMUX_L32.VCC_WIRE default
@ -98,6 +91,7 @@ INT_L.IMUX_L36.VCC_WIRE default
INT_L.IMUX_L37.VCC_WIRE default
INT_L.IMUX_L38.VCC_WIRE default
INT_L.IMUX_L39.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L40.VCC_WIRE default
INT_L.IMUX_L41.VCC_WIRE default
INT_L.IMUX_L42.VCC_WIRE default
@ -106,3 +100,9 @@ INT_L.IMUX_L44.VCC_WIRE default
INT_L.IMUX_L45.VCC_WIRE default
INT_L.IMUX_L46.VCC_WIRE default
INT_L.IMUX_L47.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default

50
kintex7/ppips_int_r.db
View File

@ -1,3 +1,11 @@
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.BYP_ALT0.VCC_WIRE default
INT_R.BYP_ALT1.VCC_WIRE default
INT_R.BYP_ALT2.VCC_WIRE default
@ -14,6 +22,14 @@ INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.FAN_ALT0.VCC_WIRE default
INT_R.FAN_ALT1.VCC_WIRE default
INT_R.FAN_ALT2.VCC_WIRE default
@ -42,32 +58,7 @@ INT_R.GCLK_B4_EAST.GCLK_B4 always
INT_R.GCLK_B4_WEST.GCLK_B4 always
INT_R.GCLK_B5_EAST.GCLK_B5 always
INT_R.GCLK_B5_WEST.GCLK_B5 always
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.IMUX0.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default
INT_R.IMUX10.VCC_WIRE default
INT_R.IMUX11.VCC_WIRE default
INT_R.IMUX12.VCC_WIRE default
@ -78,6 +69,7 @@ INT_R.IMUX16.VCC_WIRE default
INT_R.IMUX17.VCC_WIRE default
INT_R.IMUX18.VCC_WIRE default
INT_R.IMUX19.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX20.VCC_WIRE default
INT_R.IMUX21.VCC_WIRE default
INT_R.IMUX22.VCC_WIRE default
@ -88,6 +80,7 @@ INT_R.IMUX26.VCC_WIRE default
INT_R.IMUX27.VCC_WIRE default
INT_R.IMUX28.VCC_WIRE default
INT_R.IMUX29.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX30.VCC_WIRE default
INT_R.IMUX31.VCC_WIRE default
INT_R.IMUX32.VCC_WIRE default
@ -98,6 +91,7 @@ INT_R.IMUX36.VCC_WIRE default
INT_R.IMUX37.VCC_WIRE default
INT_R.IMUX38.VCC_WIRE default
INT_R.IMUX39.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX40.VCC_WIRE default
INT_R.IMUX41.VCC_WIRE default
INT_R.IMUX42.VCC_WIRE default
@ -106,3 +100,9 @@ INT_R.IMUX44.VCC_WIRE default
INT_R.IMUX45.VCC_WIRE default
INT_R.IMUX46.VCC_WIRE default
INT_R.IMUX47.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default

18
kintex7/ppips_io_int_interface_l.db
View File

@ -1,13 +1,4 @@
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
@ -18,7 +9,16 @@ IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 a
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always

18
kintex7/ppips_io_int_interface_r.db
View File

@ -1,13 +1,4 @@
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
@ -18,7 +9,16 @@ IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 alway
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always

2
kintex7/ppips_liob33.db
View File

@ -3,8 +3,8 @@ LIOB33.IOB_DIFFI_IN1.IOB_PADOUT0 always
LIOB33.IOB_DIFFO_IN1.IOB_DIFFO_OUT0 always
LIOB33.IOB_O_IN1.IOB_O_OUT0 always
LIOB33.IOB_O_OUT0.IOB_O0 hint
LIOB33.IOB_PADOUT1.IOB_DIFFO_IN1 hint
LIOB33.IOB_T_IN1.IOB_T_OUT0 always
LIOB33.IOB_T_OUT0.IOB_T0 hint
LIOB33.IOB_PADOUT1.IOB_DIFFO_IN1 hint
LIOB33.LIOB_MONITOR_N.IOB_PADOUT1 always
LIOB33.LIOB_MONITOR_P.IOB_PADOUT0 always

168
kintex7/ppips_lioi3.db
View File

@ -1,26 +1,58 @@
LIOI3.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3.IOI_IDELAYCTRL_RST.IOI_IMUX24_0 always
LIOI3.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3.IOI_IMUX_RC2.IOI_BYP4_1 always
LIOI3.IOI_IMUX_RC3.IOI_BYP3_1 always
LIOI3.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
LIOI3.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
LIOI3.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
LIOI3.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
LIOI3.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
LIOI3.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3.IOI_LOGIC_OUTS13_0.IOI_IDELAYCTRL_DNPULSEOUT always
LIOI3.IOI_LOGIC_OUTS13_1.IOI_IDELAYCTRL_OUTN1 always
LIOI3.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
@ -35,66 +67,22 @@ LIOI3.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
LIOI3.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
LIOI3.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3.IOI_LOGIC_OUTS22_1.IOI_IDELAYCTRL_RDY always
LIOI3.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
LIOI3.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
LIOI3.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI3.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI3.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI3.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI3.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI3.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI3.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI3.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI3.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI3.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI3.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI3.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
@ -103,15 +91,15 @@ LIOI3.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI3.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI3.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI3.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI3.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI3.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI3.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI3.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI3.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI3.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI3.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI3.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI3.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI3.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
@ -120,25 +108,43 @@ LIOI3.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI3.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI3.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI3.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI3.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI3.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI3.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI3.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI3.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI3.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI3.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI3.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI3.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI3.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI3.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI3.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI3.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI3.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always
LIOI3.LIOI_DCI_T_TERM0.IOI_IMUX6_1 always
LIOI3.LIOI_DCI_T_TERM1.IOI_IMUX6_0 always
LIOI3.LIOI_I0.LIOI_IBUF0 always
LIOI3.LIOI_I1.LIOI_IBUF1 always
LIOI3.LIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
LIOI3.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI3.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI3.LIOI_I0.LIOI_IBUF0 always
LIOI3.LIOI_I1.LIOI_IBUF1 always
LIOI3.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
LIOI3.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3.LIOI_ILOGIC1_DDLY.LIOI_IDELAY1_DATAOUT always
LIOI3.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3.LIOI_ILOGIC1_OFB.LIOI_OLOGIC1_OFB always
LIOI3.LIOI_ILOGIC1_TFB.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3.LIOI_ISIN11.LIOI_ISOUT10 always
@ -155,9 +161,3 @@ LIOI3.LIOI_OSIN10.LIOI_OSOUT11 always
LIOI3.LIOI_OSIN20.LIOI_OSOUT21 always
LIOI3.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI3.LIOI_T1.LIOI_OLOGIC1_TQ always
LIOI3.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always

66
kintex7/ppips_lioi3_sing.db
View File

@ -1,46 +1,42 @@
LIOI3_SING.IOI_LOGIC_OUTS0_0.IOI_ILOGIC0_Q1 always
LIOI3_SING.IOI_LOGIC_OUTS1_0.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_SING.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_SING.IOI_LOGIC_OUTS3_0.IOI_ILOGIC0_Q6 always
LIOI3_SING.IOI_LOGIC_OUTS5_0.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_SING.IOI_LOGIC_OUTS7_0.IOI_ILOGIC0_Q7 always
LIOI3_SING.IOI_LOGIC_OUTS8_0.IOI_ILOGIC0_Q8 always
LIOI3_SING.IOI_LOGIC_OUTS9_0.IOI_ILOGIC0_Q3 always
LIOI3_SING.IOI_LOGIC_OUTS10_0.IOI_ILOGIC0_Q4 always
LIOI3_SING.IOI_LOGIC_OUTS11_0.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3_SING.IOI_LOGIC_OUTS14_0.IOI_ILOGIC0_Q5 always
LIOI3_SING.IOI_LOGIC_OUTS15_0.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI3_SING.IOI_LOGIC_OUTS18_0.IOI_ILOGIC0_O always
LIOI3_SING.IOI_LOGIC_OUTS19_0.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3_SING.IOI_LOGIC_OUTS20_0.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3_SING.IOI_LOGIC_OUTS23_0.IOI_ILOGIC0_Q2 always
LIOI3_SING.IOI_IDELAY0_C.IOI_CLK1_0 always
LIOI3_SING.IOI_IDELAY0_CE.IOI_IMUX32_0 always
LIOI3_SING.IOI_IDELAY0_CINVCTRL.IOI_BYP6_0 always
LIOI3_SING.IOI_IDELAY0_DATAIN.IOI_IMUX25_0 always
LIOI3_SING.IOI_IDELAY0_INC.IOI_IMUX26_0 always
LIOI3_SING.IOI_IDELAY0_LD.IOI_IMUX30_0 always
LIOI3_SING.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_SING.IOI_IDELAY0_REGRST.IOI_IMUX12_0 always
LIOI3_SING.IOI_IDELAY0_C.IOI_CLK1_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_SING.IOI_IDELAY0_DATAIN.IOI_IMUX25_0 always
LIOI3_SING.IOI_IDELAY0_INC.IOI_IMUX26_0 always
LIOI3_SING.IOI_IDELAY0_LD.IOI_IMUX30_0 always
LIOI3_SING.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_SING.IOI_IDELAY0_REGRST.IOI_IMUX12_0 always
LIOI3_SING.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_0 always
LIOI3_SING.IOI_ILOGIC0_CE1.IOI_IMUX5_0 always
LIOI3_SING.IOI_ILOGIC0_CE2.IOI_IMUX14_0 always
LIOI3_SING.IOI_ILOGIC0_CLKDIV.IOI_CLK0_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_SING.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_SING.IOI_ILOGIC0_SR.IOI_CTRL1_0 always
LIOI3_SING.IOI_ILOGIC0_CE1.IOI_IMUX5_0 always
LIOI3_SING.IOI_ILOGIC0_CE2.IOI_IMUX14_0 always
LIOI3_SING.IOI_LOGIC_OUTS0_0.IOI_ILOGIC0_Q1 always
LIOI3_SING.IOI_LOGIC_OUTS10_0.IOI_ILOGIC0_Q4 always
LIOI3_SING.IOI_LOGIC_OUTS1_0.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_SING.IOI_LOGIC_OUTS11_0.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3_SING.IOI_LOGIC_OUTS14_0.IOI_ILOGIC0_Q5 always
LIOI3_SING.IOI_LOGIC_OUTS15_0.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI3_SING.IOI_LOGIC_OUTS18_0.IOI_ILOGIC0_O always
LIOI3_SING.IOI_LOGIC_OUTS19_0.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3_SING.IOI_LOGIC_OUTS20_0.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3_SING.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_SING.IOI_LOGIC_OUTS23_0.IOI_ILOGIC0_Q2 always
LIOI3_SING.IOI_LOGIC_OUTS3_0.IOI_ILOGIC0_Q6 always
LIOI3_SING.IOI_LOGIC_OUTS5_0.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_SING.IOI_LOGIC_OUTS7_0.IOI_ILOGIC0_Q7 always
LIOI3_SING.IOI_LOGIC_OUTS8_0.IOI_ILOGIC0_Q8 always
LIOI3_SING.IOI_LOGIC_OUTS9_0.IOI_ILOGIC0_Q3 always
LIOI3_SING.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3_SING.IOI_OLOGIC0_OCE.IOI_IMUX29_0 always
LIOI3_SING.IOI_OLOGIC0_SR.IOI_CTRL0_0 always
LIOI3_SING.IOI_OLOGIC0_TBYTEIN.IOI_SING_TBYTEIN always
LIOI3_SING.IOI_OLOGIC0_TCE.IOI_IMUX1_0 always
LIOI3_SING.IOI_OLOGIC0_D1.IOI_IMUX34_0 always
LIOI3_SING.IOI_OLOGIC0_D2.IOI_IMUX40_0 always
LIOI3_SING.IOI_OLOGIC0_D3.IOI_IMUX44_0 always
@ -49,16 +45,23 @@ LIOI3_SING.IOI_OLOGIC0_D5.IOI_IMUX43_0 always
LIOI3_SING.IOI_OLOGIC0_D6.IOI_IMUX45_0 always
LIOI3_SING.IOI_OLOGIC0_D7.IOI_IMUX46_0 always
LIOI3_SING.IOI_OLOGIC0_D8.IOI_IMUX47_0 always
LIOI3_SING.IOI_OLOGIC0_OCE.IOI_IMUX29_0 always
LIOI3_SING.IOI_OLOGIC0_SR.IOI_CTRL0_0 always
LIOI3_SING.IOI_OLOGIC0_T1.IOI_IMUX15_0 always
LIOI3_SING.IOI_OLOGIC0_T2.IOI_IMUX7_0 always
LIOI3_SING.IOI_OLOGIC0_T3.IOI_IMUX13_0 always
LIOI3_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
LIOI3_SING.IOI_OLOGIC0_TBYTEIN.IOI_SING_TBYTEIN always
LIOI3_SING.IOI_OLOGIC0_TCE.IOI_IMUX1_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_0 always
LIOI3_SING.LIOI_DCI_T_TERM0.IOI_IMUX6_0 always
LIOI3_SING.LIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
LIOI3_SING.LIOI_I0.LIOI_IBUF0 always
LIOI3_SING.LIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
LIOI3_SING.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3_SING.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_SING.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3_SING.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_SING.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3_SING.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_SING.LIOI_O0.LIOI_OLOGIC0_OQ always
@ -66,6 +69,3 @@ LIOI3_SING.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI3_SING.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI3_SING.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI3_SING.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_0 always

204
kintex7/ppips_lioi3_tbytesrc.db
View File

@ -1,23 +1,55 @@
LIOI3_TBYTESRC.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3_TBYTESRC.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3_TBYTESRC.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_TBYTESRC.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3_TBYTESRC.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3_TBYTESRC.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
@ -28,8 +60,54 @@ LIOI3_TBYTESRC.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3_TBYTESRC.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI3_TBYTESRC.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3_TBYTESRC.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI3_TBYTESRC.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
@ -39,99 +117,27 @@ LIOI3_TBYTESRC.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI3_TBYTESRC.IOI_TBYTEIN.IOI_OLOGIC1_TBYTEOUT always
LIOI3_TBYTESRC.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3_TBYTESRC.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_TBYTESRC.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_TBYTESRC.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3_TBYTESRC.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3_TBYTESRC.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3_TBYTESRC.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3_TBYTESRC.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI3_TBYTESRC.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI3_TBYTESRC.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI3_TBYTESRC.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI3_TBYTESRC.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always
LIOI3_TBYTESRC.LIOI_DCI_T_TERM0.IOI_IMUX6_1 always
LIOI3_TBYTESRC.LIOI_DCI_T_TERM1.IOI_IMUX6_0 always
LIOI3_TBYTESRC.LIOI_I0.LIOI_IBUF0 always
LIOI3_TBYTESRC.LIOI_I1.LIOI_IBUF1 always
LIOI3_TBYTESRC.LIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
LIOI3_TBYTESRC.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI3_TBYTESRC.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI3_TBYTESRC.LIOI_I0.LIOI_IBUF0 always
LIOI3_TBYTESRC.LIOI_I1.LIOI_IBUF1 always
LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3_TBYTESRC.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
LIOI3_TBYTESRC.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3_TBYTESRC.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_TBYTESRC.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3_TBYTESRC.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTESRC.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3_TBYTESRC.LIOI_ILOGIC1_DDLY.LIOI_IDELAY1_DATAOUT always
LIOI3_TBYTESRC.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3_TBYTESRC.LIOI_ILOGIC1_OFB.LIOI_OLOGIC1_OFB always
LIOI3_TBYTESRC.LIOI_ILOGIC1_TFB.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTESRC.LIOI_ISIN11.LIOI_ISOUT10 always
@ -148,9 +154,3 @@ LIOI3_TBYTESRC.LIOI_OSIN10.LIOI_OSOUT11 always
LIOI3_TBYTESRC.LIOI_OSIN20.LIOI_OSOUT21 always
LIOI3_TBYTESRC.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI3_TBYTESRC.LIOI_T1.LIOI_OLOGIC1_TQ always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always

168
kintex7/ppips_lioi3_tbyteterm.db
View File

@ -1,23 +1,55 @@
LIOI3_TBYTETERM.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3_TBYTETERM.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3_TBYTETERM.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_TBYTETERM.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3_TBYTETERM.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3_TBYTETERM.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
@ -28,65 +60,21 @@ LIOI3_TBYTETERM.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI3_TBYTETERM.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3_TBYTETERM.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_TBYTETERM.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_TBYTETERM.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3_TBYTETERM.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3_TBYTETERM.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3_TBYTETERM.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3_TBYTETERM.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3_TBYTETERM.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3_TBYTETERM.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3_TBYTETERM.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN_TERM always
LIOI3_TBYTETERM.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
@ -95,15 +83,15 @@ LIOI3_TBYTETERM.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI3_TBYTETERM.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN_TERM always
LIOI3_TBYTETERM.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3_TBYTETERM.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI3_TBYTETERM.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN_TERM always
LIOI3_TBYTETERM.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
@ -112,24 +100,42 @@ LIOI3_TBYTETERM.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI3_TBYTETERM.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN_TERM always
LIOI3_TBYTETERM.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI3_TBYTETERM.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI3_TBYTETERM.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3_TBYTETERM.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3_TBYTETERM.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3_TBYTETERM.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3_TBYTETERM.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3_TBYTETERM.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always
LIOI3_TBYTETERM.LIOI_DCI_T_TERM0.IOI_IMUX6_1 always
LIOI3_TBYTETERM.LIOI_DCI_T_TERM1.IOI_IMUX6_0 always
LIOI3_TBYTETERM.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI3_TBYTETERM.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI3_TBYTETERM.LIOI_I0.LIOI_IBUF0 always
LIOI3_TBYTETERM.LIOI_I1.LIOI_IBUF1 always
LIOI3_TBYTETERM.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI3_TBYTETERM.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI3_TBYTETERM.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3_TBYTETERM.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
LIOI3_TBYTETERM.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_TBYTETERM.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3_TBYTETERM.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_TBYTETERM.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3_TBYTETERM.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTETERM.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3_TBYTETERM.LIOI_ILOGIC1_DDLY.LIOI_IDELAY1_DATAOUT always
LIOI3_TBYTETERM.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3_TBYTETERM.LIOI_ILOGIC1_OFB.LIOI_OLOGIC1_OFB always
LIOI3_TBYTETERM.LIOI_ILOGIC1_TFB.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTETERM.LIOI_ISIN11.LIOI_ISOUT10 always
@ -146,9 +152,3 @@ LIOI3_TBYTETERM.LIOI_OSIN10.LIOI_OSOUT11 always
LIOI3_TBYTETERM.LIOI_OSIN20.LIOI_OSOUT21 always
LIOI3_TBYTETERM.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI3_TBYTETERM.LIOI_T1.LIOI_OLOGIC1_TQ always
LIOI3_TBYTETERM.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3_TBYTETERM.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3_TBYTETERM.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3_TBYTETERM.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3_TBYTETERM.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3_TBYTETERM.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always

2408
kintex7/ppips_pcie_bot.db
View File

File diff suppressed because it is too large Load Diff

54
kintex7/ppips_pcie_int_interface_l.db
View File

@ -1,13 +1,4 @@
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
@ -18,20 +9,20 @@ PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY0.PCIE_INT_INTERFACE_IMUX_L0 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY1.PCIE_INT_INTERFACE_IMUX_L1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY2.PCIE_INT_INTERFACE_IMUX_L2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY3.PCIE_INT_INTERFACE_IMUX_L3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY4.PCIE_INT_INTERFACE_IMUX_L4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY5.PCIE_INT_INTERFACE_IMUX_L5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY6.PCIE_INT_INTERFACE_IMUX_L6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY7.PCIE_INT_INTERFACE_IMUX_L7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY8.PCIE_INT_INTERFACE_IMUX_L8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY9.PCIE_INT_INTERFACE_IMUX_L9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY10.PCIE_INT_INTERFACE_IMUX_L10 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY11.PCIE_INT_INTERFACE_IMUX_L11 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY12.PCIE_INT_INTERFACE_IMUX_L12 always
@ -42,6 +33,7 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY16.PCIE_INT_INTERFACE_IMUX_L
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY17.PCIE_INT_INTERFACE_IMUX_L17 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY18.PCIE_INT_INTERFACE_IMUX_L18 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY19.PCIE_INT_INTERFACE_IMUX_L19 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY1.PCIE_INT_INTERFACE_IMUX_L1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY20.PCIE_INT_INTERFACE_IMUX_L20 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY21.PCIE_INT_INTERFACE_IMUX_L21 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY22.PCIE_INT_INTERFACE_IMUX_L22 always
@ -52,6 +44,7 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY26.PCIE_INT_INTERFACE_IMUX_L
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY27.PCIE_INT_INTERFACE_IMUX_L27 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY28.PCIE_INT_INTERFACE_IMUX_L28 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY29.PCIE_INT_INTERFACE_IMUX_L29 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY2.PCIE_INT_INTERFACE_IMUX_L2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY30.PCIE_INT_INTERFACE_IMUX_L30 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY31.PCIE_INT_INTERFACE_IMUX_L31 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY32.PCIE_INT_INTERFACE_IMUX_L32 always
@ -62,6 +55,7 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY36.PCIE_INT_INTERFACE_IMUX_L
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY37.PCIE_INT_INTERFACE_IMUX_L37 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY38.PCIE_INT_INTERFACE_IMUX_L38 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY39.PCIE_INT_INTERFACE_IMUX_L39 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY3.PCIE_INT_INTERFACE_IMUX_L3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY40.PCIE_INT_INTERFACE_IMUX_L40 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY41.PCIE_INT_INTERFACE_IMUX_L41 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY42.PCIE_INT_INTERFACE_IMUX_L42 always
@ -70,16 +64,13 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY44.PCIE_INT_INTERFACE_IMUX_L
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY45.PCIE_INT_INTERFACE_IMUX_L45 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY46.PCIE_INT_INTERFACE_IMUX_L46 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY47.PCIE_INT_INTERFACE_IMUX_L47 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY4.PCIE_INT_INTERFACE_IMUX_L4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY5.PCIE_INT_INTERFACE_IMUX_L5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY6.PCIE_INT_INTERFACE_IMUX_L6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY7.PCIE_INT_INTERFACE_IMUX_L7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY8.PCIE_INT_INTERFACE_IMUX_L8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY9.PCIE_INT_INTERFACE_IMUX_L9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L0 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L10 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L11 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L12 always
@ -90,6 +81,7 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L16
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L17 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L18 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L19 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L20 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L21 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L22 always
@ -100,6 +92,7 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L26
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L27 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L28 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L29 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L30 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L31 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L32 always
@ -110,6 +103,7 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L36
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L37 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L38 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L39 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L40 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L41 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L42 always
@ -118,3 +112,9 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L44
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L45 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L46 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L47 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L9 always

54
kintex7/ppips_pcie_int_interface_r.db
View File

@ -1,13 +1,4 @@
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
@ -18,20 +9,20 @@ PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 alw
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY0.PCIE_INT_INTERFACE_IMUX0 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY1.PCIE_INT_INTERFACE_IMUX1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY2.PCIE_INT_INTERFACE_IMUX2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY3.PCIE_INT_INTERFACE_IMUX3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY4.PCIE_INT_INTERFACE_IMUX4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY5.PCIE_INT_INTERFACE_IMUX5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY6.PCIE_INT_INTERFACE_IMUX6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY7.PCIE_INT_INTERFACE_IMUX7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY8.PCIE_INT_INTERFACE_IMUX8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY9.PCIE_INT_INTERFACE_IMUX9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY10.PCIE_INT_INTERFACE_IMUX10 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY11.PCIE_INT_INTERFACE_IMUX11 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY12.PCIE_INT_INTERFACE_IMUX12 always
@ -42,6 +33,7 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY16.PCIE_INT_INTERFACE_IMUX16 a
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY17.PCIE_INT_INTERFACE_IMUX17 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY18.PCIE_INT_INTERFACE_IMUX18 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY19.PCIE_INT_INTERFACE_IMUX19 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY1.PCIE_INT_INTERFACE_IMUX1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY20.PCIE_INT_INTERFACE_IMUX20 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY21.PCIE_INT_INTERFACE_IMUX21 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY22.PCIE_INT_INTERFACE_IMUX22 always
@ -52,6 +44,7 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY26.PCIE_INT_INTERFACE_IMUX26 a
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY27.PCIE_INT_INTERFACE_IMUX27 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY28.PCIE_INT_INTERFACE_IMUX28 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY29.PCIE_INT_INTERFACE_IMUX29 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY2.PCIE_INT_INTERFACE_IMUX2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY30.PCIE_INT_INTERFACE_IMUX30 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY31.PCIE_INT_INTERFACE_IMUX31 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY32.PCIE_INT_INTERFACE_IMUX32 always
@ -62,6 +55,7 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY36.PCIE_INT_INTERFACE_IMUX36 a
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY37.PCIE_INT_INTERFACE_IMUX37 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY38.PCIE_INT_INTERFACE_IMUX38 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY39.PCIE_INT_INTERFACE_IMUX39 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY3.PCIE_INT_INTERFACE_IMUX3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY40.PCIE_INT_INTERFACE_IMUX40 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY41.PCIE_INT_INTERFACE_IMUX41 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY42.PCIE_INT_INTERFACE_IMUX42 always
@ -70,16 +64,13 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY44.PCIE_INT_INTERFACE_IMUX44 a
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY45.PCIE_INT_INTERFACE_IMUX45 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY46.PCIE_INT_INTERFACE_IMUX46 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY47.PCIE_INT_INTERFACE_IMUX47 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY4.PCIE_INT_INTERFACE_IMUX4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY5.PCIE_INT_INTERFACE_IMUX5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY6.PCIE_INT_INTERFACE_IMUX6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY7.PCIE_INT_INTERFACE_IMUX7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY8.PCIE_INT_INTERFACE_IMUX8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY9.PCIE_INT_INTERFACE_IMUX9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX0 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX10 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX11 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX12 always
@ -90,6 +81,7 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX16 alw
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX17 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX18 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX19 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX20 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX21 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX22 always
@ -100,6 +92,7 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX26 alw
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX27 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX28 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX29 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX30 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX31 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX32 always
@ -110,6 +103,7 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX36 alw
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX37 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX38 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX39 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX40 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX41 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX42 always
@ -118,3 +112,9 @@ PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX44 alw
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX45 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX46 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX47 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX9 always

242
kintex7/ppips_pcie_top.db
View File

@ -8,96 +8,6 @@ PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_1.PCIE_TOP_MIMRXWDATA24 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_2.PCIE_TOP_MIMRXWADDR2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_3.PCIE_TOP_TRNRD83 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_4.PCIE_TOP_TRNRD79 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_0.PCIE_TOP_TRNRD60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_1.PCIE_TOP_TRNRD64 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_2.PCIE_TOP_TRNRD68 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_3.PCIE_TOP_TRNRD72 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TOP_TRNRD76 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_0.PCIE_TOP_MIMRXWADDR12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TOP_TRNRD91 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_2.PCIE_TOP_MIMRXWDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_3.PCIE_TOP_TRNRD84 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_4.PCIE_TOP_TRNTDSTRDY3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_0.PCIE_TOP_TRNRD61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_1.PCIE_TOP_TRNRD65 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_2.PCIE_TOP_TRNRD69 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TOP_TRNRD73 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_4.PCIE_TOP_TRNRD77 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_0.PCIE_TOP_TRNRD95 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TOP_MIMRXWDATA12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_2.PCIE_TOP_TRNRD87 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_3.PCIE_TOP_TRNRD85 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_4.PCIE_TOP_TRNRD80 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_0.PCIE_TOP_TRNRD62 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_1.PCIE_TOP_TRNRD66 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_2.PCIE_TOP_TRNRD70 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_3.PCIE_TOP_TRNRD74 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TOP_TRNRD78 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TOP_MIMRXRADDR10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TOP_TRNRD92 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_2.PCIE_TOP_TRNRD88 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_3.PCIE_TOP_MIMRXWDATA9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_4.PCIE_TOP_TRNRD81 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_0.PCIE_TOP_TRNRDLLPDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TOP_TRNRDLLPDATA36 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_2.PCIE_TOP_TRNRDLLPDATA40 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TOP_TRNRDLLPDATA44 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_4.PCIE_TOP_TRNRDLLPDATA48 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_0.PCIE_TOP_TRNRD96 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TOP_TRNRD93 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_2.PCIE_TOP_TRNRD89 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TOP_TRNRD86 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_4.PCIE_TOP_TRNRD82 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_0.PCIE_TOP_TRNRDLLPDATA33 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TOP_TRNRDLLPDATA37 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_2.PCIE_TOP_TRNRDLLPDATA41 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TOP_TRNRDLLPDATA45 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TOP_TRNRDLLPDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TOP_TRNRD97 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_1.PCIE_TOP_MIMRXWDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_2.PCIE_TOP_MIMRXRADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TOP_TRNRDLLPDATA56 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TOP_TRNRDLLPDATA52 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_0.PCIE_TOP_PIPETXMARGIN2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TOP_TRNRDLLPDATA38 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_2.PCIE_TOP_TRNRDLLPDATA42 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TOP_TRNRDLLPDATA46 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_4.PCIE_TOP_TRNRDLLPDATA50 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_0.PCIE_TOP_TRNRD98 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_1.PCIE_TOP_TRNRD94 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_2.PCIE_TOP_TRNRD90 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_3.PCIE_TOP_TRNRDLLPDATA57 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_4.PCIE_TOP_TRNRDLLPDATA53 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_0.PCIE_TOP_TRNRDLLPDATA34 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TOP_TRNRDLLPDATA39 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_2.PCIE_TOP_TRNRDLLPDATA43 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TOP_TRNRDLLPDATA47 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TOP_TRNRDLLPDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TOP_PL2SUSPENDOK always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_1.PCIE_TOP_MIMRXWDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_2.PCIE_TOP_TRNRDLLPDATA60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_3.PCIE_TOP_TRNRDLLPDATA58 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_4.PCIE_TOP_TRNRDLLPDATA54 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_0.PCIE_TOP_TRNRDLLPDATA35 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TOP_CFGPMRCVENTERL23N always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_2.PCIE_TOP_CFGPMCSRPMEEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TOP_CFGTRANSACTIONADDR0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TOP_CFGTRANSACTIONADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TOP_MIMRXRADDR9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_1.PCIE_TOP_MIMRXWDATA8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TOP_TRNRDLLPDATA61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_3.PCIE_TOP_MIMRXWDATA19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_4.PCIE_TOP_MIMRXWDATA29 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_0.PCIE_TOP_CFGPCIELINKSTATE1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_1.PCIE_TOP_CFGPMRCVREQACKN always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_2.PCIE_TOP_CFGPMCSRPMESTATUS always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_3.PCIE_TOP_CFGTRANSACTIONADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TOP_CFGTRANSACTIONADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_0.PCIE_TOP_MIMRXWDATA4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_1.PCIE_TOP_MIMRXWADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_2.PCIE_TOP_MIMRXWDATA17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_3.PCIE_TOP_TRNRDLLPDATA59 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_4.PCIE_TOP_MIMRXWDATA13 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_0.PCIE_TOP_CFGPCIELINKSTATE2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_2.PCIE_TOP_CFGTRANSACTION always
@ -198,6 +108,16 @@ PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_1.PCIE_TOP_MIMRXWDATA10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_2.PCIE_TOP_CFGMGMTDO19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_3.PCIE_TOP_MIMRXWDATA21 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_4.PCIE_TOP_MIMRXWDATA27 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_0.PCIE_TOP_TRNRD60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_1.PCIE_TOP_TRNRD64 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_2.PCIE_TOP_TRNRD68 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_3.PCIE_TOP_TRNRD72 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TOP_TRNRD76 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_0.PCIE_TOP_MIMRXWADDR12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TOP_TRNRD91 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_2.PCIE_TOP_MIMRXWDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_3.PCIE_TOP_TRNRD84 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_4.PCIE_TOP_TRNTDSTRDY3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_0.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_1.PCIE_TOP_DRPDO11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_2.PCIE_TOP_DRPDO15 always
@ -237,22 +157,93 @@ PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_1.PCIE_TOP_DBGVECA17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_2.PCIE_TOP_DBGVECA15 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_3.PCIE_TOP_MIMRXWDATA7 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_4.PCIE_TOP_CFGDEVCONTROL2LTREN always
PCIE_TOP.PCIE_TOP_CFGERRLOCKEDN.PCIE_IMUX17_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRNORECOVERYN.PCIE_IMUX18_R_2 always
PCIE_TOP.PCIE_TOP_CFGINTERRUPTN.PCIE_IMUX19_R_4 always
PCIE_TOP.PCIE_TOP_LL2SENDPMACK.PCIE_IMUX2_L_4 always
PCIE_TOP.PCIE_TOP_LL2SUSPENDNOW.PCIE_IMUX16_R_3 always
PCIE_TOP.PCIE_TOP_LL2TLPRCV.PCIE_IMUX2_L_3 always
PCIE_TOP.PCIE_TOP_PIPERX0CHANISALIGNED.PCIE_IMUX33_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0PHYSTATUS.PCIE_IMUX37_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0VALID.PCIE_IMUX36_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX4CHANISALIGNED.PCIE_IMUX33_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4PHYSTATUS.PCIE_IMUX37_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4VALID.PCIE_IMUX36_R_0 always
PCIE_TOP.PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK.PCIE_IMUX18_R_3 always
PCIE_TOP.PCIE_TOP_TL2PPMSUSPENDREQ.PCIE_IMUX17_R_3 always
PCIE_TOP.PCIE_TOP_TRNTDLLPSRCRDY.PCIE_IMUX1_L_3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_0.PCIE_TOP_TRNRD61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_1.PCIE_TOP_TRNRD65 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_2.PCIE_TOP_TRNRD69 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TOP_TRNRD73 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_4.PCIE_TOP_TRNRD77 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_0.PCIE_TOP_TRNRD95 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TOP_MIMRXWDATA12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_2.PCIE_TOP_TRNRD87 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_3.PCIE_TOP_TRNRD85 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_4.PCIE_TOP_TRNRD80 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_0.PCIE_TOP_TRNRD62 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_1.PCIE_TOP_TRNRD66 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_2.PCIE_TOP_TRNRD70 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_3.PCIE_TOP_TRNRD74 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TOP_TRNRD78 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TOP_MIMRXRADDR10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TOP_TRNRD92 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_2.PCIE_TOP_TRNRD88 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_3.PCIE_TOP_MIMRXWDATA9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_4.PCIE_TOP_TRNRD81 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_0.PCIE_TOP_TRNRDLLPDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TOP_TRNRDLLPDATA36 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_2.PCIE_TOP_TRNRDLLPDATA40 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TOP_TRNRDLLPDATA44 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_4.PCIE_TOP_TRNRDLLPDATA48 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_0.PCIE_TOP_TRNRD96 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TOP_TRNRD93 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_2.PCIE_TOP_TRNRD89 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TOP_TRNRD86 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_4.PCIE_TOP_TRNRD82 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_0.PCIE_TOP_TRNRDLLPDATA33 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TOP_TRNRDLLPDATA37 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_2.PCIE_TOP_TRNRDLLPDATA41 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TOP_TRNRDLLPDATA45 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TOP_TRNRDLLPDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TOP_TRNRD97 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_1.PCIE_TOP_MIMRXWDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_2.PCIE_TOP_MIMRXRADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TOP_TRNRDLLPDATA56 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TOP_TRNRDLLPDATA52 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_0.PCIE_TOP_PIPETXMARGIN2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TOP_TRNRDLLPDATA38 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_2.PCIE_TOP_TRNRDLLPDATA42 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TOP_TRNRDLLPDATA46 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_4.PCIE_TOP_TRNRDLLPDATA50 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_0.PCIE_TOP_TRNRD98 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_1.PCIE_TOP_TRNRD94 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_2.PCIE_TOP_TRNRD90 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_3.PCIE_TOP_TRNRDLLPDATA57 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_4.PCIE_TOP_TRNRDLLPDATA53 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_0.PCIE_TOP_TRNRDLLPDATA34 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TOP_TRNRDLLPDATA39 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_2.PCIE_TOP_TRNRDLLPDATA43 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TOP_TRNRDLLPDATA47 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TOP_TRNRDLLPDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TOP_PL2SUSPENDOK always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_1.PCIE_TOP_MIMRXWDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_2.PCIE_TOP_TRNRDLLPDATA60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_3.PCIE_TOP_TRNRDLLPDATA58 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_4.PCIE_TOP_TRNRDLLPDATA54 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_0.PCIE_TOP_TRNRDLLPDATA35 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TOP_CFGPMRCVENTERL23N always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_2.PCIE_TOP_CFGPMCSRPMEEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TOP_CFGTRANSACTIONADDR0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TOP_CFGTRANSACTIONADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TOP_MIMRXRADDR9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_1.PCIE_TOP_MIMRXWDATA8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TOP_TRNRDLLPDATA61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_3.PCIE_TOP_MIMRXWDATA19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_4.PCIE_TOP_MIMRXWDATA29 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_0.PCIE_TOP_CFGPCIELINKSTATE1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_1.PCIE_TOP_CFGPMRCVREQACKN always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_2.PCIE_TOP_CFGPMCSRPMESTATUS always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_3.PCIE_TOP_CFGTRANSACTIONADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TOP_CFGTRANSACTIONADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_0.PCIE_TOP_MIMRXWDATA4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_1.PCIE_TOP_MIMRXWADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_2.PCIE_TOP_MIMRXWDATA17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_3.PCIE_TOP_TRNRDLLPDATA59 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_4.PCIE_TOP_MIMRXWDATA13 always
PCIE_TOP.PCIE_TOP_CFGDEVID0.PCIE_IMUX11_L_1 always
PCIE_TOP.PCIE_TOP_CFGDEVID10.PCIE_IMUX9_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID11.PCIE_IMUX10_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID12.PCIE_IMUX11_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID13.PCIE_IMUX21_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID14.PCIE_IMUX22_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID15.PCIE_IMUX23_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID1.PCIE_IMUX8_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID2.PCIE_IMUX9_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID3.PCIE_IMUX10_L_2 always
@ -262,12 +253,6 @@ PCIE_TOP.PCIE_TOP_CFGDEVID6.PCIE_IMUX9_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID7.PCIE_IMUX10_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID8.PCIE_IMUX11_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID9.PCIE_IMUX8_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID10.PCIE_IMUX9_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID11.PCIE_IMUX10_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID12.PCIE_IMUX11_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID13.PCIE_IMUX21_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID14.PCIE_IMUX22_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID15.PCIE_IMUX23_R_4 always
PCIE_TOP.PCIE_TOP_CFGDSN57.PCIE_IMUX8_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN58.PCIE_IMUX9_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN59.PCIE_IMUX10_L_0 always
@ -276,6 +261,8 @@ PCIE_TOP.PCIE_TOP_CFGDSN61.PCIE_IMUX8_L_1 always
PCIE_TOP.PCIE_TOP_CFGDSN62.PCIE_IMUX9_L_1 always
PCIE_TOP.PCIE_TOP_CFGDSN63.PCIE_IMUX10_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG0.PCIE_IMUX19_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG10.PCIE_IMUX24_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG11.PCIE_IMUX21_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG1.PCIE_IMUX20_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG2.PCIE_IMUX20_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG3.PCIE_IMUX21_R_3 always
@ -285,8 +272,8 @@ PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG6.PCIE_IMUX13_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG7.PCIE_IMUX14_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG8.PCIE_IMUX15_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG9.PCIE_IMUX16_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG10.PCIE_IMUX24_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG11.PCIE_IMUX21_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRLOCKEDN.PCIE_IMUX17_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRNORECOVERYN.PCIE_IMUX18_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER26.PCIE_IMUX4_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER27.PCIE_IMUX5_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER28.PCIE_IMUX6_L_0 always
@ -310,11 +297,18 @@ PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER45.PCIE_IMUX7_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER46.PCIE_IMUX17_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER47.PCIE_IMUX18_R_4 always
PCIE_TOP.PCIE_TOP_CFGINTERRUPTDI0.PCIE_IMUX20_R_4 always
PCIE_TOP.PCIE_TOP_CFGINTERRUPTN.PCIE_IMUX19_R_4 always
PCIE_TOP.PCIE_TOP_CFGVENDID0.PCIE_IMUX24_R_4 always
PCIE_TOP.PCIE_TOP_DBGMODE0.PCIE_IMUX25_R_4 always
PCIE_TOP.PCIE_TOP_DRPADDR7.PCIE_IMUX12_L_0 always
PCIE_TOP.PCIE_TOP_DRPADDR8.PCIE_IMUX13_L_0 always
PCIE_TOP.PCIE_TOP_DRPDI0.PCIE_IMUX12_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI10.PCIE_IMUX14_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI11.PCIE_IMUX15_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI12.PCIE_IMUX12_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI13.PCIE_IMUX13_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI14.PCIE_IMUX14_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI15.PCIE_IMUX15_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI1.PCIE_IMUX13_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI2.PCIE_IMUX14_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI3.PCIE_IMUX15_L_1 always
@ -324,15 +318,12 @@ PCIE_TOP.PCIE_TOP_DRPDI6.PCIE_IMUX14_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI7.PCIE_IMUX15_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI8.PCIE_IMUX12_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI9.PCIE_IMUX13_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI10.PCIE_IMUX14_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI11.PCIE_IMUX15_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI12.PCIE_IMUX12_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI13.PCIE_IMUX13_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI14.PCIE_IMUX14_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI15.PCIE_IMUX15_L_4 always
PCIE_TOP.PCIE_TOP_LL2SENDASREQL1.PCIE_IMUX1_L_4 always
PCIE_TOP.PCIE_TOP_LL2SENDENTERL1.PCIE_IMUX3_L_3 always
PCIE_TOP.PCIE_TOP_LL2SENDENTERL23.PCIE_IMUX0_L_4 always
PCIE_TOP.PCIE_TOP_LL2SENDPMACK.PCIE_IMUX2_L_4 always
PCIE_TOP.PCIE_TOP_LL2SUSPENDNOW.PCIE_IMUX16_R_3 always
PCIE_TOP.PCIE_TOP_LL2TLPRCV.PCIE_IMUX2_L_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA20.PCIE_IMUX0_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA21.PCIE_IMUX1_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA22.PCIE_IMUX2_R_0 always
@ -369,6 +360,7 @@ PCIE_TOP.PCIE_TOP_MIMRXRDATA52.PCIE_IMUX4_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA53.PCIE_IMUX5_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA54.PCIE_IMUX6_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA55.PCIE_IMUX7_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX0CHANISALIGNED.PCIE_IMUX33_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0CHARISK0.PCIE_IMUX16_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA0.PCIE_IMUX37_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA1.PCIE_IMUX36_L_1 always
@ -378,6 +370,9 @@ PCIE_TOP.PCIE_TOP_PIPERX0DATA4.PCIE_IMUX39_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA5.PCIE_IMUX38_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA6.PCIE_IMUX35_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA7.PCIE_IMUX34_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0PHYSTATUS.PCIE_IMUX37_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0VALID.PCIE_IMUX36_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX4CHANISALIGNED.PCIE_IMUX33_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4CHARISK0.PCIE_IMUX16_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA0.PCIE_IMUX37_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA1.PCIE_IMUX36_R_1 always
@ -387,13 +382,15 @@ PCIE_TOP.PCIE_TOP_PIPERX4DATA4.PCIE_IMUX39_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA5.PCIE_IMUX38_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA6.PCIE_IMUX35_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA7.PCIE_IMUX34_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4PHYSTATUS.PCIE_IMUX37_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4VALID.PCIE_IMUX36_R_0 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE0.PCIE_IMUX3_L_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE1.PCIE_IMUX8_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE2.PCIE_IMUX9_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE3.PCIE_IMUX10_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE4.PCIE_IMUX11_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD8.PCIE_IMUX8_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD9.PCIE_IMUX9_R_0 always
PCIE_TOP.PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK.PCIE_IMUX18_R_3 always
PCIE_TOP.PCIE_TOP_TL2PPMSUSPENDREQ.PCIE_IMUX17_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD10.PCIE_IMUX10_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD11.PCIE_IMUX11_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD12.PCIE_IMUX8_R_1 always
@ -426,6 +423,8 @@ PCIE_TOP.PCIE_TOP_TRNTD38.PCIE_IMUX14_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD39.PCIE_IMUX15_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD40.PCIE_IMUX12_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD41.PCIE_IMUX13_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD8.PCIE_IMUX8_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD9.PCIE_IMUX9_R_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA19.PCIE_IMUX0_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA20.PCIE_IMUX1_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA21.PCIE_IMUX2_L_0 always
@ -439,3 +438,4 @@ PCIE_TOP.PCIE_TOP_TRNTDLLPDATA28.PCIE_IMUX1_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA29.PCIE_IMUX2_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA30.PCIE_IMUX3_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA31.PCIE_IMUX0_L_3 always
PCIE_TOP.PCIE_TOP_TRNTDLLPSRCRDY.PCIE_IMUX1_L_3 always

10
kintex7/ppips_riob18.db Normal file
View File

@ -0,0 +1,10 @@
RIOB18.IOB_DIFFI_IN0.IOB_PADOUT1 always
RIOB18.IOB_DIFFI_IN1.IOB_PADOUT0 always
RIOB18.IOB_DIFFO_IN1.IOB_DIFFO_OUT0 always
RIOB18.IOB_O_IN1.IOB_O_OUT0 always
RIOB18.IOB_O_OUT0.IOB_O0 hint
RIOB18.IOB_PADOUT1.IOB_DIFFO_IN1 hint
RIOB18.IOB_T_IN1.IOB_T_OUT0 always
RIOB18.IOB_T_OUT0.IOB_T0 hint
RIOB18.RIOB_MONITOR_N.IOB_PADOUT1 always
RIOB18.RIOB_MONITOR_P.IOB_PADOUT0 always

0
kintex7/ppips_riob18_sing.db Normal file
View File

207
kintex7/ppips_rioi.db Normal file
View File

@ -0,0 +1,207 @@
RIOI.IOI_IDELAY0_CE.IOI_IMUX32_1 always
RIOI.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
RIOI.IOI_IDELAY0_C.IOI_CLK1_1 always
RIOI.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
RIOI.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
RIOI.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
RIOI.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
RIOI.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
RIOI.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
RIOI.IOI_IDELAY0_INC.IOI_IMUX26_1 always
RIOI.IOI_IDELAY0_LD.IOI_IMUX30_1 always
RIOI.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
RIOI.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
RIOI.IOI_IDELAY1_CE.IOI_IMUX32_0 always
RIOI.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
RIOI.IOI_IDELAY1_C.IOI_CLK1_0 always
RIOI.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
RIOI.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
RIOI.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
RIOI.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
RIOI.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
RIOI.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
RIOI.IOI_IDELAY1_INC.IOI_IMUX26_0 always
RIOI.IOI_IDELAY1_LD.IOI_IMUX30_0 always
RIOI.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
RIOI.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
RIOI.IOI_IDELAYCTRL_RST.IOI_IMUX24_0 always
RIOI.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
RIOI.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
RIOI.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
RIOI.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
RIOI.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
RIOI.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
RIOI.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
RIOI.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
RIOI.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
RIOI.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
RIOI.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
RIOI.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
RIOI.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
RIOI.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
RIOI.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
RIOI.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
RIOI.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
RIOI.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
RIOI.IOI_IMUX_RC2.IOI_BYP4_1 always
RIOI.IOI_IMUX_RC3.IOI_BYP3_1 always
RIOI.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
RIOI.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
RIOI.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
RIOI.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
RIOI.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
RIOI.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
RIOI.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
RIOI.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
RIOI.IOI_LOGIC_OUTS12_0.IOI_ODELAY1_CNTVALUEOUT0 always
RIOI.IOI_LOGIC_OUTS12_1.IOI_ODELAY0_CNTVALUEOUT0 always
RIOI.IOI_LOGIC_OUTS13_0.IOI_IDELAYCTRL_DNPULSEOUT always
RIOI.IOI_LOGIC_OUTS13_1.IOI_IDELAYCTRL_OUTN1 always
RIOI.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
RIOI.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
RIOI.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
RIOI.IOI_LOGIC_OUTS15_1.IOI_IDELAY0_CNTVALUEOUT3 always
RIOI.IOI_LOGIC_OUTS16_0.IOI_IDELAYCTRL_UPPULSEOUT always
RIOI.IOI_LOGIC_OUTS16_1.IOI_IDELAYCTRL_OUTN65 always
RIOI.IOI_LOGIC_OUTS17_0.IOI_ODELAY1_CNTVALUEOUT3 always
RIOI.IOI_LOGIC_OUTS17_1.IOI_ODELAY0_CNTVALUEOUT3 always
RIOI.IOI_LOGIC_OUTS18_0.IOI_ILOGIC1_O always
RIOI.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O always
RIOI.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
RIOI.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
RIOI.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
RIOI.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
RIOI.IOI_LOGIC_OUTS2_0.RIOI_OLOGIC1_TFB_LOCAL always
RIOI.IOI_LOGIC_OUTS21_0.IOI_ODELAY1_CNTVALUEOUT4 always
RIOI.IOI_LOGIC_OUTS21_1.IOI_ODELAY0_CNTVALUEOUT4 always
RIOI.IOI_LOGIC_OUTS2_1.RIOI_OLOGIC0_TFB_LOCAL always
RIOI.IOI_LOGIC_OUTS22_1.IOI_IDELAYCTRL_RDY always
RIOI.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
RIOI.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
RIOI.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
RIOI.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
RIOI.IOI_LOGIC_OUTS4_0.IOI_ODELAY1_CNTVALUEOUT1 always
RIOI.IOI_LOGIC_OUTS4_1.IOI_ODELAY0_CNTVALUEOUT1 always
RIOI.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
RIOI.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
RIOI.IOI_LOGIC_OUTS6_0.IOI_ODELAY1_CNTVALUEOUT2 always
RIOI.IOI_LOGIC_OUTS6_1.IOI_ODELAY0_CNTVALUEOUT2 always
RIOI.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
RIOI.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
RIOI.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
RIOI.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
RIOI.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
RIOI.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
RIOI.IOI_ODELAY0_CE.IOI_IMUX2_1 always
RIOI.IOI_ODELAY0_CINVCTRL.IOI_BYP2_1 always
RIOI.IOI_ODELAY0_C.IOI_CLK1_1 always
RIOI.IOI_ODELAY0_CLKIN.IOI_OCLK_0 always
RIOI.IOI_ODELAY0_CNTVALUEIN0.IOI_IMUX23_1 always
RIOI.IOI_ODELAY0_CNTVALUEIN1.IOI_IMUX16_1 always
RIOI.IOI_ODELAY0_CNTVALUEIN2.IOI_IMUX17_1 always
RIOI.IOI_ODELAY0_CNTVALUEIN3.IOI_IMUX19_1 always
RIOI.IOI_ODELAY0_CNTVALUEIN4.IOI_IMUX18_1 always
RIOI.IOI_ODELAY0_INC.IOI_IMUX3_1 always
RIOI.IOI_ODELAY0_LD.IOI_IMUX28_1 always
RIOI.IOI_ODELAY0_LDPIPEEN.IOI_IMUX27_1 always
RIOI.IOI_ODELAY0_REGRST.IOI_IMUX11_1 always
RIOI.IOI_ODELAY1_CE.IOI_IMUX2_0 always
RIOI.IOI_ODELAY1_CINVCTRL.IOI_BYP2_0 always
RIOI.IOI_ODELAY1_C.IOI_CLK1_0 always
RIOI.IOI_ODELAY1_CLKIN.IOI_OCLK_1 always
RIOI.IOI_ODELAY1_CNTVALUEIN0.IOI_IMUX23_0 always
RIOI.IOI_ODELAY1_CNTVALUEIN1.IOI_IMUX16_0 always
RIOI.IOI_ODELAY1_CNTVALUEIN2.IOI_IMUX17_0 always
RIOI.IOI_ODELAY1_CNTVALUEIN3.IOI_IMUX19_0 always
RIOI.IOI_ODELAY1_CNTVALUEIN4.IOI_IMUX18_0 always
RIOI.IOI_ODELAY1_INC.IOI_IMUX3_0 always
RIOI.IOI_ODELAY1_LD.IOI_IMUX28_0 always
RIOI.IOI_ODELAY1_LDPIPEEN.IOI_IMUX27_0 always
RIOI.IOI_ODELAY1_REGRST.IOI_IMUX11_0 always
RIOI.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
RIOI.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
RIOI.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
RIOI.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
RIOI.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
RIOI.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
RIOI.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
RIOI.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
RIOI.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
RIOI.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
RIOI.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
RIOI.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
RIOI.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
RIOI.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
RIOI.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
RIOI.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
RIOI.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
RIOI.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
RIOI.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
RIOI.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
RIOI.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
RIOI.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
RIOI.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
RIOI.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
RIOI.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
RIOI.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
RIOI.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
RIOI.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
RIOI.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
RIOI.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
RIOI.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
RIOI.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
RIOI.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
RIOI.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
RIOI.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
RIOI.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
RIOI.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
RIOI.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
RIOI.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
RIOI.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
RIOI.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
RIOI.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
RIOI.RIOI_DCI_T_TERM0.IOI_IMUX6_1 always
RIOI.RIOI_DCI_T_TERM1.IOI_IMUX6_0 always
RIOI.RIOI_I0.RIOI_IBUF0 always
RIOI.RIOI_I1.RIOI_IBUF1 always
RIOI.RIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
RIOI.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
RIOI.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
RIOI.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
RIOI.RIOI_IDELAY0_IFDLY0.IOI_FAN4_1 always
RIOI.RIOI_IDELAY0_IFDLY1.IOI_FAN5_1 always
RIOI.RIOI_IDELAY0_IFDLY2.IOI_BYP7_1 always
RIOI.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
RIOI.RIOI_IDELAY1_IFDLY0.IOI_FAN4_0 always
RIOI.RIOI_IDELAY1_IFDLY1.IOI_FAN5_0 always
RIOI.RIOI_IDELAY1_IFDLY2.IOI_BYP7_0 always
RIOI.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
RIOI.RIOI_ILOGIC0_D.RIOI_I0 always
RIOI.RIOI_ILOGIC0_OFB.RIOI_OLOGIC0_OFB always
RIOI.RIOI_ILOGIC0_TFB.RIOI_OLOGIC0_TFB_LOCAL always
RIOI.RIOI_ILOGIC1_DDLY.RIOI_IDELAY1_DATAOUT always
RIOI.RIOI_ILOGIC1_D.RIOI_I1 always
RIOI.RIOI_ILOGIC1_OFB.RIOI_OLOGIC1_OFB always
RIOI.RIOI_ILOGIC1_TFB.RIOI_OLOGIC1_TFB_LOCAL always
RIOI.RIOI_ISIN11.RIOI_ISOUT10 always
RIOI.RIOI_ISIN21.RIOI_ISOUT20 always
RIOI.RIOI_O0.RIOI_OLOGIC0_OQ always
RIOI.RIOI_O1.RIOI_OLOGIC1_OQ always
RIOI.RIOI_ODELAY0_ODATAIN.RIOI_OLOGIC0_OFB always
RIOI.RIOI_ODELAY0_OFDLY0.IOI_BYP0_1 always
RIOI.RIOI_ODELAY0_OFDLY1.IOI_BYP1_1 always
RIOI.RIOI_ODELAY0_OFDLY2.IOI_BYP5_1 always
RIOI.RIOI_ODELAY1_ODATAIN.RIOI_OLOGIC1_OFB always
RIOI.RIOI_ODELAY1_OFDLY0.IOI_BYP0_0 always
RIOI.RIOI_ODELAY1_OFDLY1.IOI_BYP1_0 always
RIOI.RIOI_ODELAY1_OFDLY2.IOI_BYP5_0 always
RIOI.RIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
RIOI.RIOI_OLOGIC0_TFB_LOCAL.RIOI_OLOGIC0_TFB always
RIOI.RIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
RIOI.RIOI_OLOGIC1_OQ.IOI_OLOGIC1_D1 always
RIOI.RIOI_OLOGIC1_TFB_LOCAL.RIOI_OLOGIC1_TFB always
RIOI.RIOI_OLOGIC1_TQ.IOI_OLOGIC1_T1 always
RIOI.RIOI_OSIN10.RIOI_OSOUT11 always
RIOI.RIOI_OSIN20.RIOI_OSOUT21 always
RIOI.RIOI_T0.RIOI_OLOGIC0_TQ always
RIOI.RIOI_T1.RIOI_OLOGIC1_TQ always

92
kintex7/ppips_rioi_sing.db Normal file
View File

@ -0,0 +1,92 @@
RIOI_SING.IOI_IDELAY0_CE.IOI_IMUX32_0 always
RIOI_SING.IOI_IDELAY0_CINVCTRL.IOI_BYP6_0 always
RIOI_SING.IOI_IDELAY0_C.IOI_CLK1_0 always
RIOI_SING.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_0 always
RIOI_SING.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_0 always
RIOI_SING.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_0 always
RIOI_SING.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_0 always
RIOI_SING.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_0 always
RIOI_SING.IOI_IDELAY0_DATAIN.IOI_IMUX25_0 always
RIOI_SING.IOI_IDELAY0_INC.IOI_IMUX26_0 always
RIOI_SING.IOI_IDELAY0_LD.IOI_IMUX30_0 always
RIOI_SING.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_0 always
RIOI_SING.IOI_IDELAY0_REGRST.IOI_IMUX12_0 always
RIOI_SING.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_0 always
RIOI_SING.IOI_ILOGIC0_CE1.IOI_IMUX5_0 always
RIOI_SING.IOI_ILOGIC0_CE2.IOI_IMUX14_0 always
RIOI_SING.IOI_ILOGIC0_CLKDIV.IOI_CLK0_0 always
RIOI_SING.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_0 always
RIOI_SING.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_0 always
RIOI_SING.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_0 always
RIOI_SING.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
RIOI_SING.IOI_ILOGIC0_SR.IOI_CTRL1_0 always
RIOI_SING.IOI_LOGIC_OUTS0_0.IOI_ILOGIC0_Q1 always
RIOI_SING.IOI_LOGIC_OUTS10_0.IOI_ILOGIC0_Q4 always
RIOI_SING.IOI_LOGIC_OUTS1_0.IOI_IDELAY0_CNTVALUEOUT1 always
RIOI_SING.IOI_LOGIC_OUTS11_0.IOI_IDELAY0_CNTVALUEOUT4 always
RIOI_SING.IOI_LOGIC_OUTS12_0.IOI_ODELAY0_CNTVALUEOUT0 always
RIOI_SING.IOI_LOGIC_OUTS14_0.IOI_ILOGIC0_Q5 always
RIOI_SING.IOI_LOGIC_OUTS15_0.IOI_IDELAY0_CNTVALUEOUT3 always
RIOI_SING.IOI_LOGIC_OUTS17_0.IOI_ODELAY0_CNTVALUEOUT3 always
RIOI_SING.IOI_LOGIC_OUTS18_0.IOI_ILOGIC0_O always
RIOI_SING.IOI_LOGIC_OUTS19_0.IOI_IDELAY0_CNTVALUEOUT2 always
RIOI_SING.IOI_LOGIC_OUTS20_0.IOI_IDELAY0_CNTVALUEOUT0 always
RIOI_SING.IOI_LOGIC_OUTS2_0.RIOI_OLOGIC0_TFB_LOCAL always
RIOI_SING.IOI_LOGIC_OUTS21_0.IOI_ODELAY0_CNTVALUEOUT4 always
RIOI_SING.IOI_LOGIC_OUTS23_0.IOI_ILOGIC0_Q2 always
RIOI_SING.IOI_LOGIC_OUTS3_0.IOI_ILOGIC0_Q6 always
RIOI_SING.IOI_LOGIC_OUTS4_0.IOI_ODELAY0_CNTVALUEOUT1 always
RIOI_SING.IOI_LOGIC_OUTS5_0.IOI_OLOGIC0_IOCLKGLITCH always
RIOI_SING.IOI_LOGIC_OUTS6_0.IOI_ODELAY0_CNTVALUEOUT2 always
RIOI_SING.IOI_LOGIC_OUTS7_0.IOI_ILOGIC0_Q7 always
RIOI_SING.IOI_LOGIC_OUTS8_0.IOI_ILOGIC0_Q8 always
RIOI_SING.IOI_LOGIC_OUTS9_0.IOI_ILOGIC0_Q3 always
RIOI_SING.IOI_ODELAY0_CE.IOI_IMUX2_0 always
RIOI_SING.IOI_ODELAY0_CINVCTRL.IOI_BYP2_0 always
RIOI_SING.IOI_ODELAY0_C.IOI_CLK1_0 always
RIOI_SING.IOI_ODELAY0_CLKIN.IOI_OCLK_0 always
RIOI_SING.IOI_ODELAY0_CNTVALUEIN0.IOI_IMUX23_0 always
RIOI_SING.IOI_ODELAY0_CNTVALUEIN1.IOI_IMUX16_0 always
RIOI_SING.IOI_ODELAY0_CNTVALUEIN2.IOI_IMUX17_0 always
RIOI_SING.IOI_ODELAY0_CNTVALUEIN3.IOI_IMUX19_0 always
RIOI_SING.IOI_ODELAY0_CNTVALUEIN4.IOI_IMUX18_0 always
RIOI_SING.IOI_ODELAY0_INC.IOI_IMUX3_0 always
RIOI_SING.IOI_ODELAY0_LD.IOI_IMUX28_0 always
RIOI_SING.IOI_ODELAY0_LDPIPEEN.IOI_IMUX27_0 always
RIOI_SING.IOI_ODELAY0_REGRST.IOI_IMUX11_0 always
RIOI_SING.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
RIOI_SING.IOI_OLOGIC0_D1.IOI_IMUX34_0 always
RIOI_SING.IOI_OLOGIC0_D2.IOI_IMUX40_0 always
RIOI_SING.IOI_OLOGIC0_D3.IOI_IMUX44_0 always
RIOI_SING.IOI_OLOGIC0_D4.IOI_IMUX42_0 always
RIOI_SING.IOI_OLOGIC0_D5.IOI_IMUX43_0 always
RIOI_SING.IOI_OLOGIC0_D6.IOI_IMUX45_0 always
RIOI_SING.IOI_OLOGIC0_D7.IOI_IMUX46_0 always
RIOI_SING.IOI_OLOGIC0_D8.IOI_IMUX47_0 always
RIOI_SING.IOI_OLOGIC0_OCE.IOI_IMUX29_0 always
RIOI_SING.IOI_OLOGIC0_SR.IOI_CTRL0_0 always
RIOI_SING.IOI_OLOGIC0_T1.IOI_IMUX15_0 always
RIOI_SING.IOI_OLOGIC0_T2.IOI_IMUX7_0 always
RIOI_SING.IOI_OLOGIC0_T3.IOI_IMUX13_0 always
RIOI_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
RIOI_SING.IOI_OLOGIC0_TBYTEIN.IOI_SING_TBYTEIN always
RIOI_SING.IOI_OLOGIC0_TCE.IOI_IMUX1_0 always
RIOI_SING.RIOI_DCI_T_TERM0.IOI_IMUX6_0 always
RIOI_SING.RIOI_I0.RIOI_IBUF0 always
RIOI_SING.RIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
RIOI_SING.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
RIOI_SING.RIOI_IDELAY0_IFDLY0.IOI_FAN4_0 always
RIOI_SING.RIOI_IDELAY0_IFDLY1.IOI_FAN5_0 always
RIOI_SING.RIOI_IDELAY0_IFDLY2.IOI_BYP7_0 always
RIOI_SING.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
RIOI_SING.RIOI_ILOGIC0_D.RIOI_I0 always
RIOI_SING.RIOI_ILOGIC0_OFB.RIOI_OLOGIC0_OFB always
RIOI_SING.RIOI_ILOGIC0_TFB.RIOI_OLOGIC0_TFB_LOCAL always
RIOI_SING.RIOI_ODELAY0_ODATAIN.RIOI_OLOGIC0_OFB always
RIOI_SING.RIOI_ODELAY0_OFDLY0.IOI_BYP0_0 always
RIOI_SING.RIOI_ODELAY0_OFDLY1.IOI_BYP1_0 always
RIOI_SING.RIOI_ODELAY0_OFDLY2.IOI_BYP5_0 always
RIOI_SING.RIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
RIOI_SING.RIOI_OLOGIC0_TFB_LOCAL.RIOI_OLOGIC0_TFB always
RIOI_SING.RIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
RIOI_SING.RIOI_T0.RIOI_OLOGIC0_TQ always

200
kintex7/ppips_rioi_tbytesrc.db Normal file
View File

@ -0,0 +1,200 @@
RIOI_TBYTESRC.IOI_IDELAY0_CE.IOI_IMUX32_1 always
RIOI_TBYTESRC.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
RIOI_TBYTESRC.IOI_IDELAY0_C.IOI_CLK1_1 always
RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
RIOI_TBYTESRC.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
RIOI_TBYTESRC.IOI_IDELAY0_INC.IOI_IMUX26_1 always
RIOI_TBYTESRC.IOI_IDELAY0_LD.IOI_IMUX30_1 always
RIOI_TBYTESRC.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
RIOI_TBYTESRC.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
RIOI_TBYTESRC.IOI_IDELAY1_CE.IOI_IMUX32_0 always
RIOI_TBYTESRC.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
RIOI_TBYTESRC.IOI_IDELAY1_C.IOI_CLK1_0 always
RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
RIOI_TBYTESRC.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
RIOI_TBYTESRC.IOI_IDELAY1_INC.IOI_IMUX26_0 always
RIOI_TBYTESRC.IOI_IDELAY1_LD.IOI_IMUX30_0 always
RIOI_TBYTESRC.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
RIOI_TBYTESRC.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
RIOI_TBYTESRC.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
RIOI_TBYTESRC.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
RIOI_TBYTESRC.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
RIOI_TBYTESRC.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
RIOI_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
RIOI_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
RIOI_TBYTESRC.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
RIOI_TBYTESRC.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
RIOI_TBYTESRC.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
RIOI_TBYTESRC.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
RIOI_TBYTESRC.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
RIOI_TBYTESRC.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
RIOI_TBYTESRC.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
RIOI_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
RIOI_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
RIOI_TBYTESRC.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
RIOI_TBYTESRC.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
RIOI_TBYTESRC.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS12_0.IOI_ODELAY1_CNTVALUEOUT0 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS12_1.IOI_ODELAY0_CNTVALUEOUT0 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS15_1.IOI_IDELAY0_CNTVALUEOUT3 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS17_0.IOI_ODELAY1_CNTVALUEOUT3 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS17_1.IOI_ODELAY0_CNTVALUEOUT3 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS18_0.IOI_ILOGIC1_O always
RIOI_TBYTESRC.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O always
RIOI_TBYTESRC.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS2_0.RIOI_OLOGIC1_TFB_LOCAL always
RIOI_TBYTESRC.IOI_LOGIC_OUTS21_0.IOI_ODELAY1_CNTVALUEOUT4 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS21_1.IOI_ODELAY0_CNTVALUEOUT4 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS2_1.RIOI_OLOGIC0_TFB_LOCAL always
RIOI_TBYTESRC.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS4_0.IOI_ODELAY1_CNTVALUEOUT1 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS4_1.IOI_ODELAY0_CNTVALUEOUT1 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
RIOI_TBYTESRC.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
RIOI_TBYTESRC.IOI_LOGIC_OUTS6_0.IOI_ODELAY1_CNTVALUEOUT2 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS6_1.IOI_ODELAY0_CNTVALUEOUT2 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
RIOI_TBYTESRC.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
RIOI_TBYTESRC.IOI_ODELAY0_CE.IOI_IMUX2_1 always
RIOI_TBYTESRC.IOI_ODELAY0_CINVCTRL.IOI_BYP2_1 always
RIOI_TBYTESRC.IOI_ODELAY0_C.IOI_CLK1_1 always
RIOI_TBYTESRC.IOI_ODELAY0_CLKIN.IOI_OCLK_0 always
RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEIN0.IOI_IMUX23_1 always
RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEIN1.IOI_IMUX16_1 always
RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEIN2.IOI_IMUX17_1 always
RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEIN3.IOI_IMUX19_1 always
RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEIN4.IOI_IMUX18_1 always
RIOI_TBYTESRC.IOI_ODELAY0_INC.IOI_IMUX3_1 always
RIOI_TBYTESRC.IOI_ODELAY0_LD.IOI_IMUX28_1 always
RIOI_TBYTESRC.IOI_ODELAY0_LDPIPEEN.IOI_IMUX27_1 always
RIOI_TBYTESRC.IOI_ODELAY0_REGRST.IOI_IMUX11_1 always
RIOI_TBYTESRC.IOI_ODELAY1_CE.IOI_IMUX2_0 always
RIOI_TBYTESRC.IOI_ODELAY1_CINVCTRL.IOI_BYP2_0 always
RIOI_TBYTESRC.IOI_ODELAY1_C.IOI_CLK1_0 always
RIOI_TBYTESRC.IOI_ODELAY1_CLKIN.IOI_OCLK_1 always
RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEIN0.IOI_IMUX23_0 always
RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEIN1.IOI_IMUX16_0 always
RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEIN2.IOI_IMUX17_0 always
RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEIN3.IOI_IMUX19_0 always
RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEIN4.IOI_IMUX18_0 always
RIOI_TBYTESRC.IOI_ODELAY1_INC.IOI_IMUX3_0 always
RIOI_TBYTESRC.IOI_ODELAY1_LD.IOI_IMUX28_0 always
RIOI_TBYTESRC.IOI_ODELAY1_LDPIPEEN.IOI_IMUX27_0 always
RIOI_TBYTESRC.IOI_ODELAY1_REGRST.IOI_IMUX11_0 always
RIOI_TBYTESRC.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
RIOI_TBYTESRC.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
RIOI_TBYTESRC.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
RIOI_TBYTESRC.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
RIOI_TBYTESRC.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
RIOI_TBYTESRC.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
RIOI_TBYTESRC.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
RIOI_TBYTESRC.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
RIOI_TBYTESRC.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
RIOI_TBYTESRC.IOI_TBYTEIN.IOI_OLOGIC1_TBYTEOUT always
RIOI_TBYTESRC.RIOI_DCI_T_TERM0.IOI_IMUX6_1 always
RIOI_TBYTESRC.RIOI_DCI_T_TERM1.IOI_IMUX6_0 always
RIOI_TBYTESRC.RIOI_I0.RIOI_IBUF0 always
RIOI_TBYTESRC.RIOI_I1.RIOI_IBUF1 always
RIOI_TBYTESRC.RIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
RIOI_TBYTESRC.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
RIOI_TBYTESRC.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
RIOI_TBYTESRC.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
RIOI_TBYTESRC.RIOI_IDELAY0_IFDLY0.IOI_FAN4_1 always
RIOI_TBYTESRC.RIOI_IDELAY0_IFDLY1.IOI_FAN5_1 always
RIOI_TBYTESRC.RIOI_IDELAY0_IFDLY2.IOI_BYP7_1 always
RIOI_TBYTESRC.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
RIOI_TBYTESRC.RIOI_IDELAY1_IFDLY0.IOI_FAN4_0 always
RIOI_TBYTESRC.RIOI_IDELAY1_IFDLY1.IOI_FAN5_0 always
RIOI_TBYTESRC.RIOI_IDELAY1_IFDLY2.IOI_BYP7_0 always
RIOI_TBYTESRC.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
RIOI_TBYTESRC.RIOI_ILOGIC0_D.RIOI_I0 always
RIOI_TBYTESRC.RIOI_ILOGIC0_OFB.RIOI_OLOGIC0_OFB always
RIOI_TBYTESRC.RIOI_ILOGIC0_TFB.RIOI_OLOGIC0_TFB_LOCAL always
RIOI_TBYTESRC.RIOI_ILOGIC1_DDLY.RIOI_IDELAY1_DATAOUT always
RIOI_TBYTESRC.RIOI_ILOGIC1_D.RIOI_I1 always
RIOI_TBYTESRC.RIOI_ILOGIC1_OFB.RIOI_OLOGIC1_OFB always
RIOI_TBYTESRC.RIOI_ILOGIC1_TFB.RIOI_OLOGIC1_TFB_LOCAL always
RIOI_TBYTESRC.RIOI_ISIN11.RIOI_ISOUT10 always
RIOI_TBYTESRC.RIOI_ISIN21.RIOI_ISOUT20 always
RIOI_TBYTESRC.RIOI_O0.RIOI_OLOGIC0_OQ always
RIOI_TBYTESRC.RIOI_O1.RIOI_OLOGIC1_OQ always
RIOI_TBYTESRC.RIOI_ODELAY0_ODATAIN.RIOI_OLOGIC0_OFB always
RIOI_TBYTESRC.RIOI_ODELAY0_OFDLY0.IOI_BYP0_1 always
RIOI_TBYTESRC.RIOI_ODELAY0_OFDLY1.IOI_BYP1_1 always
RIOI_TBYTESRC.RIOI_ODELAY0_OFDLY2.IOI_BYP5_1 always
RIOI_TBYTESRC.RIOI_ODELAY1_ODATAIN.RIOI_OLOGIC1_OFB always
RIOI_TBYTESRC.RIOI_ODELAY1_OFDLY0.IOI_BYP0_0 always
RIOI_TBYTESRC.RIOI_ODELAY1_OFDLY1.IOI_BYP1_0 always
RIOI_TBYTESRC.RIOI_ODELAY1_OFDLY2.IOI_BYP5_0 always
RIOI_TBYTESRC.RIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
RIOI_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL.RIOI_OLOGIC0_TFB always
RIOI_TBYTESRC.RIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
RIOI_TBYTESRC.RIOI_OLOGIC1_OQ.IOI_OLOGIC1_D1 always
RIOI_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL.RIOI_OLOGIC1_TFB always
RIOI_TBYTESRC.RIOI_OLOGIC1_TQ.IOI_OLOGIC1_T1 always
RIOI_TBYTESRC.RIOI_OSIN10.RIOI_OSOUT11 always
RIOI_TBYTESRC.RIOI_OSIN20.RIOI_OSOUT21 always
RIOI_TBYTESRC.RIOI_T0.RIOI_OLOGIC0_TQ always
RIOI_TBYTESRC.RIOI_T1.RIOI_OLOGIC1_TQ always

198
kintex7/ppips_rioi_tbyteterm.db Normal file
View File

@ -0,0 +1,198 @@
RIOI_TBYTETERM.IOI_IDELAY0_CE.IOI_IMUX32_1 always
RIOI_TBYTETERM.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
RIOI_TBYTETERM.IOI_IDELAY0_C.IOI_CLK1_1 always
RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
RIOI_TBYTETERM.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
RIOI_TBYTETERM.IOI_IDELAY0_INC.IOI_IMUX26_1 always
RIOI_TBYTETERM.IOI_IDELAY0_LD.IOI_IMUX30_1 always
RIOI_TBYTETERM.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
RIOI_TBYTETERM.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
RIOI_TBYTETERM.IOI_IDELAY1_CE.IOI_IMUX32_0 always
RIOI_TBYTETERM.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
RIOI_TBYTETERM.IOI_IDELAY1_C.IOI_CLK1_0 always
RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
RIOI_TBYTETERM.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
RIOI_TBYTETERM.IOI_IDELAY1_INC.IOI_IMUX26_0 always
RIOI_TBYTETERM.IOI_IDELAY1_LD.IOI_IMUX30_0 always
RIOI_TBYTETERM.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
RIOI_TBYTETERM.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
RIOI_TBYTETERM.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
RIOI_TBYTETERM.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
RIOI_TBYTETERM.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
RIOI_TBYTETERM.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
RIOI_TBYTETERM.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
RIOI_TBYTETERM.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
RIOI_TBYTETERM.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
RIOI_TBYTETERM.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
RIOI_TBYTETERM.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
RIOI_TBYTETERM.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
RIOI_TBYTETERM.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
RIOI_TBYTETERM.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
RIOI_TBYTETERM.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
RIOI_TBYTETERM.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
RIOI_TBYTETERM.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
RIOI_TBYTETERM.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
RIOI_TBYTETERM.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
RIOI_TBYTETERM.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS12_0.IOI_ODELAY1_CNTVALUEOUT0 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS12_1.IOI_ODELAY0_CNTVALUEOUT0 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS15_1.IOI_IDELAY0_CNTVALUEOUT3 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS17_0.IOI_ODELAY1_CNTVALUEOUT3 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS17_1.IOI_ODELAY0_CNTVALUEOUT3 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS18_0.IOI_ILOGIC1_O always
RIOI_TBYTETERM.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O always
RIOI_TBYTETERM.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS2_0.RIOI_OLOGIC1_TFB_LOCAL always
RIOI_TBYTETERM.IOI_LOGIC_OUTS21_0.IOI_ODELAY1_CNTVALUEOUT4 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS21_1.IOI_ODELAY0_CNTVALUEOUT4 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS2_1.RIOI_OLOGIC0_TFB_LOCAL always
RIOI_TBYTETERM.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS4_0.IOI_ODELAY1_CNTVALUEOUT1 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS4_1.IOI_ODELAY0_CNTVALUEOUT1 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
RIOI_TBYTETERM.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
RIOI_TBYTETERM.IOI_LOGIC_OUTS6_0.IOI_ODELAY1_CNTVALUEOUT2 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS6_1.IOI_ODELAY0_CNTVALUEOUT2 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
RIOI_TBYTETERM.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
RIOI_TBYTETERM.IOI_ODELAY0_CE.IOI_IMUX2_1 always
RIOI_TBYTETERM.IOI_ODELAY0_CINVCTRL.IOI_BYP2_1 always
RIOI_TBYTETERM.IOI_ODELAY0_C.IOI_CLK1_1 always
RIOI_TBYTETERM.IOI_ODELAY0_CLKIN.IOI_OCLK_0 always
RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEIN0.IOI_IMUX23_1 always
RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEIN1.IOI_IMUX16_1 always
RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEIN2.IOI_IMUX17_1 always
RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEIN3.IOI_IMUX19_1 always
RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEIN4.IOI_IMUX18_1 always
RIOI_TBYTETERM.IOI_ODELAY0_INC.IOI_IMUX3_1 always
RIOI_TBYTETERM.IOI_ODELAY0_LD.IOI_IMUX28_1 always
RIOI_TBYTETERM.IOI_ODELAY0_LDPIPEEN.IOI_IMUX27_1 always
RIOI_TBYTETERM.IOI_ODELAY0_REGRST.IOI_IMUX11_1 always
RIOI_TBYTETERM.IOI_ODELAY1_CE.IOI_IMUX2_0 always
RIOI_TBYTETERM.IOI_ODELAY1_CINVCTRL.IOI_BYP2_0 always
RIOI_TBYTETERM.IOI_ODELAY1_C.IOI_CLK1_0 always
RIOI_TBYTETERM.IOI_ODELAY1_CLKIN.IOI_OCLK_1 always
RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEIN0.IOI_IMUX23_0 always
RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEIN1.IOI_IMUX16_0 always
RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEIN2.IOI_IMUX17_0 always
RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEIN3.IOI_IMUX19_0 always
RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEIN4.IOI_IMUX18_0 always
RIOI_TBYTETERM.IOI_ODELAY1_INC.IOI_IMUX3_0 always
RIOI_TBYTETERM.IOI_ODELAY1_LD.IOI_IMUX28_0 always
RIOI_TBYTETERM.IOI_ODELAY1_LDPIPEEN.IOI_IMUX27_0 always
RIOI_TBYTETERM.IOI_ODELAY1_REGRST.IOI_IMUX11_0 always
RIOI_TBYTETERM.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
RIOI_TBYTETERM.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
RIOI_TBYTETERM.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN_TERM always
RIOI_TBYTETERM.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
RIOI_TBYTETERM.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
RIOI_TBYTETERM.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
RIOI_TBYTETERM.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN_TERM always
RIOI_TBYTETERM.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
RIOI_TBYTETERM.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
RIOI_TBYTETERM.RIOI_DCI_T_TERM0.IOI_IMUX6_1 always
RIOI_TBYTETERM.RIOI_DCI_T_TERM1.IOI_IMUX6_0 always
RIOI_TBYTETERM.RIOI_I0.RIOI_IBUF0 always
RIOI_TBYTETERM.RIOI_I1.RIOI_IBUF1 always
RIOI_TBYTETERM.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
RIOI_TBYTETERM.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
RIOI_TBYTETERM.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
RIOI_TBYTETERM.RIOI_IDELAY0_IFDLY0.IOI_FAN4_1 always
RIOI_TBYTETERM.RIOI_IDELAY0_IFDLY1.IOI_FAN5_1 always
RIOI_TBYTETERM.RIOI_IDELAY0_IFDLY2.IOI_BYP7_1 always
RIOI_TBYTETERM.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
RIOI_TBYTETERM.RIOI_IDELAY1_IFDLY0.IOI_FAN4_0 always
RIOI_TBYTETERM.RIOI_IDELAY1_IFDLY1.IOI_FAN5_0 always
RIOI_TBYTETERM.RIOI_IDELAY1_IFDLY2.IOI_BYP7_0 always
RIOI_TBYTETERM.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
RIOI_TBYTETERM.RIOI_ILOGIC0_D.RIOI_I0 always
RIOI_TBYTETERM.RIOI_ILOGIC0_OFB.RIOI_OLOGIC0_OFB always
RIOI_TBYTETERM.RIOI_ILOGIC0_TFB.RIOI_OLOGIC0_TFB_LOCAL always
RIOI_TBYTETERM.RIOI_ILOGIC1_DDLY.RIOI_IDELAY1_DATAOUT always
RIOI_TBYTETERM.RIOI_ILOGIC1_D.RIOI_I1 always
RIOI_TBYTETERM.RIOI_ILOGIC1_OFB.RIOI_OLOGIC1_OFB always
RIOI_TBYTETERM.RIOI_ILOGIC1_TFB.RIOI_OLOGIC1_TFB_LOCAL always
RIOI_TBYTETERM.RIOI_ISIN11.RIOI_ISOUT10 always
RIOI_TBYTETERM.RIOI_ISIN21.RIOI_ISOUT20 always
RIOI_TBYTETERM.RIOI_O0.RIOI_OLOGIC0_OQ always
RIOI_TBYTETERM.RIOI_O1.RIOI_OLOGIC1_OQ always
RIOI_TBYTETERM.RIOI_ODELAY0_ODATAIN.RIOI_OLOGIC0_OFB always
RIOI_TBYTETERM.RIOI_ODELAY0_OFDLY0.IOI_BYP0_1 always
RIOI_TBYTETERM.RIOI_ODELAY0_OFDLY1.IOI_BYP1_1 always
RIOI_TBYTETERM.RIOI_ODELAY0_OFDLY2.IOI_BYP5_1 always
RIOI_TBYTETERM.RIOI_ODELAY1_ODATAIN.RIOI_OLOGIC1_OFB always
RIOI_TBYTETERM.RIOI_ODELAY1_OFDLY0.IOI_BYP0_0 always
RIOI_TBYTETERM.RIOI_ODELAY1_OFDLY1.IOI_BYP1_0 always
RIOI_TBYTETERM.RIOI_ODELAY1_OFDLY2.IOI_BYP5_0 always
RIOI_TBYTETERM.RIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
RIOI_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL.RIOI_OLOGIC0_TFB always
RIOI_TBYTETERM.RIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
RIOI_TBYTETERM.RIOI_OLOGIC1_OQ.IOI_OLOGIC1_D1 always
RIOI_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL.RIOI_OLOGIC1_TFB always
RIOI_TBYTETERM.RIOI_OLOGIC1_TQ.IOI_OLOGIC1_T1 always
RIOI_TBYTETERM.RIOI_OSIN10.RIOI_OSOUT11 always
RIOI_TBYTETERM.RIOI_OSIN20.RIOI_OSOUT21 always
RIOI_TBYTETERM.RIOI_T0.RIOI_OLOGIC0_TQ always
RIOI_TBYTETERM.RIOI_T1.RIOI_OLOGIC1_TQ always

18432
kintex7/segbits_bram_l.block_ram.db
View File

File diff suppressed because it is too large Load Diff

18432
kintex7/segbits_bram_l.block_ram.origin_info.db
View File

File diff suppressed because it is too large Load Diff

324
kintex7/segbits_bram_l.db
View File

@ -1,6 +1,21 @@
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 26_32 !26_33 26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 26_32 26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0 !26_32 !26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 26_48 !26_49 26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 26_48 26_49 !26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1 !26_48 !26_49 !26_51
@ -28,24 +43,24 @@ BRAM_L.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8 !26_80 !26_81 !26_83
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 26_208 !26_209 26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 26_208 26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9 !26_208 !26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 26_37 !26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 !26_37 26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0 !26_37 !26_38 !26_39
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 26_53 !26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 !26_53 26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1 !26_53 !26_54 !26_55
@ -73,24 +88,24 @@ BRAM_L.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 !26_85 !26_86 !26_87
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 26_213 !26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 !26_213 26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 !26_213 !26_214 !26_215
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_40 !26_41 26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 26_40 26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_IMUX_ADDRBWRADDRL0 !26_40 !26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_56 !26_57 26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 26_56 26_57 !26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_IMUX_ADDRBWRADDRL1 !26_56 !26_57 !26_59
@ -118,24 +133,24 @@ BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 !26_88 !26_89 !26_91
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_216 !26_217 26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 26_216 26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_IMUX_ADDRBWRADDRL9 !26_216 !26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_45 !26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 !26_45 26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_IMUX_ADDRBWRADDRU0 !26_45 !26_46 !26_47
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_61 !26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 !26_61 26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_IMUX_ADDRBWRADDRU1 !26_61 !26_62 !26_63
@ -163,51 +178,10 @@ BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 !26_93 !26_94 !26_95
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_221 !26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 !26_221 26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 !26_221 !26_222 !26_223
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_L.CASCOUT_ARD_ACTIVE 26_170
BRAM_L.CASCOUT_BWR_ACTIVE 26_172
BRAM_L.EN_SYN 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH 27_170
BRAM_L.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_L.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_L.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_L.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] 27_13
BRAM_L.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_L.RAMB18_Y0.DOA_REG 27_69
BRAM_L.RAMB18_Y0.DOB_REG 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE 27_150
@ -215,15 +189,15 @@ BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
@ -235,17 +209,25 @@ BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_L.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_L.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_L.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_L.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_L.RAMB18_Y0.ZINIT_A[4] 27_105
@ -254,16 +236,16 @@ BRAM_L.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_L.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_L.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_L.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_L.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_L.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_L.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_L.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_L.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_L.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_L.RAMB18_Y0.ZINIT_B[4] 27_111
@ -272,14 +254,6 @@ BRAM_L.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_L.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_L.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_L.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_L.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -291,7 +265,15 @@ BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.ZSRVAL_A[4] 27_106
@ -300,16 +282,16 @@ BRAM_L.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.ZSRVAL_B[4] 27_110
@ -318,14 +300,6 @@ BRAM_L.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_L.RAMB18_Y1.DOA_REG 27_251
BRAM_L.RAMB18_Y1.DOB_REG 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE 27_169
@ -333,15 +307,15 @@ BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
@ -353,17 +327,25 @@ BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_L.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_L.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_L.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_L.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_L.RAMB18_Y1.ZINIT_A[4] 27_281
@ -372,16 +354,16 @@ BRAM_L.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_L.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_L.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_L.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_L.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_L.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_L.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_L.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_L.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_L.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_L.RAMB18_Y1.ZINIT_B[4] 27_287
@ -390,14 +372,6 @@ BRAM_L.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_L.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_L.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_L.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_L.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -409,7 +383,15 @@ BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_L.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.ZSRVAL_A[4] 27_282
@ -418,16 +400,16 @@ BRAM_L.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.ZSRVAL_B[4] 27_286
@ -436,21 +418,39 @@ BRAM_L.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_L.RAMB36.BRAM36_READ_WIDTH_A_1 27_184
BRAM_L.RAMB36.BRAM36_READ_WIDTH_B_1 27_181
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_A_1 27_180
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_B_1 27_179
BRAM_L.RAMB36.EN_ECC_READ 27_175
BRAM_L.RAMB36.EN_ECC_WRITE 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
BRAM_L.RAMB36.BRAM36_READ_WIDTH_A_1 27_184
BRAM_L.RAMB36.BRAM36_READ_WIDTH_B_1 27_181
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_A_1 27_180
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_B_1 27_179
BRAM_L.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_L.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_L.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_L.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_L.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] 27_13

324
kintex7/segbits_bram_l.origin_info.db
View File

@ -1,6 +1,21 @@
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_33 26_32 26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_35 26_32 26_33
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0 origin:060-bram-cascades !26_32 !26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_113 26_112 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_115 26_112 26_113
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 origin:060-bram-cascades !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_241 26_240 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_243 26_240 26_241
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 origin:060-bram-cascades !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_129 26_128 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_131 26_128 26_129
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 origin:060-bram-cascades !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_257 26_256 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_49 26_48 26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_51 26_48 26_49
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1 origin:060-bram-cascades !26_48 !26_49 !26_51
@ -28,24 +43,24 @@ BRAM_L.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8 origin:060-bram-cascades !26_8
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_209 26_208 26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_211 26_208 26_209
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9 origin:060-bram-cascades !26_208 !26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_113 26_112 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_115 26_112 26_113
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 origin:060-bram-cascades !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_241 26_240 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_243 26_240 26_241
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 origin:060-bram-cascades !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_129 26_128 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_131 26_128 26_129
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 origin:060-bram-cascades !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_257 26_256 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_38 26_37 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_37 26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0 origin:060-bram-cascades !26_37 !26_38 !26_39
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_150 26_149 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 origin:060-bram-cascades !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_118 26_117 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 origin:060-bram-cascades !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_54 26_53 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_53 26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1 origin:060-bram-cascades !26_53 !26_54 !26_55
@ -73,24 +88,24 @@ BRAM_L.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 origin:060-bram-cascades !26_8
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_214 26_213 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_213 26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 origin:060-bram-cascades !26_213 !26_214 !26_215
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_150 26_149 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 origin:060-bram-cascades !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_118 26_117 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 origin:060-bram-cascades !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_41 26_40 26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_43 26_40 26_41
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_IMUX_ADDRBWRADDRL0 origin:060-bram-cascades !26_40 !26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_57 26_56 26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_59 26_56 26_57
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_IMUX_ADDRBWRADDRL1 origin:060-bram-cascades !26_56 !26_57 !26_59
@ -118,24 +133,24 @@ BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 origin:060-bram-cascades !26_8
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_217 26_216 26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_219 26_216 26_217
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_IMUX_ADDRBWRADDRL9 origin:060-bram-cascades !26_216 !26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_46 26_45 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_IMUX_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 !26_46 !26_47
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_62 26_61 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_IMUX_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 !26_62 !26_63
@ -163,67 +178,26 @@ BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 origin:060-bram-cascades !26_9
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_222 26_221 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 !26_222 !26_223
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271
BRAM_L.CASCOUT_ARD_ACTIVE origin:060-bram-cascades 26_170
BRAM_L.CASCOUT_BWR_ACTIVE origin:060-bram-cascades 26_172
BRAM_L.EN_SYN origin:028-fifo-config 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH origin:028-fifo-config 27_170
BRAM_L.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307
BRAM_L.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312
BRAM_L.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32
BRAM_L.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13
BRAM_L.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08
BRAM_L.RAMB18_Y0.DOA_REG origin:025-bram-config 27_69
BRAM_L.RAMB18_Y0.DOB_REG origin:025-bram-config 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE origin:029-bram-fifo-config 27_150
BRAM_L.RAMB18_Y0.IN_USE origin:029-bram-fifo-config 27_100 27_99
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 origin:025-bram-config !27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 origin:025-bram-config !27_36 !27_37 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 origin:025-bram-config !27_35 !27_37 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 origin:025-bram-config !27_37 27_35 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 origin:025-bram-config !27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 origin:025-bram-config !27_44 !27_45 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 origin:025-bram-config !27_43 !27_45 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 origin:025-bram-config !27_45 27_43 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_125
@ -234,17 +208,25 @@ BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 origin:025-bram-config !27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 origin:025-bram-config !27_52 !27_53 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 origin:025-bram-config !27_51 !27_53 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 origin:025-bram-config !27_53 27_51 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 origin:025-bram-config !27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 origin:025-bram-config !27_60 !27_61 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 origin:025-bram-config !27_59 !27_61 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 origin:025-bram-config !27_61 27_59 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.ZINIT_A[0] origin:025-bram-config 27_73
BRAM_L.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01
BRAM_L.RAMB18_Y0.ZINIT_A[1] origin:025-bram-config 27_65
BRAM_L.RAMB18_Y0.ZINIT_A[2] origin:025-bram-config 27_137
BRAM_L.RAMB18_Y0.ZINIT_A[3] origin:025-bram-config 27_121
@ -254,15 +236,15 @@ BRAM_L.RAMB18_Y0.ZINIT_A[6] origin:025-bram-config 27_57
BRAM_L.RAMB18_Y0.ZINIT_A[7] origin:025-bram-config 27_41
BRAM_L.RAMB18_Y0.ZINIT_A[8] origin:025-bram-config 27_25
BRAM_L.RAMB18_Y0.ZINIT_A[9] origin:025-bram-config 27_09
BRAM_L.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01
BRAM_L.RAMB18_Y0.ZINIT_B[0] origin:025-bram-config 27_79
BRAM_L.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07
BRAM_L.RAMB18_Y0.ZINIT_B[1] origin:025-bram-config 27_71
BRAM_L.RAMB18_Y0.ZINIT_B[2] origin:025-bram-config 27_143
BRAM_L.RAMB18_Y0.ZINIT_B[3] origin:025-bram-config 27_127
@ -272,14 +254,6 @@ BRAM_L.RAMB18_Y0.ZINIT_B[6] origin:025-bram-config 27_63
BRAM_L.RAMB18_Y0.ZINIT_B[7] origin:025-bram-config 27_47
BRAM_L.RAMB18_Y0.ZINIT_B[8] origin:025-bram-config 27_31
BRAM_L.RAMB18_Y0.ZINIT_B[9] origin:025-bram-config 27_15
BRAM_L.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK origin:025-bram-config 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK origin:025-bram-config 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN origin:025-bram-config 27_112
@ -291,6 +265,14 @@ BRAM_L.RAMB18_Y0.ZINV_RSTRAMB origin:025-bram-config 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG origin:025-bram-config 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB origin:025-bram-config 27_123
BRAM_L.RAMB18_Y0.ZSRVAL_A[0] origin:025-bram-config 27_74
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_A[1] origin:025-bram-config 27_66
BRAM_L.RAMB18_Y0.ZSRVAL_A[2] origin:025-bram-config 27_138
BRAM_L.RAMB18_Y0.ZSRVAL_A[3] origin:025-bram-config 27_122
@ -300,15 +282,15 @@ BRAM_L.RAMB18_Y0.ZSRVAL_A[6] origin:025-bram-config 27_58
BRAM_L.RAMB18_Y0.ZSRVAL_A[7] origin:025-bram-config 27_42
BRAM_L.RAMB18_Y0.ZSRVAL_A[8] origin:025-bram-config 27_26
BRAM_L.RAMB18_Y0.ZSRVAL_A[9] origin:025-bram-config 27_10
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_B[0] origin:025-bram-config 27_78
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06
BRAM_L.RAMB18_Y0.ZSRVAL_B[1] origin:025-bram-config 27_70
BRAM_L.RAMB18_Y0.ZSRVAL_B[2] origin:025-bram-config 27_142
BRAM_L.RAMB18_Y0.ZSRVAL_B[3] origin:025-bram-config 27_126
@ -318,30 +300,22 @@ BRAM_L.RAMB18_Y0.ZSRVAL_B[6] origin:025-bram-config 27_62
BRAM_L.RAMB18_Y0.ZSRVAL_B[7] origin:025-bram-config 27_46
BRAM_L.RAMB18_Y0.ZSRVAL_B[8] origin:025-bram-config 27_30
BRAM_L.RAMB18_Y0.ZSRVAL_B[9] origin:025-bram-config 27_14
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06
BRAM_L.RAMB18_Y1.DOA_REG origin:025-bram-config 27_251
BRAM_L.RAMB18_Y1.DOB_REG origin:025-bram-config 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE origin:029-bram-fifo-config 27_169
BRAM_L.RAMB18_Y1.IN_USE origin:029-bram-fifo-config 27_220 27_221
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 origin:025-bram-config !27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 origin:025-bram-config !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 origin:025-bram-config !27_283 !27_285 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 origin:025-bram-config !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275
BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 origin:025-bram-config !27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 origin:025-bram-config !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 origin:025-bram-config !27_275 !27_277 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 origin:025-bram-config !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_195
@ -352,17 +326,25 @@ BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 origin:025-bram-config !27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 origin:025-bram-config !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 origin:025-bram-config !27_267 !27_269 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 origin:025-bram-config !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 origin:025-bram-config !27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 origin:025-bram-config !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 origin:025-bram-config !27_259 !27_261 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 origin:025-bram-config !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259
BRAM_L.RAMB18_Y1.ZINIT_A[0] origin:025-bram-config 27_249
BRAM_L.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177
BRAM_L.RAMB18_Y1.ZINIT_A[1] origin:025-bram-config 27_241
BRAM_L.RAMB18_Y1.ZINIT_A[2] origin:025-bram-config 27_313
BRAM_L.RAMB18_Y1.ZINIT_A[3] origin:025-bram-config 27_297
@ -372,15 +354,15 @@ BRAM_L.RAMB18_Y1.ZINIT_A[6] origin:025-bram-config 27_233
BRAM_L.RAMB18_Y1.ZINIT_A[7] origin:025-bram-config 27_217
BRAM_L.RAMB18_Y1.ZINIT_A[8] origin:025-bram-config 27_201
BRAM_L.RAMB18_Y1.ZINIT_A[9] origin:025-bram-config 27_185
BRAM_L.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177
BRAM_L.RAMB18_Y1.ZINIT_B[0] origin:025-bram-config 27_255
BRAM_L.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183
BRAM_L.RAMB18_Y1.ZINIT_B[1] origin:025-bram-config 27_247
BRAM_L.RAMB18_Y1.ZINIT_B[2] origin:025-bram-config 27_319
BRAM_L.RAMB18_Y1.ZINIT_B[3] origin:025-bram-config 27_303
@ -390,14 +372,6 @@ BRAM_L.RAMB18_Y1.ZINIT_B[6] origin:025-bram-config 27_239
BRAM_L.RAMB18_Y1.ZINIT_B[7] origin:025-bram-config 27_223
BRAM_L.RAMB18_Y1.ZINIT_B[8] origin:025-bram-config 27_207
BRAM_L.RAMB18_Y1.ZINIT_B[9] origin:025-bram-config 27_191
BRAM_L.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK origin:025-bram-config 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK origin:025-bram-config 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN origin:025-bram-config 27_208
@ -409,6 +383,14 @@ BRAM_L.RAMB18_Y1.ZINV_RSTRAMB origin:025-bram-config 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG origin:025-bram-config 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB origin:025-bram-config 27_197
BRAM_L.RAMB18_Y1.ZSRVAL_A[0] origin:025-bram-config 27_250
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_A[1] origin:025-bram-config 27_242
BRAM_L.RAMB18_Y1.ZSRVAL_A[2] origin:025-bram-config 27_314
BRAM_L.RAMB18_Y1.ZSRVAL_A[3] origin:025-bram-config 27_298
@ -418,15 +400,15 @@ BRAM_L.RAMB18_Y1.ZSRVAL_A[6] origin:025-bram-config 27_234
BRAM_L.RAMB18_Y1.ZSRVAL_A[7] origin:025-bram-config 27_218
BRAM_L.RAMB18_Y1.ZSRVAL_A[8] origin:025-bram-config 27_202
BRAM_L.RAMB18_Y1.ZSRVAL_A[9] origin:025-bram-config 27_186
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_B[0] origin:025-bram-config 27_254
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182
BRAM_L.RAMB18_Y1.ZSRVAL_B[1] origin:025-bram-config 27_246
BRAM_L.RAMB18_Y1.ZSRVAL_B[2] origin:025-bram-config 27_318
BRAM_L.RAMB18_Y1.ZSRVAL_B[3] origin:025-bram-config 27_302
@ -436,21 +418,39 @@ BRAM_L.RAMB18_Y1.ZSRVAL_B[6] origin:025-bram-config 27_238
BRAM_L.RAMB18_Y1.ZSRVAL_B[7] origin:025-bram-config 27_222
BRAM_L.RAMB18_Y1.ZSRVAL_B[8] origin:025-bram-config 27_206
BRAM_L.RAMB18_Y1.ZSRVAL_B[9] origin:025-bram-config 27_190
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182
BRAM_L.RAMB36.BRAM36_READ_WIDTH_A_1 origin:027-bram36-config 27_184
BRAM_L.RAMB36.BRAM36_READ_WIDTH_B_1 origin:027-bram36-config 27_181
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_A_1 origin:027-bram36-config 27_180
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_B_1 origin:027-bram36-config 27_179
BRAM_L.RAMB36.EN_ECC_READ origin:027-bram36-config 27_175
BRAM_L.RAMB36.EN_ECC_WRITE origin:027-bram36-config 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER origin:027-bram36-config 27_188
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
BRAM_L.RAMB36.BRAM36_READ_WIDTH_A_1 origin:027-bram36-config 27_184
BRAM_L.RAMB36.BRAM36_READ_WIDTH_B_1 origin:027-bram36-config 27_181
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_A_1 origin:027-bram36-config 27_180
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_B_1 origin:027-bram36-config 27_179
BRAM_L.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312
BRAM_L.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307
BRAM_L.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32
BRAM_L.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08
BRAM_L.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13

18432
kintex7/segbits_bram_r.block_ram.db
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File diff suppressed because it is too large Load Diff

18432
kintex7/segbits_bram_r.block_ram.origin_info.db
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File diff suppressed because it is too large Load Diff

324
kintex7/segbits_bram_r.db
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@ -1,6 +1,21 @@
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 26_32 !26_33 26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 26_32 26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_R_IMUX_ADDRARDADDRL0 !26_32 !26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_R_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_R_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_R_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 26_48 !26_49 26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 26_48 26_49 !26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_R_IMUX_ADDRARDADDRL1 !26_48 !26_49 !26_51
@ -28,24 +43,24 @@ BRAM_R.BRAM_ADDRARDADDRL8.BRAM_R_IMUX_ADDRARDADDRL8 !26_80 !26_81 !26_83
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 26_208 !26_209 26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 26_208 26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_R_IMUX_ADDRARDADDRL9 !26_208 !26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_R_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_R_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_R_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 26_37 !26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 !26_37 26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_R_IMUX_ADDRARDADDRU0 !26_37 !26_38 !26_39
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_R_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_R_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_R_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_R_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_R_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 26_53 !26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 !26_53 26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_R_IMUX_ADDRARDADDRU1 !26_53 !26_54 !26_55
@ -73,24 +88,24 @@ BRAM_R.BRAM_ADDRARDADDRU8.BRAM_R_IMUX_ADDRARDADDRU8 !26_85 !26_86 !26_87
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 26_213 !26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 !26_213 26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_R_IMUX_ADDRARDADDRU9 !26_213 !26_214 !26_215
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_R_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_R_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_R_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_R_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_R_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_40 !26_41 26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 26_40 26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_R_IMUX_ADDRBWRADDRL0 !26_40 !26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_R_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_R_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_R_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_56 !26_57 26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 26_56 26_57 !26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_R_IMUX_ADDRBWRADDRL1 !26_56 !26_57 !26_59
@ -118,24 +133,24 @@ BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_R_IMUX_ADDRBWRADDRL8 !26_88 !26_89 !26_91
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_216 !26_217 26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 26_216 26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_R_IMUX_ADDRBWRADDRL9 !26_216 !26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_R_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_R_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_R_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_45 !26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 !26_45 26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_R_IMUX_ADDRBWRADDRU0 !26_45 !26_46 !26_47
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_61 !26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 !26_61 26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_R_IMUX_ADDRBWRADDRU1 !26_61 !26_62 !26_63
@ -163,51 +178,10 @@ BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_R_IMUX_ADDRBWRADDRU8 !26_93 !26_94 !26_95
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_221 !26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 !26_221 26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_R_IMUX_ADDRBWRADDRU9 !26_221 !26_222 !26_223
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_R.CASCOUT_ARD_ACTIVE 26_170
BRAM_R.CASCOUT_BWR_ACTIVE 26_172
BRAM_R.EN_SYN 27_171
BRAM_R.FIRST_WORD_FALL_THROUGH 27_170
BRAM_R.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_R.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_R.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_R.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_R.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_R.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_R.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_R.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_R.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_R.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_R.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_R.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_R.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_R.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_R.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_R.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_R.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_R.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_R.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_R.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_R.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_R.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_R.ZALMOST_FULL_OFFSET[9] 27_13
BRAM_R.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_R.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_R.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_R.RAMB18_Y0.DOA_REG 27_69
BRAM_R.RAMB18_Y0.DOB_REG 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE 27_150
@ -215,15 +189,15 @@ BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
@ -235,17 +209,25 @@ BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_R.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_R.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_R.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_R.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_R.RAMB18_Y0.ZINIT_A[4] 27_105
@ -254,16 +236,16 @@ BRAM_R.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_R.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_R.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_R.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_R.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_R.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_R.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_R.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_R.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_R.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_R.RAMB18_Y0.ZINIT_B[4] 27_111
@ -272,14 +254,6 @@ BRAM_R.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_R.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_R.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_R.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_R.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -291,7 +265,15 @@ BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.ZSRVAL_A[4] 27_106
@ -300,16 +282,16 @@ BRAM_R.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.ZSRVAL_B[4] 27_110
@ -318,14 +300,6 @@ BRAM_R.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_R.RAMB18_Y1.DOA_REG 27_251
BRAM_R.RAMB18_Y1.DOB_REG 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE 27_169
@ -333,15 +307,15 @@ BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
@ -353,17 +327,25 @@ BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_R.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_R.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_R.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_R.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_R.RAMB18_Y1.ZINIT_A[4] 27_281
@ -372,16 +354,16 @@ BRAM_R.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_R.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_R.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_R.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_R.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_R.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_R.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_R.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_R.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_R.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_R.RAMB18_Y1.ZINIT_B[4] 27_287
@ -390,14 +372,6 @@ BRAM_R.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_R.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_R.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_R.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_R.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -409,7 +383,15 @@ BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_R.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.ZSRVAL_A[4] 27_282
@ -418,16 +400,16 @@ BRAM_R.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.ZSRVAL_B[4] 27_286
@ -436,21 +418,39 @@ BRAM_R.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_R.RAMB36.BRAM36_READ_WIDTH_A_1 27_184
BRAM_R.RAMB36.BRAM36_READ_WIDTH_B_1 27_181
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_A_1 27_180
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_B_1 27_179
BRAM_R.RAMB36.EN_ECC_READ 27_175
BRAM_R.RAMB36.EN_ECC_WRITE 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
BRAM_R.RAMB36.BRAM36_READ_WIDTH_A_1 27_184
BRAM_R.RAMB36.BRAM36_READ_WIDTH_B_1 27_181
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_A_1 27_180
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_B_1 27_179
BRAM_R.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_R.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_R.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_R.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_R.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_R.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_R.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_R.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_R.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_R.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_R.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_R.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_R.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_R.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_R.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_R.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_R.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_R.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_R.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_R.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_R.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_R.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_R.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_R.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_R.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_R.ZALMOST_FULL_OFFSET[9] 27_13

324
kintex7/segbits_bram_r.origin_info.db
View File

@ -1,6 +1,21 @@
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_33 26_32 26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_35 26_32 26_33
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_R_IMUX_ADDRARDADDRL0 origin:060-bram-cascades !26_32 !26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_113 26_112 26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_115 26_112 26_113
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_R_IMUX_ADDRARDADDRL11 origin:060-bram-cascades !26_112 !26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_241 26_240 26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_243 26_240 26_241
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_R_IMUX_ADDRARDADDRL12 origin:060-bram-cascades !26_240 !26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_129 26_128 26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_131 26_128 26_129
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_R_IMUX_ADDRARDADDRL13 origin:060-bram-cascades !26_128 !26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_257 26_256 26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_49 26_48 26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_51 26_48 26_49
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_R_IMUX_ADDRARDADDRL1 origin:060-bram-cascades !26_48 !26_49 !26_51
@ -28,24 +43,24 @@ BRAM_R.BRAM_ADDRARDADDRL8.BRAM_R_IMUX_ADDRARDADDRL8 origin:060-bram-cascades !26
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_209 26_208 26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_211 26_208 26_209
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_R_IMUX_ADDRARDADDRL9 origin:060-bram-cascades !26_208 !26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_113 26_112 26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_115 26_112 26_113
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_R_IMUX_ADDRARDADDRL11 origin:060-bram-cascades !26_112 !26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_241 26_240 26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_243 26_240 26_241
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_R_IMUX_ADDRARDADDRL12 origin:060-bram-cascades !26_240 !26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_129 26_128 26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_131 26_128 26_129
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_R_IMUX_ADDRARDADDRL13 origin:060-bram-cascades !26_128 !26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_257 26_256 26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_38 26_37 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_37 26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_R_IMUX_ADDRARDADDRU0 origin:060-bram-cascades !26_37 !26_38 !26_39
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_150 26_149 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_149 26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_R_IMUX_ADDRARDADDRU10 origin:060-bram-cascades !26_149 !26_150 !26_151
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_118 26_117 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_117 26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_R_IMUX_ADDRARDADDRU11 origin:060-bram-cascades !26_117 !26_118 !26_119
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_R_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_R_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_R_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_54 26_53 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_53 26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_R_IMUX_ADDRARDADDRU1 origin:060-bram-cascades !26_53 !26_54 !26_55
@ -73,24 +88,24 @@ BRAM_R.BRAM_ADDRARDADDRU8.BRAM_R_IMUX_ADDRARDADDRU8 origin:060-bram-cascades !26
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_214 26_213 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_213 26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_R_IMUX_ADDRARDADDRU9 origin:060-bram-cascades !26_213 !26_214 !26_215
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_150 26_149 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_149 26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_R_IMUX_ADDRARDADDRU10 origin:060-bram-cascades !26_149 !26_150 !26_151
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_118 26_117 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_117 26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_R_IMUX_ADDRARDADDRU11 origin:060-bram-cascades !26_117 !26_118 !26_119
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_R_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_R_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_R_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_41 26_40 26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_43 26_40 26_41
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_R_IMUX_ADDRBWRADDRL0 origin:060-bram-cascades !26_40 !26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_R_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_R_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_R_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_57 26_56 26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_59 26_56 26_57
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_R_IMUX_ADDRBWRADDRL1 origin:060-bram-cascades !26_56 !26_57 !26_59
@ -118,24 +133,24 @@ BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_R_IMUX_ADDRBWRADDRL8 origin:060-bram-cascades !26
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_217 26_216 26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_219 26_216 26_217
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_R_IMUX_ADDRBWRADDRL9 origin:060-bram-cascades !26_216 !26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_R_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_R_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_R_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_46 26_45 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_R_IMUX_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 !26_46 !26_47
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_62 26_61 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_R_IMUX_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 !26_62 !26_63
@ -163,67 +178,26 @@ BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_R_IMUX_ADDRBWRADDRU8 origin:060-bram-cascades !26
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_222 26_221 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_R_IMUX_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 !26_222 !26_223
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271
BRAM_R.CASCOUT_ARD_ACTIVE origin:060-bram-cascades 26_170
BRAM_R.CASCOUT_BWR_ACTIVE origin:060-bram-cascades 26_172
BRAM_R.EN_SYN origin:028-fifo-config 27_171
BRAM_R.FIRST_WORD_FALL_THROUGH origin:028-fifo-config 27_170
BRAM_R.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288
BRAM_R.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291
BRAM_R.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292
BRAM_R.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293
BRAM_R.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296
BRAM_R.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299
BRAM_R.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300
BRAM_R.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301
BRAM_R.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304
BRAM_R.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307
BRAM_R.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308
BRAM_R.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309
BRAM_R.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312
BRAM_R.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32
BRAM_R.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29
BRAM_R.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28
BRAM_R.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27
BRAM_R.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24
BRAM_R.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21
BRAM_R.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20
BRAM_R.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19
BRAM_R.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16
BRAM_R.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13
BRAM_R.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12
BRAM_R.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11
BRAM_R.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08
BRAM_R.RAMB18_Y0.DOA_REG origin:025-bram-config 27_69
BRAM_R.RAMB18_Y0.DOB_REG origin:025-bram-config 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE origin:029-bram-fifo-config 27_150
BRAM_R.RAMB18_Y0.IN_USE origin:029-bram-fifo-config 27_100 27_99
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 origin:025-bram-config !27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 origin:025-bram-config !27_36 !27_37 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 origin:025-bram-config !27_35 !27_37 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 origin:025-bram-config !27_37 27_35 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_1 origin:025-bram-config !27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 origin:025-bram-config !27_44 !27_45 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 origin:025-bram-config !27_43 !27_45 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 origin:025-bram-config !27_45 27_43 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_125
@ -234,17 +208,25 @@ BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_1 origin:025-bram-config !27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 origin:025-bram-config !27_52 !27_53 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 origin:025-bram-config !27_51 !27_53 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 origin:025-bram-config !27_53 27_51 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_1 origin:025-bram-config !27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 origin:025-bram-config !27_60 !27_61 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 origin:025-bram-config !27_59 !27_61 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 origin:025-bram-config !27_61 27_59 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.ZINIT_A[0] origin:025-bram-config 27_73
BRAM_R.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01
BRAM_R.RAMB18_Y0.ZINIT_A[1] origin:025-bram-config 27_65
BRAM_R.RAMB18_Y0.ZINIT_A[2] origin:025-bram-config 27_137
BRAM_R.RAMB18_Y0.ZINIT_A[3] origin:025-bram-config 27_121
@ -254,15 +236,15 @@ BRAM_R.RAMB18_Y0.ZINIT_A[6] origin:025-bram-config 27_57
BRAM_R.RAMB18_Y0.ZINIT_A[7] origin:025-bram-config 27_41
BRAM_R.RAMB18_Y0.ZINIT_A[8] origin:025-bram-config 27_25
BRAM_R.RAMB18_Y0.ZINIT_A[9] origin:025-bram-config 27_09
BRAM_R.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01
BRAM_R.RAMB18_Y0.ZINIT_B[0] origin:025-bram-config 27_79
BRAM_R.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07
BRAM_R.RAMB18_Y0.ZINIT_B[1] origin:025-bram-config 27_71
BRAM_R.RAMB18_Y0.ZINIT_B[2] origin:025-bram-config 27_143
BRAM_R.RAMB18_Y0.ZINIT_B[3] origin:025-bram-config 27_127
@ -272,14 +254,6 @@ BRAM_R.RAMB18_Y0.ZINIT_B[6] origin:025-bram-config 27_63
BRAM_R.RAMB18_Y0.ZINIT_B[7] origin:025-bram-config 27_47
BRAM_R.RAMB18_Y0.ZINIT_B[8] origin:025-bram-config 27_31
BRAM_R.RAMB18_Y0.ZINIT_B[9] origin:025-bram-config 27_15
BRAM_R.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK origin:025-bram-config 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK origin:025-bram-config 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN origin:025-bram-config 27_112
@ -291,6 +265,14 @@ BRAM_R.RAMB18_Y0.ZINV_RSTRAMB origin:025-bram-config 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG origin:025-bram-config 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB origin:025-bram-config 27_123
BRAM_R.RAMB18_Y0.ZSRVAL_A[0] origin:025-bram-config 27_74
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_A[1] origin:025-bram-config 27_66
BRAM_R.RAMB18_Y0.ZSRVAL_A[2] origin:025-bram-config 27_138
BRAM_R.RAMB18_Y0.ZSRVAL_A[3] origin:025-bram-config 27_122
@ -300,15 +282,15 @@ BRAM_R.RAMB18_Y0.ZSRVAL_A[6] origin:025-bram-config 27_58
BRAM_R.RAMB18_Y0.ZSRVAL_A[7] origin:025-bram-config 27_42
BRAM_R.RAMB18_Y0.ZSRVAL_A[8] origin:025-bram-config 27_26
BRAM_R.RAMB18_Y0.ZSRVAL_A[9] origin:025-bram-config 27_10
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_B[0] origin:025-bram-config 27_78
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06
BRAM_R.RAMB18_Y0.ZSRVAL_B[1] origin:025-bram-config 27_70
BRAM_R.RAMB18_Y0.ZSRVAL_B[2] origin:025-bram-config 27_142
BRAM_R.RAMB18_Y0.ZSRVAL_B[3] origin:025-bram-config 27_126
@ -318,30 +300,22 @@ BRAM_R.RAMB18_Y0.ZSRVAL_B[6] origin:025-bram-config 27_62
BRAM_R.RAMB18_Y0.ZSRVAL_B[7] origin:025-bram-config 27_46
BRAM_R.RAMB18_Y0.ZSRVAL_B[8] origin:025-bram-config 27_30
BRAM_R.RAMB18_Y0.ZSRVAL_B[9] origin:025-bram-config 27_14
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06
BRAM_R.RAMB18_Y1.DOA_REG origin:025-bram-config 27_251
BRAM_R.RAMB18_Y1.DOB_REG origin:025-bram-config 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE origin:029-bram-fifo-config 27_169
BRAM_R.RAMB18_Y1.IN_USE origin:029-bram-fifo-config 27_220 27_221
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 origin:025-bram-config !27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 origin:025-bram-config !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 origin:025-bram-config !27_283 !27_285 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 origin:025-bram-config !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275
BRAM_R.RAMB18_Y1.READ_WIDTH_B_1 origin:025-bram-config !27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 origin:025-bram-config !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 origin:025-bram-config !27_275 !27_277 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 origin:025-bram-config !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_195
@ -352,17 +326,25 @@ BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_1 origin:025-bram-config !27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 origin:025-bram-config !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 origin:025-bram-config !27_267 !27_269 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 origin:025-bram-config !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_1 origin:025-bram-config !27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 origin:025-bram-config !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 origin:025-bram-config !27_259 !27_261 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 origin:025-bram-config !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259
BRAM_R.RAMB18_Y1.ZINIT_A[0] origin:025-bram-config 27_249
BRAM_R.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177
BRAM_R.RAMB18_Y1.ZINIT_A[1] origin:025-bram-config 27_241
BRAM_R.RAMB18_Y1.ZINIT_A[2] origin:025-bram-config 27_313
BRAM_R.RAMB18_Y1.ZINIT_A[3] origin:025-bram-config 27_297
@ -372,15 +354,15 @@ BRAM_R.RAMB18_Y1.ZINIT_A[6] origin:025-bram-config 27_233
BRAM_R.RAMB18_Y1.ZINIT_A[7] origin:025-bram-config 27_217
BRAM_R.RAMB18_Y1.ZINIT_A[8] origin:025-bram-config 27_201
BRAM_R.RAMB18_Y1.ZINIT_A[9] origin:025-bram-config 27_185
BRAM_R.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177
BRAM_R.RAMB18_Y1.ZINIT_B[0] origin:025-bram-config 27_255
BRAM_R.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183
BRAM_R.RAMB18_Y1.ZINIT_B[1] origin:025-bram-config 27_247
BRAM_R.RAMB18_Y1.ZINIT_B[2] origin:025-bram-config 27_319
BRAM_R.RAMB18_Y1.ZINIT_B[3] origin:025-bram-config 27_303
@ -390,14 +372,6 @@ BRAM_R.RAMB18_Y1.ZINIT_B[6] origin:025-bram-config 27_239
BRAM_R.RAMB18_Y1.ZINIT_B[7] origin:025-bram-config 27_223
BRAM_R.RAMB18_Y1.ZINIT_B[8] origin:025-bram-config 27_207
BRAM_R.RAMB18_Y1.ZINIT_B[9] origin:025-bram-config 27_191
BRAM_R.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK origin:025-bram-config 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK origin:025-bram-config 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN origin:025-bram-config 27_208
@ -409,6 +383,14 @@ BRAM_R.RAMB18_Y1.ZINV_RSTRAMB origin:025-bram-config 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG origin:025-bram-config 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB origin:025-bram-config 27_197
BRAM_R.RAMB18_Y1.ZSRVAL_A[0] origin:025-bram-config 27_250
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_A[1] origin:025-bram-config 27_242
BRAM_R.RAMB18_Y1.ZSRVAL_A[2] origin:025-bram-config 27_314
BRAM_R.RAMB18_Y1.ZSRVAL_A[3] origin:025-bram-config 27_298
@ -418,15 +400,15 @@ BRAM_R.RAMB18_Y1.ZSRVAL_A[6] origin:025-bram-config 27_234
BRAM_R.RAMB18_Y1.ZSRVAL_A[7] origin:025-bram-config 27_218
BRAM_R.RAMB18_Y1.ZSRVAL_A[8] origin:025-bram-config 27_202
BRAM_R.RAMB18_Y1.ZSRVAL_A[9] origin:025-bram-config 27_186
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_B[0] origin:025-bram-config 27_254
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182
BRAM_R.RAMB18_Y1.ZSRVAL_B[1] origin:025-bram-config 27_246
BRAM_R.RAMB18_Y1.ZSRVAL_B[2] origin:025-bram-config 27_318
BRAM_R.RAMB18_Y1.ZSRVAL_B[3] origin:025-bram-config 27_302
@ -436,21 +418,39 @@ BRAM_R.RAMB18_Y1.ZSRVAL_B[6] origin:025-bram-config 27_238
BRAM_R.RAMB18_Y1.ZSRVAL_B[7] origin:025-bram-config 27_222
BRAM_R.RAMB18_Y1.ZSRVAL_B[8] origin:025-bram-config 27_206
BRAM_R.RAMB18_Y1.ZSRVAL_B[9] origin:025-bram-config 27_190
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182
BRAM_R.RAMB36.BRAM36_READ_WIDTH_A_1 origin:027-bram36-config 27_184
BRAM_R.RAMB36.BRAM36_READ_WIDTH_B_1 origin:027-bram36-config 27_181
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_A_1 origin:027-bram36-config 27_180
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_B_1 origin:027-bram36-config 27_179
BRAM_R.RAMB36.EN_ECC_READ origin:027-bram36-config 27_175
BRAM_R.RAMB36.EN_ECC_WRITE origin:027-bram36-config 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER origin:027-bram36-config 27_188
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
BRAM_R.RAMB36.BRAM36_READ_WIDTH_A_1 origin:027-bram36-config 27_184
BRAM_R.RAMB36.BRAM36_READ_WIDTH_B_1 origin:027-bram36-config 27_181
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_A_1 origin:027-bram36-config 27_180
BRAM_R.RAMB36.BRAM36_WRITE_WIDTH_B_1 origin:027-bram36-config 27_179
BRAM_R.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288
BRAM_R.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308
BRAM_R.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309
BRAM_R.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312
BRAM_R.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291
BRAM_R.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292
BRAM_R.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293
BRAM_R.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296
BRAM_R.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299
BRAM_R.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300
BRAM_R.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301
BRAM_R.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304
BRAM_R.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307
BRAM_R.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32
BRAM_R.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12
BRAM_R.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11
BRAM_R.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08
BRAM_R.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29
BRAM_R.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28
BRAM_R.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27
BRAM_R.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24
BRAM_R.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21
BRAM_R.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20
BRAM_R.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19
BRAM_R.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16
BRAM_R.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13

2
kintex7/segbits_cfg_center_mid.db
View File

@ -3,6 +3,6 @@ CFG_CENTER_MID.BSCAN.JTAG_CHAIN_2 27_2162
CFG_CENTER_MID.BSCAN.JTAG_CHAIN_3 26_2163
CFG_CENTER_MID.BSCAN.JTAG_CHAIN_4 27_2163
CFG_CENTER_MID.DCIRESET.ENABLED 26_2165 26_2166 27_2164
CFG_CENTER_MID.ICAP.ICAP_WIDTH_X8 26_2203 26_2204 27_2202
CFG_CENTER_MID.ICAP.ICAP_WIDTH_X16 26_2199 27_2200 27_2201
CFG_CENTER_MID.ICAP.ICAP_WIDTH_X8 26_2203 26_2204 27_2202
CFG_CENTER_MID.STARTUP.PROG_USR 26_2197 26_2198 27_2196

2
kintex7/segbits_cfg_center_mid.origin_info.db
View File

@ -3,6 +3,6 @@ CFG_CENTER_MID.BSCAN.JTAG_CHAIN_2 origin:038-cfg 27_2162
CFG_CENTER_MID.BSCAN.JTAG_CHAIN_3 origin:038-cfg 26_2163
CFG_CENTER_MID.BSCAN.JTAG_CHAIN_4 origin:038-cfg 27_2163
CFG_CENTER_MID.DCIRESET.ENABLED origin:038-cfg 26_2165 26_2166 27_2164
CFG_CENTER_MID.ICAP.ICAP_WIDTH_X8 origin:038-cfg 26_2203 26_2204 27_2202
CFG_CENTER_MID.ICAP.ICAP_WIDTH_X16 origin:038-cfg 26_2199 27_2200 27_2201
CFG_CENTER_MID.ICAP.ICAP_WIDTH_X8 origin:038-cfg 26_2203 26_2204 27_2202
CFG_CENTER_MID.STARTUP.PROG_USR origin:038-cfg 26_2197 26_2198 27_2196

116
kintex7/segbits_clbll_l.db
View File

@ -1,15 +1,15 @@
CLBLL_L.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14
@ -76,22 +76,22 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30
@ -158,23 +158,27 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CLKINV 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
@ -242,21 +246,21 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
@ -323,33 +327,29 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_L.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.NOCLKINV !01_51
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -416,22 +416,22 @@ CLBLL_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -498,23 +498,27 @@ CLBLL_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLL_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CLKINV 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -582,21 +586,21 @@ CLBLL_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -663,18 +667,14 @@ CLBLL_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLL_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.NOCLKINV !00_52
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49

116
kintex7/segbits_clbll_l.origin_info.db
View File

@ -1,15 +1,15 @@
CLBLL_L.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLL_L.SLICEL_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLL_L.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLL_L.SLICEL_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLL_L.SLICEL_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLL_L.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLL_L.SLICEL_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLL_L.SLICEL_X0.ALUT.INIT[00] origin:010-clb-lutinit 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] origin:010-clb-lutinit 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] origin:010-clb-lutinit 32_14
@ -76,22 +76,22 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[62] origin:010-clb-lutinit 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] origin:010-clb-lutinit 34_00
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLL_L.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLL_L.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLL_L.SLICEL_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLL_L.SLICEL_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLL_L.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLL_L.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLL_L.SLICEL_X0.BLUT.INIT[00] origin:010-clb-lutinit 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] origin:010-clb-lutinit 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] origin:010-clb-lutinit 32_30
@ -158,23 +158,27 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[62] origin:010-clb-lutinit 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] origin:010-clb-lutinit 34_16
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLL_L.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLL_L.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLL_L.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLL_L.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLL_L.SLICEL_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLL_L.SLICEL_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLL_L.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLL_L.SLICEL_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLL_L.SLICEL_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] origin:010-clb-lutinit 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] origin:010-clb-lutinit 33_47
@ -242,21 +246,21 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[62] origin:010-clb-lutinit 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] origin:010-clb-lutinit 34_32
CLBLL_L.SLICEL_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLL_L.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLL_L.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLL_L.SLICEL_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLL_L.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLL_L.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLL_L.SLICEL_X0.DLUT.INIT[00] origin:010-clb-lutinit 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] origin:010-clb-lutinit 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] origin:010-clb-lutinit 32_62
@ -323,33 +327,29 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[62] origin:010-clb-lutinit 35_48
CLBLL_L.SLICEL_X0.DLUT.INIT[63] origin:010-clb-lutinit 34_48
CLBLL_L.SLICEL_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_L.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_L.SLICEL_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLL_L.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLL_L.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLL_L.SLICEL_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLL_L.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLL_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLL_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLL_L.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLL_L.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLL_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLL_L.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLL_L.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLL_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLL_L.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
@ -416,22 +416,22 @@ CLBLL_L.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLL_L.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLL_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLL_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLL_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLL_L.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLL_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLL_L.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLL_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLL_L.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
@ -498,23 +498,27 @@ CLBLL_L.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLL_L.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLL_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLL_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLL_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLL_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLL_L.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLL_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLL_L.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLL_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLL_L.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
@ -582,21 +586,21 @@ CLBLL_L.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLL_L.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLL_L.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLL_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLL_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLL_L.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLL_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLL_L.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLL_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLL_L.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
@ -663,18 +667,14 @@ CLBLL_L.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLL_L.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLL_L.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_L.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLL_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLL_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLL_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLL_L.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32
CLBLL_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49

116
kintex7/segbits_clbll_r.db
View File

@ -1,15 +1,15 @@
CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
CLBLL_R.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_R.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_R.SLICEL_X0.ALUT.INIT[02] 32_14
@ -76,22 +76,22 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_R.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
CLBLL_R.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_R.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_R.SLICEL_X0.BLUT.INIT[02] 32_30
@ -158,23 +158,27 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
CLBLL_R.SLICEL_X0.CLKINV 01_51
CLBLL_R.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_R.SLICEL_X0.CLUT.INIT[01] 33_47
@ -242,21 +246,21 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_R.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_R.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_R.SLICEL_X0.DLUT.INIT[02] 32_62
@ -323,33 +327,29 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_R.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.NOCLKINV !01_51
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
CLBLL_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -416,22 +416,22 @@ CLBLL_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
CLBLL_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -498,23 +498,27 @@ CLBLL_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLL_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
CLBLL_R.SLICEL_X1.CLKINV 00_52
CLBLL_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -582,21 +586,21 @@ CLBLL_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -663,18 +667,14 @@ CLBLL_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLL_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.NOCLKINV !00_52
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49

116
kintex7/segbits_clbll_r.origin_info.db
View File

@ -1,15 +1,15 @@
CLBLL_R.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLL_R.SLICEL_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLL_R.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLL_R.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLL_R.SLICEL_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLL_R.SLICEL_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLL_R.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLL_R.SLICEL_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLL_R.SLICEL_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLL_R.SLICEL_X0.ALUT.INIT[00] origin:010-clb-lutinit 32_15
CLBLL_R.SLICEL_X0.ALUT.INIT[01] origin:010-clb-lutinit 33_15
CLBLL_R.SLICEL_X0.ALUT.INIT[02] origin:010-clb-lutinit 32_14
@ -76,22 +76,22 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[62] origin:010-clb-lutinit 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] origin:010-clb-lutinit 34_00
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLL_R.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLL_R.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLL_R.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLL_R.SLICEL_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLL_R.SLICEL_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLL_R.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLL_R.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLL_R.SLICEL_X0.BLUT.INIT[00] origin:010-clb-lutinit 32_31
CLBLL_R.SLICEL_X0.BLUT.INIT[01] origin:010-clb-lutinit 33_31
CLBLL_R.SLICEL_X0.BLUT.INIT[02] origin:010-clb-lutinit 32_30
@ -158,23 +158,27 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[62] origin:010-clb-lutinit 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] origin:010-clb-lutinit 34_16
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLL_R.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLL_R.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLL_R.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLL_R.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLL_R.SLICEL_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLL_R.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLL_R.SLICEL_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLL_R.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLL_R.SLICEL_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLL_R.SLICEL_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLL_R.SLICEL_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLL_R.SLICEL_X0.CLUT.INIT[00] origin:010-clb-lutinit 32_47
CLBLL_R.SLICEL_X0.CLUT.INIT[01] origin:010-clb-lutinit 33_47
@ -242,21 +246,21 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[62] origin:010-clb-lutinit 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] origin:010-clb-lutinit 34_32
CLBLL_R.SLICEL_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLL_R.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLL_R.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLL_R.SLICEL_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLL_R.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLL_R.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLL_R.SLICEL_X0.DLUT.INIT[00] origin:010-clb-lutinit 32_63
CLBLL_R.SLICEL_X0.DLUT.INIT[01] origin:010-clb-lutinit 33_63
CLBLL_R.SLICEL_X0.DLUT.INIT[02] origin:010-clb-lutinit 32_62
@ -323,33 +327,29 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[62] origin:010-clb-lutinit 35_48
CLBLL_R.SLICEL_X0.DLUT.INIT[63] origin:010-clb-lutinit 34_48
CLBLL_R.SLICEL_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_R.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_R.SLICEL_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLL_R.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLL_R.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLL_R.SLICEL_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLL_R.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLL_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLL_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLL_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLL_R.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLL_R.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLL_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLL_R.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLL_R.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLL_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLL_R.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLL_R.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLL_R.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
@ -416,22 +416,22 @@ CLBLL_R.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLL_R.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLL_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLL_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLL_R.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLL_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLL_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLL_R.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLL_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLL_R.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLL_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLL_R.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLL_R.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLL_R.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
@ -498,23 +498,27 @@ CLBLL_R.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLL_R.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLL_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLL_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLL_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLL_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLL_R.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLL_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLL_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLL_R.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLL_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLL_R.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLL_R.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLL_R.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
@ -582,21 +586,21 @@ CLBLL_R.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLL_R.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLL_R.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLL_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLL_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLL_R.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLL_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLL_R.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLL_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLL_R.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLL_R.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLL_R.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
@ -663,18 +667,14 @@ CLBLL_R.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLL_R.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLL_R.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_R.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLL_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLL_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLL_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLL_R.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32
CLBLL_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49

116
kintex7/segbits_clblm_l.db
View File

@ -1,15 +1,15 @@
CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
CLBLM_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -76,22 +76,22 @@ CLBLM_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
CLBLM_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -158,23 +158,27 @@ CLBLM_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLM_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
CLBLM_L.SLICEL_X1.CLKINV 00_52
CLBLM_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -242,21 +246,21 @@ CLBLM_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -323,33 +327,29 @@ CLBLM_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLM_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.NOCLKINV !00_52
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
@ -421,22 +421,22 @@ CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_L.SLICEM_X0.ALUT.SRL 30_16
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
@ -508,23 +508,27 @@ CLBLM_L.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_L.SLICEM_X0.BLUT.SRL 30_17
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
CLBLM_L.SLICEM_X0.CLKINV 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
@ -597,22 +601,22 @@ CLBLM_L.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_L.SLICEM_X0.CLUT.SRL 30_46
CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_L.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_L.SLICEM_X0.DLUT.INIT[02] 34_62
@ -682,22 +686,18 @@ CLBLM_L.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.NOCLKINV !01_51
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_L.SLICEM_X0.WA7USED 00_40
CLBLM_L.SLICEM_X0.WA8USED 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE 01_23
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49

116
kintex7/segbits_clblm_l.origin_info.db
View File

@ -1,15 +1,15 @@
CLBLM_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLM_L.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLM_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLM_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLM_L.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLM_L.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLM_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLM_L.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLM_L.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLM_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLM_L.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLM_L.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLM_L.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
@ -76,22 +76,22 @@ CLBLM_L.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLM_L.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLM_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLM_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLM_L.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLM_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLM_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLM_L.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLM_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLM_L.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLM_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLM_L.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLM_L.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLM_L.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
@ -158,23 +158,27 @@ CLBLM_L.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLM_L.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLM_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLM_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLM_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLM_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLM_L.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLM_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLM_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLM_L.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLM_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLM_L.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLM_L.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLM_L.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
@ -242,21 +246,21 @@ CLBLM_L.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLM_L.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLM_L.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLM_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLM_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLM_L.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLM_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLM_L.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLM_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLM_L.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLM_L.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLM_L.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
@ -323,33 +327,29 @@ CLBLM_L.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLM_L.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLM_L.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_L.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLM_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLM_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLM_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLM_L.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32
CLBLM_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLM_L.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLM_L.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLM_L.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLM_L.SLICEM_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLM_L.SLICEM_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLM_L.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLM_L.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 origin:019-clb-ndi1mux !00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
@ -421,22 +421,22 @@ CLBLM_L.SLICEM_X0.ALUT.SMALL origin:018-clb-ram 00_04
CLBLM_L.SLICEM_X0.ALUT.SRL origin:018-clb-ram 30_16
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLM_L.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLM_L.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLM_L.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLM_L.SLICEM_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLM_L.SLICEM_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLM_L.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 origin:019-clb-ndi1mux !00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
@ -508,23 +508,27 @@ CLBLM_L.SLICEM_X0.BLUT.SMALL origin:018-clb-ram 00_24
CLBLM_L.SLICEM_X0.BLUT.SRL origin:018-clb-ram 30_17
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLM_L.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLM_L.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLM_L.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLM_L.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLM_L.SLICEM_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLM_L.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLM_L.SLICEM_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLM_L.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLM_L.SLICEM_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLM_L.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 origin:019-clb-ndi1mux !01_43
@ -597,22 +601,22 @@ CLBLM_L.SLICEM_X0.CLUT.SMALL origin:018-clb-ram 00_28
CLBLM_L.SLICEM_X0.CLUT.SRL origin:018-clb-ram 30_46
CLBLM_L.SLICEM_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLM_L.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_L.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_L.SLICEM_X0.DLUT.INIT[00] origin:010-clb-lutinit 34_63
CLBLM_L.SLICEM_X0.DLUT.INIT[01] origin:010-clb-lutinit 35_63
CLBLM_L.SLICEM_X0.DLUT.INIT[02] origin:010-clb-lutinit 34_62
@ -682,22 +686,18 @@ CLBLM_L.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_L.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_L.SLICEM_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLM_L.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLM_L.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLM_L.SLICEM_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLM_L.SLICEM_X0.WA7USED origin:018-clb-ram 00_40
CLBLM_L.SLICEM_X0.WA8USED origin:018-clb-ram 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE origin:018-clb-ram 01_23
CLBLM_L.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49

116
kintex7/segbits_clblm_r.db
View File

@ -1,15 +1,15 @@
CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
CLBLM_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -76,22 +76,22 @@ CLBLM_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
CLBLM_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -158,23 +158,27 @@ CLBLM_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLM_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
CLBLM_R.SLICEL_X1.CLKINV 00_52
CLBLM_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -242,21 +246,21 @@ CLBLM_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -323,33 +327,29 @@ CLBLM_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLM_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.NOCLKINV !00_52
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
@ -421,22 +421,22 @@ CLBLM_R.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_R.SLICEM_X0.ALUT.SRL 30_16
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
@ -508,23 +508,27 @@ CLBLM_R.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_R.SLICEM_X0.BLUT.SRL 30_17
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
CLBLM_R.SLICEM_X0.CLKINV 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
@ -597,22 +601,22 @@ CLBLM_R.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_R.SLICEM_X0.CLUT.SRL 30_46
CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_R.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_R.SLICEM_X0.DLUT.INIT[02] 34_62
@ -682,22 +686,18 @@ CLBLM_R.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.NOCLKINV !01_51
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_R.SLICEM_X0.WA7USED 00_40
CLBLM_R.SLICEM_X0.WA8USED 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE 01_23
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49

116
kintex7/segbits_clblm_r.origin_info.db
View File

@ -1,15 +1,15 @@
CLBLM_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLM_R.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11
CLBLM_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLM_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03
CLBLM_R.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01
CLBLM_R.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02
CLBLM_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01
CLBLM_R.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00
CLBLM_R.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04
CLBLM_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15
CLBLM_R.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15
CLBLM_R.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15
CLBLM_R.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14
@ -76,22 +76,22 @@ CLBLM_R.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00
CLBLM_R.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09
CLBLM_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLM_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19
CLBLM_R.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18
CLBLM_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLM_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16
CLBLM_R.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26
CLBLM_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25
CLBLM_R.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24
CLBLM_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30
CLBLM_R.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31
CLBLM_R.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31
CLBLM_R.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30
@ -158,23 +158,27 @@ CLBLM_R.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16
CLBLM_R.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20
CLBLM_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLM_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39
CLBLM_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44
CLBLM_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLM_R.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36
CLBLM_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37
CLBLM_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36
CLBLM_R.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36
CLBLM_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34
CLBLM_R.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52
CLBLM_R.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47
CLBLM_R.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47
@ -242,21 +246,21 @@ CLBLM_R.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32
CLBLM_R.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32
CLBLM_R.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLM_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLM_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56
CLBLM_R.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61
CLBLM_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60
CLBLM_R.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60
CLBLM_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50
CLBLM_R.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63
CLBLM_R.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63
CLBLM_R.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62
@ -323,33 +327,29 @@ CLBLM_R.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48
CLBLM_R.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48
CLBLM_R.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_R.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLM_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLM_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
CLBLM_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12
CLBLM_R.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32
CLBLM_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49
CLBLM_R.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10
CLBLM_R.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLM_R.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07
CLBLM_R.SLICEM_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01
CLBLM_R.SLICEM_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02
CLBLM_R.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01
CLBLM_R.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 origin:019-clb-ndi1mux !00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
@ -421,22 +421,22 @@ CLBLM_R.SLICEM_X0.ALUT.SMALL origin:018-clb-ram 00_04
CLBLM_R.SLICEM_X0.ALUT.SRL origin:018-clb-ram 30_16
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLM_R.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18
CLBLM_R.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLM_R.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19
CLBLM_R.SLICEM_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26
CLBLM_R.SLICEM_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27
CLBLM_R.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 origin:019-clb-ndi1mux !00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
@ -508,23 +508,27 @@ CLBLM_R.SLICEM_X0.BLUT.SMALL origin:018-clb-ram 00_24
CLBLM_R.SLICEM_X0.BLUT.SRL origin:018-clb-ram 30_17
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20
CLBLM_R.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLM_R.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39
CLBLM_R.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47
CLBLM_R.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49
CLBLM_R.SLICEM_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39
CLBLM_R.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36
CLBLM_R.SLICEM_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37
CLBLM_R.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36
CLBLM_R.SLICEM_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33
CLBLM_R.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 origin:019-clb-ndi1mux !01_43
@ -597,22 +601,22 @@ CLBLM_R.SLICEM_X0.CLUT.SMALL origin:018-clb-ram 00_28
CLBLM_R.SLICEM_X0.CLUT.SRL origin:018-clb-ram 30_46
CLBLM_R.SLICEM_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLM_R.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_R.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55
CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_R.SLICEM_X0.DLUT.INIT[00] origin:010-clb-lutinit 34_63
CLBLM_R.SLICEM_X0.DLUT.INIT[01] origin:010-clb-lutinit 35_63
CLBLM_R.SLICEM_X0.DLUT.INIT[02] origin:010-clb-lutinit 34_62
@ -682,22 +686,18 @@ CLBLM_R.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_R.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_R.SLICEM_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLM_R.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLM_R.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13
CLBLM_R.SLICEM_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35
CLBLM_R.SLICEM_X0.WA7USED origin:018-clb-ram 00_40
CLBLM_R.SLICEM_X0.WA8USED origin:018-clb-ram 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE origin:018-clb-ram 01_23
CLBLM_R.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49

526
kintex7/segbits_clk_bufg_bot_r.db
View File

@ -1,5 +1,5 @@
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE 27_00 27_15
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT 27_13
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE 27_00 27_15
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED 26_01
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED 27_12
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 26_12
@ -8,98 +8,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 27_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 27_03
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 26_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 26_02
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE 27_16 27_31
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT 27_29
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED 26_17
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED 27_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 26_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 27_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 27_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 27_19
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 26_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 26_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE 27_32 27_47
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT 27_45
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED 26_33
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED 27_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 26_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 27_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 27_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 27_35
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 26_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 26_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE 27_48 27_63
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT 27_61
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED 26_49
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED 27_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 26_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 27_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 27_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 27_51
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 26_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 26_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE 27_64 27_79
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT 27_77
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED 26_65
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED 27_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 26_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 27_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 27_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 27_67
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 26_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 26_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE 27_80 27_95
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT 27_93
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED 26_81
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED 27_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 26_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 27_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 27_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 27_83
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 26_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 26_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE 27_96 27_111
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT 27_109
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED 26_97
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED 27_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 26_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 27_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 27_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 27_99
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 26_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 26_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE 27_112 27_127
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT 27_125
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED 26_113
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED 27_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 26_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 27_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 27_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 27_115
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 26_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 26_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE 27_128 27_143
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT 27_141
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED 26_129
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED 27_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 26_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 27_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 27_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 27_131
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 26_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 26_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE 27_144 27_159
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT 27_157
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED 26_145
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED 27_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 26_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 27_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 27_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 27_147
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 26_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 26_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE 27_160 27_175
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT 27_173
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE 27_160 27_175
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED 26_161
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED 27_172
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 26_172
@ -108,8 +18,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 27_171
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 27_163
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 26_171
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 26_162
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE 27_176 27_191
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT 27_189
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE 27_176 27_191
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED 26_177
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED 27_188
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 26_188
@ -118,8 +28,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 27_187
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 27_179
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 26_187
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 26_178
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE 27_192 27_207
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT 27_205
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE 27_192 27_207
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED 26_193
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED 27_204
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 26_204
@ -128,8 +38,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 27_203
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 27_195
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 26_203
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 26_194
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE 27_208 27_223
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT 27_221
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE 27_208 27_223
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED 26_209
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED 27_220
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 26_220
@ -138,8 +48,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 27_219
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 27_211
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 26_219
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 26_210
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE 27_224 27_239
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT 27_237
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE 27_224 27_239
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED 26_225
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED 27_236
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 26_236
@ -148,8 +58,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 27_235
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 27_227
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 26_235
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 26_226
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT 27_253
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED 26_241
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED 27_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 26_252
@ -158,7 +68,263 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 27_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 27_243
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 26_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 26_242
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT 27_29
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE 27_16 27_31
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED 26_17
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED 27_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 26_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 27_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 27_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 27_19
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 26_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 26_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT 27_45
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE 27_32 27_47
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED 26_33
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED 27_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 26_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 27_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 27_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 27_35
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 26_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 26_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT 27_61
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE 27_48 27_63
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED 26_49
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED 27_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 26_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 27_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 27_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 27_51
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 26_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 26_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT 27_77
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE 27_64 27_79
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED 26_65
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED 27_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 26_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 27_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 27_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 27_67
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 26_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 26_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT 27_93
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE 27_80 27_95
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED 26_81
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED 27_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 26_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 27_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 27_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 27_83
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 26_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 26_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT 27_109
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE 27_96 27_111
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED 26_97
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED 27_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 26_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 27_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 27_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 27_99
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 26_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 26_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT 27_125
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE 27_112 27_127
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED 26_113
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED 27_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 26_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 27_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 27_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 27_115
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 26_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 26_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT 27_141
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE 27_128 27_143
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED 26_129
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED 27_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 26_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 27_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 27_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 27_131
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 26_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 26_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT 27_157
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE 27_144 27_159
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED 26_145
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED 27_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 26_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 27_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 27_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 27_147
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 26_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 26_146
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0 !26_07 26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 !26_07 !26_08 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 !26_07 !26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 26_07 !26_08 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 26_07 !26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 26_04 !26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 !26_04 26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 !26_04 !26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 !26_04 26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 !26_04 !26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 !26_167 26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 !26_167 !26_168 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 !26_167 !26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 26_167 !26_168 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 26_167 !26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 26_164 !26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 !26_164 26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 !26_164 !26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 !26_164 26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 !26_164 !26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 !26_183 26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 !26_183 !26_184 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 !26_183 !26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 26_183 !26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 26_183 !26_184 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 26_180 !26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 !26_180 26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 !26_180 !26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 !26_180 !26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 !26_180 26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 !26_199 26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 !26_199 !26_200 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 !26_199 !26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 26_199 !26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 26_199 !26_200 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 26_196 !26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 !26_196 26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 !26_196 !26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 !26_196 !26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 !26_196 26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 !26_215 26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 !26_215 !26_216 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 !26_215 !26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 26_215 !26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 26_215 !26_216 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 26_212 !26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 !26_212 26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 !26_212 !26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 !26_212 !26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 !26_212 26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 !26_231 26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 !26_231 !26_232 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 !26_231 !26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 26_231 !26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 26_231 !26_232 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 26_228 !26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 !26_228 26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 !26_228 !26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 !26_228 !26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 !26_228 26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 !26_247 26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 !26_247 !26_248 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 !26_247 !26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 26_247 !26_248 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 26_247 !26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 26_244 !26_245 !27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 !26_244 26_245 !27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 !26_244 !26_245 !27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 !26_244 26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 !26_244 !26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 !26_23 26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 !26_23 !26_24 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 !26_23 !26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 26_23 !26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 26_23 !26_24 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 26_20 !26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 !26_20 26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 !26_20 !26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 !26_20 !26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 !26_20 26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 !26_39 26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 !26_39 !26_40 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 !26_39 !26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 26_39 !26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 26_39 !26_40 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 26_36 !26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 !26_36 26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 !26_36 !26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 !26_36 !26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 !26_36 26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 !26_55 26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 !26_55 !26_56 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 !26_55 !26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 26_55 !26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 26_55 !26_56 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 26_52 !26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 !26_52 26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 !26_52 !26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 !26_52 !26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 !26_52 26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 !26_71 26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 !26_71 !26_72 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 !26_71 !26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 26_71 !26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 26_71 !26_72 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 26_68 !26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 !26_68 26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 !26_68 !26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 !26_68 !26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 !26_68 26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 !26_87 26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 !26_87 !26_88 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 !26_87 !26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 26_87 !26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 26_87 !26_88 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 26_84 !26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 !26_84 26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 !26_84 !26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 !26_84 !26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 !26_84 26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 !26_103 26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 !26_103 !26_104 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 !26_103 !26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 26_103 !26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 26_103 !26_104 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 26_100 !26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 !26_100 26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 !26_100 !26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 !26_100 !26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 !26_100 26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 !26_119 26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 !26_119 !26_120 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 !26_119 !26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 26_119 !26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 26_119 !26_120 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 26_116 !26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 !26_116 26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 !26_116 !26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 !26_116 !26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 !26_116 26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 !26_135 26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 !26_135 !26_136 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 !26_135 !26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 26_135 !26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 26_135 !26_136 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 26_132 !26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 !26_132 26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 !26_132 !26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 !26_132 !26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 !26_132 26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 !26_151 26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 !26_151 !26_152 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 !26_151 !26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 26_151 !26_152 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 26_151 !26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 26_148 !26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 !26_148 26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 !26_148 !26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 !26_148 26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 !26_148 !26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O 27_14
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK10.CLK_BUFG_BUFGCTRL10_O 27_174
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK11.CLK_BUFG_BUFGCTRL11_O 27_190
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK12.CLK_BUFG_BUFGCTRL12_O 27_206
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK13.CLK_BUFG_BUFGCTRL13_O 27_222
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK14.CLK_BUFG_BUFGCTRL14_O 27_238
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK15.CLK_BUFG_BUFGCTRL15_O 27_254
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK1.CLK_BUFG_BUFGCTRL1_O 27_30
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK2.CLK_BUFG_BUFGCTRL2_O 27_46
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK3.CLK_BUFG_BUFGCTRL3_O 27_62
@ -168,169 +334,3 @@ CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK6.CLK_BUFG_BUFGCTRL6_O 27_110
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK7.CLK_BUFG_BUFGCTRL7_O 27_126
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK8.CLK_BUFG_BUFGCTRL8_O 27_142
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK9.CLK_BUFG_BUFGCTRL9_O 27_158
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK10.CLK_BUFG_BUFGCTRL10_O 27_174
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK11.CLK_BUFG_BUFGCTRL11_O 27_190
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK12.CLK_BUFG_BUFGCTRL12_O 27_206
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK13.CLK_BUFG_BUFGCTRL13_O 27_222
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK14.CLK_BUFG_BUFGCTRL14_O 27_238
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK15.CLK_BUFG_BUFGCTRL15_O 27_254
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0 !26_07 26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 26_07 !26_08 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 26_07 !26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 !26_07 !26_08 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 !26_07 !26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 26_04 !26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 !26_04 26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 !26_04 !26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 !26_04 26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 !26_04 !26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 !26_23 26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 26_23 !26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 26_23 !26_24 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 !26_23 !26_24 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 !26_23 !26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 26_20 !26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 !26_20 !26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 !26_20 26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 !26_20 26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 !26_20 !26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 !26_39 26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 26_39 !26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 26_39 !26_40 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 !26_39 !26_40 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 !26_39 !26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 26_36 !26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 !26_36 !26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 !26_36 26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 !26_36 26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 !26_36 !26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 !26_55 26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 26_55 !26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 26_55 !26_56 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 !26_55 !26_56 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 !26_55 !26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 26_52 !26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 !26_52 !26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 !26_52 26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 !26_52 26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 !26_52 !26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 !26_71 26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 26_71 !26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 26_71 !26_72 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 !26_71 !26_72 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 !26_71 !26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 26_68 !26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 !26_68 !26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 !26_68 26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 !26_68 26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 !26_68 !26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 !26_87 26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 26_87 !26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 26_87 !26_88 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 !26_87 !26_88 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 !26_87 !26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 26_84 !26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 !26_84 !26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 !26_84 26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 !26_84 26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 !26_84 !26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 !26_103 26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 26_103 !26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 26_103 !26_104 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 !26_103 !26_104 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 !26_103 !26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 26_100 !26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 !26_100 !26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 !26_100 26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 !26_100 26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 !26_100 !26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 !26_119 26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 26_119 !26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 26_119 !26_120 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 !26_119 !26_120 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 !26_119 !26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 26_116 !26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 !26_116 !26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 !26_116 26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 !26_116 26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 !26_116 !26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 !26_135 26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 26_135 !26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 26_135 !26_136 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 !26_135 !26_136 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 !26_135 !26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 26_132 !26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 !26_132 !26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 !26_132 26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 !26_132 26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 !26_132 !26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 !26_151 26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 26_151 !26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 26_151 !26_152 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 !26_151 !26_152 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 !26_151 !26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 26_148 !26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 !26_148 !26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 !26_148 26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 !26_148 26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 !26_148 !26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 !26_167 26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 26_167 !26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 26_167 !26_168 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 !26_167 !26_168 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 !26_167 !26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 26_164 !26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 !26_164 !26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 !26_164 26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 !26_164 26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 !26_164 !26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 !26_183 26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 26_183 !26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 26_183 !26_184 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 !26_183 !26_184 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 !26_183 !26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 26_180 !26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 !26_180 !26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 !26_180 26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 !26_180 26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 !26_180 !26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 !26_199 26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 26_199 !26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 26_199 !26_200 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 !26_199 !26_200 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 !26_199 !26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 26_196 !26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 !26_196 !26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 !26_196 26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 !26_196 26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 !26_196 !26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 !26_215 26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 26_215 !26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 26_215 !26_216 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 !26_215 !26_216 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 !26_215 !26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 26_212 !26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 !26_212 !26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 !26_212 26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 !26_212 26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 !26_212 !26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 !26_231 26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 26_231 !26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 26_231 !26_232 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 !26_231 !26_232 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 !26_231 !26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 26_228 !26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 !26_228 !26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 !26_228 26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 !26_228 26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 !26_228 !26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 !26_247 26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 26_247 !26_248 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 26_247 !26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 !26_247 !26_248 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 !26_247 !26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 26_244 !26_245 !27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 !26_244 26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 !26_244 !26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 !26_244 26_245 !27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 !26_244 !26_245 !27_245

526
kintex7/segbits_clk_bufg_bot_r.origin_info.db
View File

@ -1,5 +1,5 @@
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT origin:042-clk-bufg-config 27_13
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_01
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_12
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 origin:042-clk-bufg-config 26_12
@ -8,98 +8,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 origin:042-clk-bufg-config 27_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 origin:042-clk-bufg-config 27_03
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 origin:042-clk-bufg-config 26_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 origin:042-clk-bufg-config 26_02
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT origin:042-clk-bufg-config 27_173
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_161
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_172
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 origin:042-clk-bufg-config 26_172
@ -108,8 +18,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 origin:042-clk-bufg-config 27_17
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 origin:042-clk-bufg-config 27_163
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 origin:042-clk-bufg-config 26_171
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 origin:042-clk-bufg-config 26_162
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT origin:042-clk-bufg-config 27_189
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_177
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_188
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 origin:042-clk-bufg-config 26_188
@ -118,8 +28,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 origin:042-clk-bufg-config 27_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 origin:042-clk-bufg-config 27_179
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 origin:042-clk-bufg-config 26_187
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 origin:042-clk-bufg-config 26_178
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT origin:042-clk-bufg-config 27_205
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_193
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_204
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 origin:042-clk-bufg-config 26_204
@ -128,8 +38,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 origin:042-clk-bufg-config 27_20
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 origin:042-clk-bufg-config 27_195
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 origin:042-clk-bufg-config 26_203
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 origin:042-clk-bufg-config 26_194
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT origin:042-clk-bufg-config 27_221
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_209
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_220
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 origin:042-clk-bufg-config 26_220
@ -138,8 +48,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 origin:042-clk-bufg-config 27_21
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 origin:042-clk-bufg-config 27_211
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 origin:042-clk-bufg-config 26_219
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 origin:042-clk-bufg-config 26_210
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT origin:042-clk-bufg-config 27_237
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_225
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_236
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 origin:042-clk-bufg-config 26_236
@ -148,8 +58,8 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 origin:042-clk-bufg-config 27_23
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 origin:042-clk-bufg-config 27_227
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 origin:042-clk-bufg-config 26_235
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 origin:042-clk-bufg-config 26_226
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT origin:042-clk-bufg-config 27_253
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_241
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 origin:042-clk-bufg-config 26_252
@ -158,7 +68,263 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 origin:042-clk-bufg-config 27_25
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 origin:042-clk-bufg-config 27_243
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 origin:042-clk-bufg-config 26_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 origin:042-clk-bufg-config 26_242
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0 origin:046-clk-bufg-muxed-pips !26_07 !27_06 26_08
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O origin:044-clk-bufg-pips 27_14
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK10.CLK_BUFG_BUFGCTRL10_O origin:044-clk-bufg-pips 27_174
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK11.CLK_BUFG_BUFGCTRL11_O origin:044-clk-bufg-pips 27_190
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK12.CLK_BUFG_BUFGCTRL12_O origin:044-clk-bufg-pips 27_206
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK13.CLK_BUFG_BUFGCTRL13_O origin:044-clk-bufg-pips 27_222
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK14.CLK_BUFG_BUFGCTRL14_O origin:044-clk-bufg-pips 27_238
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK15.CLK_BUFG_BUFGCTRL15_O origin:044-clk-bufg-pips 27_254
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK1.CLK_BUFG_BUFGCTRL1_O origin:044-clk-bufg-pips 27_30
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK2.CLK_BUFG_BUFGCTRL2_O origin:044-clk-bufg-pips 27_46
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK3.CLK_BUFG_BUFGCTRL3_O origin:044-clk-bufg-pips 27_62
@ -168,169 +334,3 @@ CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK6.CLK_BUFG_BUFGCTRL6_O origin:044-clk-bufg-pips 2
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK7.CLK_BUFG_BUFGCTRL7_O origin:044-clk-bufg-pips 27_126
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK8.CLK_BUFG_BUFGCTRL8_O origin:044-clk-bufg-pips 27_142
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK9.CLK_BUFG_BUFGCTRL9_O origin:044-clk-bufg-pips 27_158
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK10.CLK_BUFG_BUFGCTRL10_O origin:044-clk-bufg-pips 27_174
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK11.CLK_BUFG_BUFGCTRL11_O origin:044-clk-bufg-pips 27_190
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK12.CLK_BUFG_BUFGCTRL12_O origin:044-clk-bufg-pips 27_206
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK13.CLK_BUFG_BUFGCTRL13_O origin:044-clk-bufg-pips 27_222
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK14.CLK_BUFG_BUFGCTRL14_O origin:044-clk-bufg-pips 27_238
CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK15.CLK_BUFG_BUFGCTRL15_O origin:044-clk-bufg-pips 27_254
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0 origin:046-clk-bufg-muxed-pips !26_07 !27_06 26_08
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

72
kintex7/segbits_clk_bufg_rebuf.db
View File

@ -1,23 +1,5 @@
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT.CLK_BUFG_REBUF_R_CK_GCLK0_TOP 27_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT 27_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP 27_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT 27_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT.CLK_BUFG_REBUF_R_CK_GCLK2_TOP 27_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_TOP.CLK_BUFG_REBUF_R_CK_GCLK2_BOT 27_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT.CLK_BUFG_REBUF_R_CK_GCLK3_TOP 27_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP.CLK_BUFG_REBUF_R_CK_GCLK3_BOT 27_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT.CLK_BUFG_REBUF_R_CK_GCLK4_TOP 27_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_TOP.CLK_BUFG_REBUF_R_CK_GCLK4_BOT 27_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT.CLK_BUFG_REBUF_R_CK_GCLK5_TOP 27_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP.CLK_BUFG_REBUF_R_CK_GCLK5_BOT 27_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT.CLK_BUFG_REBUF_R_CK_GCLK6_TOP 27_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_TOP.CLK_BUFG_REBUF_R_CK_GCLK6_BOT 27_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT.CLK_BUFG_REBUF_R_CK_GCLK7_TOP 27_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP.CLK_BUFG_REBUF_R_CK_GCLK7_BOT 27_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT.CLK_BUFG_REBUF_R_CK_GCLK8_TOP 26_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_TOP.CLK_BUFG_REBUF_R_CK_GCLK8_BOT 26_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT.CLK_BUFG_REBUF_R_CK_GCLK9_TOP 26_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP.CLK_BUFG_REBUF_R_CK_GCLK9_BOT 26_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT.CLK_BUFG_REBUF_R_CK_GCLK10_TOP 26_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_TOP.CLK_BUFG_REBUF_R_CK_GCLK10_BOT 26_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT.CLK_BUFG_REBUF_R_CK_GCLK11_TOP 26_63
@ -38,6 +20,8 @@ CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT.CLK_BUFG_REBUF_R_CK_GCLK18_TOP 27_
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_TOP.CLK_BUFG_REBUF_R_CK_GCLK18_BOT 27_44
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT.CLK_BUFG_REBUF_R_CK_GCLK19_TOP 27_62
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP.CLK_BUFG_REBUF_R_CK_GCLK19_BOT 27_60
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP 27_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT 27_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT.CLK_BUFG_REBUF_R_CK_GCLK20_TOP 27_78
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_TOP.CLK_BUFG_REBUF_R_CK_GCLK20_BOT 27_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT.CLK_BUFG_REBUF_R_CK_GCLK21_TOP 27_94
@ -58,30 +42,28 @@ CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT.CLK_BUFG_REBUF_R_CK_GCLK28_TOP 26_
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_TOP.CLK_BUFG_REBUF_R_CK_GCLK28_BOT 26_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT.CLK_BUFG_REBUF_R_CK_GCLK29_TOP 26_94
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP.CLK_BUFG_REBUF_R_CK_GCLK29_BOT 26_92
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT.CLK_BUFG_REBUF_R_CK_GCLK2_TOP 27_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_TOP.CLK_BUFG_REBUF_R_CK_GCLK2_BOT 27_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT.CLK_BUFG_REBUF_R_CK_GCLK30_TOP 26_110
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_TOP.CLK_BUFG_REBUF_R_CK_GCLK30_BOT 26_108
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT.CLK_BUFG_REBUF_R_CK_GCLK31_TOP 26_126
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP.CLK_BUFG_REBUF_R_CK_GCLK31_BOT 26_124
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT.CLK_BUFG_REBUF_R_CK_GCLK3_TOP 27_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP.CLK_BUFG_REBUF_R_CK_GCLK3_BOT 27_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT.CLK_BUFG_REBUF_R_CK_GCLK4_TOP 27_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_TOP.CLK_BUFG_REBUF_R_CK_GCLK4_BOT 27_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT.CLK_BUFG_REBUF_R_CK_GCLK5_TOP 27_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP.CLK_BUFG_REBUF_R_CK_GCLK5_BOT 27_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT.CLK_BUFG_REBUF_R_CK_GCLK6_TOP 27_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_TOP.CLK_BUFG_REBUF_R_CK_GCLK6_BOT 27_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT.CLK_BUFG_REBUF_R_CK_GCLK7_TOP 27_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP.CLK_BUFG_REBUF_R_CK_GCLK7_BOT 27_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT.CLK_BUFG_REBUF_R_CK_GCLK8_TOP 26_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_TOP.CLK_BUFG_REBUF_R_CK_GCLK8_BOT 26_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT.CLK_BUFG_REBUF_R_CK_GCLK9_TOP 26_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP.CLK_BUFG_REBUF_R_CK_GCLK9_BOT 26_29
CLK_BUFG_REBUF.GCLK0_ENABLE_ABOVE 27_03
CLK_BUFG_REBUF.GCLK0_ENABLE_BELOW 27_01
CLK_BUFG_REBUF.GCLK1_ENABLE_ABOVE 27_19
CLK_BUFG_REBUF.GCLK1_ENABLE_BELOW 27_17
CLK_BUFG_REBUF.GCLK2_ENABLE_ABOVE 27_35
CLK_BUFG_REBUF.GCLK2_ENABLE_BELOW 27_33
CLK_BUFG_REBUF.GCLK3_ENABLE_ABOVE 27_51
CLK_BUFG_REBUF.GCLK3_ENABLE_BELOW 27_49
CLK_BUFG_REBUF.GCLK4_ENABLE_ABOVE 27_67
CLK_BUFG_REBUF.GCLK4_ENABLE_BELOW 27_65
CLK_BUFG_REBUF.GCLK5_ENABLE_ABOVE 27_83
CLK_BUFG_REBUF.GCLK5_ENABLE_BELOW 27_81
CLK_BUFG_REBUF.GCLK6_ENABLE_ABOVE 27_99
CLK_BUFG_REBUF.GCLK6_ENABLE_BELOW 27_97
CLK_BUFG_REBUF.GCLK7_ENABLE_ABOVE 27_115
CLK_BUFG_REBUF.GCLK7_ENABLE_BELOW 27_113
CLK_BUFG_REBUF.GCLK8_ENABLE_ABOVE 26_03
CLK_BUFG_REBUF.GCLK8_ENABLE_BELOW 26_01
CLK_BUFG_REBUF.GCLK9_ENABLE_ABOVE 26_19
CLK_BUFG_REBUF.GCLK9_ENABLE_BELOW 26_17
CLK_BUFG_REBUF.GCLK10_ENABLE_ABOVE 26_35
CLK_BUFG_REBUF.GCLK10_ENABLE_BELOW 26_33
CLK_BUFG_REBUF.GCLK11_ENABLE_ABOVE 26_51
@ -102,6 +84,8 @@ CLK_BUFG_REBUF.GCLK18_ENABLE_ABOVE 27_34
CLK_BUFG_REBUF.GCLK18_ENABLE_BELOW 27_32
CLK_BUFG_REBUF.GCLK19_ENABLE_ABOVE 27_50
CLK_BUFG_REBUF.GCLK19_ENABLE_BELOW 27_48
CLK_BUFG_REBUF.GCLK1_ENABLE_ABOVE 27_19
CLK_BUFG_REBUF.GCLK1_ENABLE_BELOW 27_17
CLK_BUFG_REBUF.GCLK20_ENABLE_ABOVE 27_66
CLK_BUFG_REBUF.GCLK20_ENABLE_BELOW 27_64
CLK_BUFG_REBUF.GCLK21_ENABLE_ABOVE 27_82
@ -122,7 +106,23 @@ CLK_BUFG_REBUF.GCLK28_ENABLE_ABOVE 26_66
CLK_BUFG_REBUF.GCLK28_ENABLE_BELOW 26_64
CLK_BUFG_REBUF.GCLK29_ENABLE_ABOVE 26_82
CLK_BUFG_REBUF.GCLK29_ENABLE_BELOW 26_80
CLK_BUFG_REBUF.GCLK2_ENABLE_ABOVE 27_35
CLK_BUFG_REBUF.GCLK2_ENABLE_BELOW 27_33
CLK_BUFG_REBUF.GCLK30_ENABLE_ABOVE 26_98
CLK_BUFG_REBUF.GCLK30_ENABLE_BELOW 26_96
CLK_BUFG_REBUF.GCLK31_ENABLE_ABOVE 26_114
CLK_BUFG_REBUF.GCLK31_ENABLE_BELOW 26_112
CLK_BUFG_REBUF.GCLK3_ENABLE_ABOVE 27_51
CLK_BUFG_REBUF.GCLK3_ENABLE_BELOW 27_49
CLK_BUFG_REBUF.GCLK4_ENABLE_ABOVE 27_67
CLK_BUFG_REBUF.GCLK4_ENABLE_BELOW 27_65
CLK_BUFG_REBUF.GCLK5_ENABLE_ABOVE 27_83
CLK_BUFG_REBUF.GCLK5_ENABLE_BELOW 27_81
CLK_BUFG_REBUF.GCLK6_ENABLE_ABOVE 27_99
CLK_BUFG_REBUF.GCLK6_ENABLE_BELOW 27_97
CLK_BUFG_REBUF.GCLK7_ENABLE_ABOVE 27_115
CLK_BUFG_REBUF.GCLK7_ENABLE_BELOW 27_113
CLK_BUFG_REBUF.GCLK8_ENABLE_ABOVE 26_03
CLK_BUFG_REBUF.GCLK8_ENABLE_BELOW 26_01
CLK_BUFG_REBUF.GCLK9_ENABLE_ABOVE 26_19
CLK_BUFG_REBUF.GCLK9_ENABLE_BELOW 26_17

72
kintex7/segbits_clk_bufg_rebuf.origin_info.db
View File

@ -1,23 +1,5 @@
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT.CLK_BUFG_REBUF_R_CK_GCLK0_TOP origin:043-clk-rebuf-pips 27_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT origin:043-clk-rebuf-pips 27_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP origin:043-clk-rebuf-pips 27_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT origin:043-clk-rebuf-pips 27_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT.CLK_BUFG_REBUF_R_CK_GCLK2_TOP origin:043-clk-rebuf-pips 27_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_TOP.CLK_BUFG_REBUF_R_CK_GCLK2_BOT origin:043-clk-rebuf-pips 27_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT.CLK_BUFG_REBUF_R_CK_GCLK3_TOP origin:043-clk-rebuf-pips 27_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP.CLK_BUFG_REBUF_R_CK_GCLK3_BOT origin:043-clk-rebuf-pips 27_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT.CLK_BUFG_REBUF_R_CK_GCLK4_TOP origin:043-clk-rebuf-pips 27_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_TOP.CLK_BUFG_REBUF_R_CK_GCLK4_BOT origin:043-clk-rebuf-pips 27_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT.CLK_BUFG_REBUF_R_CK_GCLK5_TOP origin:043-clk-rebuf-pips 27_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP.CLK_BUFG_REBUF_R_CK_GCLK5_BOT origin:043-clk-rebuf-pips 27_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT.CLK_BUFG_REBUF_R_CK_GCLK6_TOP origin:043-clk-rebuf-pips 27_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_TOP.CLK_BUFG_REBUF_R_CK_GCLK6_BOT origin:043-clk-rebuf-pips 27_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT.CLK_BUFG_REBUF_R_CK_GCLK7_TOP origin:043-clk-rebuf-pips 27_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP.CLK_BUFG_REBUF_R_CK_GCLK7_BOT origin:043-clk-rebuf-pips 27_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT.CLK_BUFG_REBUF_R_CK_GCLK8_TOP origin:043-clk-rebuf-pips 26_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_TOP.CLK_BUFG_REBUF_R_CK_GCLK8_BOT origin:043-clk-rebuf-pips 26_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT.CLK_BUFG_REBUF_R_CK_GCLK9_TOP origin:043-clk-rebuf-pips 26_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP.CLK_BUFG_REBUF_R_CK_GCLK9_BOT origin:043-clk-rebuf-pips 26_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT.CLK_BUFG_REBUF_R_CK_GCLK10_TOP origin:043-clk-rebuf-pips 26_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_TOP.CLK_BUFG_REBUF_R_CK_GCLK10_BOT origin:043-clk-rebuf-pips 26_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT.CLK_BUFG_REBUF_R_CK_GCLK11_TOP origin:043-clk-rebuf-pips 26_63
@ -38,6 +20,8 @@ CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT.CLK_BUFG_REBUF_R_CK_GCLK18_TOP ori
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_TOP.CLK_BUFG_REBUF_R_CK_GCLK18_BOT origin:043-clk-rebuf-pips 27_44
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT.CLK_BUFG_REBUF_R_CK_GCLK19_TOP origin:043-clk-rebuf-pips 27_62
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP.CLK_BUFG_REBUF_R_CK_GCLK19_BOT origin:043-clk-rebuf-pips 27_60
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP origin:043-clk-rebuf-pips 27_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT origin:043-clk-rebuf-pips 27_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT.CLK_BUFG_REBUF_R_CK_GCLK20_TOP origin:043-clk-rebuf-pips 27_78
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_TOP.CLK_BUFG_REBUF_R_CK_GCLK20_BOT origin:043-clk-rebuf-pips 27_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT.CLK_BUFG_REBUF_R_CK_GCLK21_TOP origin:043-clk-rebuf-pips 27_94
@ -58,30 +42,28 @@ CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT.CLK_BUFG_REBUF_R_CK_GCLK28_TOP ori
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_TOP.CLK_BUFG_REBUF_R_CK_GCLK28_BOT origin:043-clk-rebuf-pips 26_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT.CLK_BUFG_REBUF_R_CK_GCLK29_TOP origin:043-clk-rebuf-pips 26_94
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP.CLK_BUFG_REBUF_R_CK_GCLK29_BOT origin:043-clk-rebuf-pips 26_92
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT.CLK_BUFG_REBUF_R_CK_GCLK2_TOP origin:043-clk-rebuf-pips 27_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_TOP.CLK_BUFG_REBUF_R_CK_GCLK2_BOT origin:043-clk-rebuf-pips 27_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT.CLK_BUFG_REBUF_R_CK_GCLK30_TOP origin:043-clk-rebuf-pips 26_110
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_TOP.CLK_BUFG_REBUF_R_CK_GCLK30_BOT origin:043-clk-rebuf-pips 26_108
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT.CLK_BUFG_REBUF_R_CK_GCLK31_TOP origin:043-clk-rebuf-pips 26_126
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP.CLK_BUFG_REBUF_R_CK_GCLK31_BOT origin:043-clk-rebuf-pips 26_124
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT.CLK_BUFG_REBUF_R_CK_GCLK3_TOP origin:043-clk-rebuf-pips 27_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP.CLK_BUFG_REBUF_R_CK_GCLK3_BOT origin:043-clk-rebuf-pips 27_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT.CLK_BUFG_REBUF_R_CK_GCLK4_TOP origin:043-clk-rebuf-pips 27_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_TOP.CLK_BUFG_REBUF_R_CK_GCLK4_BOT origin:043-clk-rebuf-pips 27_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT.CLK_BUFG_REBUF_R_CK_GCLK5_TOP origin:043-clk-rebuf-pips 27_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP.CLK_BUFG_REBUF_R_CK_GCLK5_BOT origin:043-clk-rebuf-pips 27_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT.CLK_BUFG_REBUF_R_CK_GCLK6_TOP origin:043-clk-rebuf-pips 27_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_TOP.CLK_BUFG_REBUF_R_CK_GCLK6_BOT origin:043-clk-rebuf-pips 27_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT.CLK_BUFG_REBUF_R_CK_GCLK7_TOP origin:043-clk-rebuf-pips 27_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP.CLK_BUFG_REBUF_R_CK_GCLK7_BOT origin:043-clk-rebuf-pips 27_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT.CLK_BUFG_REBUF_R_CK_GCLK8_TOP origin:043-clk-rebuf-pips 26_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_TOP.CLK_BUFG_REBUF_R_CK_GCLK8_BOT origin:043-clk-rebuf-pips 26_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT.CLK_BUFG_REBUF_R_CK_GCLK9_TOP origin:043-clk-rebuf-pips 26_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP.CLK_BUFG_REBUF_R_CK_GCLK9_BOT origin:043-clk-rebuf-pips 26_29
CLK_BUFG_REBUF.GCLK0_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_03
CLK_BUFG_REBUF.GCLK0_ENABLE_BELOW origin:043-clk-rebuf-pips 27_01
CLK_BUFG_REBUF.GCLK1_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_19
CLK_BUFG_REBUF.GCLK1_ENABLE_BELOW origin:043-clk-rebuf-pips 27_17
CLK_BUFG_REBUF.GCLK2_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_35
CLK_BUFG_REBUF.GCLK2_ENABLE_BELOW origin:043-clk-rebuf-pips 27_33
CLK_BUFG_REBUF.GCLK3_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_51
CLK_BUFG_REBUF.GCLK3_ENABLE_BELOW origin:043-clk-rebuf-pips 27_49
CLK_BUFG_REBUF.GCLK4_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_67
CLK_BUFG_REBUF.GCLK4_ENABLE_BELOW origin:043-clk-rebuf-pips 27_65
CLK_BUFG_REBUF.GCLK5_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_83
CLK_BUFG_REBUF.GCLK5_ENABLE_BELOW origin:043-clk-rebuf-pips 27_81
CLK_BUFG_REBUF.GCLK6_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_99
CLK_BUFG_REBUF.GCLK6_ENABLE_BELOW origin:043-clk-rebuf-pips 27_97
CLK_BUFG_REBUF.GCLK7_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_115
CLK_BUFG_REBUF.GCLK7_ENABLE_BELOW origin:043-clk-rebuf-pips 27_113
CLK_BUFG_REBUF.GCLK8_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_03
CLK_BUFG_REBUF.GCLK8_ENABLE_BELOW origin:043-clk-rebuf-pips 26_01
CLK_BUFG_REBUF.GCLK9_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_19
CLK_BUFG_REBUF.GCLK9_ENABLE_BELOW origin:043-clk-rebuf-pips 26_17
CLK_BUFG_REBUF.GCLK10_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_35
CLK_BUFG_REBUF.GCLK10_ENABLE_BELOW origin:043-clk-rebuf-pips 26_33
CLK_BUFG_REBUF.GCLK11_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_51
@ -102,6 +84,8 @@ CLK_BUFG_REBUF.GCLK18_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_34
CLK_BUFG_REBUF.GCLK18_ENABLE_BELOW origin:043-clk-rebuf-pips 27_32
CLK_BUFG_REBUF.GCLK19_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_50
CLK_BUFG_REBUF.GCLK19_ENABLE_BELOW origin:043-clk-rebuf-pips 27_48
CLK_BUFG_REBUF.GCLK1_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_19
CLK_BUFG_REBUF.GCLK1_ENABLE_BELOW origin:043-clk-rebuf-pips 27_17
CLK_BUFG_REBUF.GCLK20_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_66
CLK_BUFG_REBUF.GCLK20_ENABLE_BELOW origin:043-clk-rebuf-pips 27_64
CLK_BUFG_REBUF.GCLK21_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_82
@ -122,7 +106,23 @@ CLK_BUFG_REBUF.GCLK28_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_66
CLK_BUFG_REBUF.GCLK28_ENABLE_BELOW origin:043-clk-rebuf-pips 26_64
CLK_BUFG_REBUF.GCLK29_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_82
CLK_BUFG_REBUF.GCLK29_ENABLE_BELOW origin:043-clk-rebuf-pips 26_80
CLK_BUFG_REBUF.GCLK2_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_35
CLK_BUFG_REBUF.GCLK2_ENABLE_BELOW origin:043-clk-rebuf-pips 27_33
CLK_BUFG_REBUF.GCLK30_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_98
CLK_BUFG_REBUF.GCLK30_ENABLE_BELOW origin:043-clk-rebuf-pips 26_96
CLK_BUFG_REBUF.GCLK31_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_114
CLK_BUFG_REBUF.GCLK31_ENABLE_BELOW origin:043-clk-rebuf-pips 26_112
CLK_BUFG_REBUF.GCLK3_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_51
CLK_BUFG_REBUF.GCLK3_ENABLE_BELOW origin:043-clk-rebuf-pips 27_49
CLK_BUFG_REBUF.GCLK4_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_67
CLK_BUFG_REBUF.GCLK4_ENABLE_BELOW origin:043-clk-rebuf-pips 27_65
CLK_BUFG_REBUF.GCLK5_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_83
CLK_BUFG_REBUF.GCLK5_ENABLE_BELOW origin:043-clk-rebuf-pips 27_81
CLK_BUFG_REBUF.GCLK6_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_99
CLK_BUFG_REBUF.GCLK6_ENABLE_BELOW origin:043-clk-rebuf-pips 27_97
CLK_BUFG_REBUF.GCLK7_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_115
CLK_BUFG_REBUF.GCLK7_ENABLE_BELOW origin:043-clk-rebuf-pips 27_113
CLK_BUFG_REBUF.GCLK8_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_03
CLK_BUFG_REBUF.GCLK8_ENABLE_BELOW origin:043-clk-rebuf-pips 26_01
CLK_BUFG_REBUF.GCLK9_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_19
CLK_BUFG_REBUF.GCLK9_ENABLE_BELOW origin:043-clk-rebuf-pips 26_17

514
kintex7/segbits_clk_bufg_top_r.db
View File

@ -1,5 +1,5 @@
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE 27_00 27_15
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT 27_13
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE 27_00 27_15
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED 26_01
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED 27_12
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 26_12
@ -8,98 +8,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 27_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 27_03
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 26_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 26_02
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE 27_16 27_31
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT 27_29
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED 26_17
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED 27_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 26_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 27_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 27_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 27_19
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 26_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 26_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE 27_32 27_47
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT 27_45
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED 26_33
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED 27_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 26_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 27_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 27_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 27_35
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 26_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 26_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE 27_48 27_63
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT 27_61
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED 26_49
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED 27_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 26_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 27_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 27_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 27_51
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 26_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 26_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE 27_64 27_79
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT 27_77
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED 26_65
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED 27_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 26_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 27_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 27_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 27_67
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 26_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 26_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE 27_80 27_95
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT 27_93
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED 26_81
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED 27_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 26_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 27_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 27_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 27_83
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 26_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 26_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE 27_96 27_111
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT 27_109
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED 26_97
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED 27_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 26_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 27_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 27_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 27_99
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 26_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 26_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE 27_112 27_127
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT 27_125
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED 26_113
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED 27_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 26_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 27_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 27_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 27_115
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 26_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 26_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE 27_128 27_143
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT 27_141
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED 26_129
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED 27_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 26_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 27_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 27_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 27_131
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 26_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 26_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE 27_144 27_159
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT 27_157
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED 26_145
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED 27_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 26_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 27_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 27_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 27_147
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 26_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 26_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE 27_160 27_175
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT 27_173
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE 27_160 27_175
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED 26_161
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED 27_172
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 26_172
@ -108,8 +18,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 27_171
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 27_163
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 26_171
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 26_162
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE 27_176 27_191
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT 27_189
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE 27_176 27_191
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED 26_177
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED 27_188
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 26_188
@ -118,8 +28,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 27_187
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 27_179
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 26_187
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 26_178
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE 27_192 27_207
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT 27_205
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE 27_192 27_207
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED 26_193
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED 27_204
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 26_204
@ -128,8 +38,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 27_203
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 27_195
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 26_203
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 26_194
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE 27_208 27_223
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT 27_221
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE 27_208 27_223
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED 26_209
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED 27_220
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 26_220
@ -138,8 +48,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 27_219
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 27_211
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 26_219
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 26_210
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE 27_224 27_239
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT 27_237
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE 27_224 27_239
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED 26_225
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED 27_236
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 26_236
@ -148,8 +58,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 27_235
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 27_227
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 26_235
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 26_226
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT 27_253
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED 26_241
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED 27_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 26_252
@ -158,6 +68,256 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 27_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 27_243
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 26_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 26_242
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT 27_29
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE 27_16 27_31
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED 26_17
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED 27_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 26_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 27_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 27_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 27_19
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 26_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 26_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT 27_45
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE 27_32 27_47
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED 26_33
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED 27_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 26_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 27_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 27_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 27_35
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 26_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 26_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT 27_61
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE 27_48 27_63
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED 26_49
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED 27_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 26_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 27_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 27_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 27_51
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 26_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 26_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT 27_77
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE 27_64 27_79
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED 26_65
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED 27_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 26_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 27_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 27_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 27_67
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 26_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 26_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT 27_93
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE 27_80 27_95
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED 26_81
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED 27_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 26_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 27_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 27_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 27_83
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 26_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 26_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT 27_109
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE 27_96 27_111
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED 26_97
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED 27_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 26_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 27_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 27_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 27_99
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 26_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 26_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT 27_125
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE 27_112 27_127
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED 26_113
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED 27_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 26_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 27_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 27_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 27_115
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 26_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 26_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT 27_141
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE 27_128 27_143
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED 26_129
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED 27_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 26_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 27_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 27_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 27_131
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 26_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 26_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT 27_157
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE 27_144 27_159
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED 26_145
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED 27_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 26_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 27_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 27_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 27_147
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 26_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 26_146
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 !26_07 !26_08 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 !26_07 !26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 26_07 !26_08 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 26_07 !26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 !26_07 26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 !26_04 26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 !26_04 !26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 !26_04 26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 !26_04 !26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 26_04 !26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 !26_167 !26_168 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 !26_167 !26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 26_167 !26_168 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 26_167 !26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 !26_167 26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 !26_164 26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 !26_164 !26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 !26_164 26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 !26_164 !26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 26_164 !26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 !26_183 !26_184 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 !26_183 !26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 26_183 !26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 26_183 !26_184 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 !26_183 26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 !26_180 26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 !26_180 !26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 !26_180 !26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 !26_180 26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 26_180 !26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 !26_199 !26_200 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 !26_199 !26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 26_199 !26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 26_199 !26_200 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 !26_199 26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 !26_196 26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 !26_196 !26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 !26_196 !26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 !26_196 26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 26_196 !26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 !26_215 !26_216 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 !26_215 !26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 26_215 !26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 26_215 !26_216 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 !26_215 26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 !26_212 26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 !26_212 !26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 !26_212 !26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 !26_212 26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 26_212 !26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 !26_231 !26_232 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 !26_231 !26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 26_231 !26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 26_231 !26_232 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 !26_231 26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 !26_228 26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 !26_228 !26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 !26_228 !26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 !26_228 26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 26_228 !26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 !26_247 !26_248 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 !26_247 !26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 26_247 !26_248 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 26_247 !26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 !26_247 26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 !26_244 26_245 !27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 !26_244 !26_245 !27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 !26_244 26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 !26_244 !26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 26_244 !26_245 !27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 !26_23 !26_24 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 !26_23 !26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 26_23 !26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 26_23 !26_24 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 !26_23 26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 !26_20 26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 !26_20 !26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 !26_20 !26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 !26_20 26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 26_20 !26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 !26_39 !26_40 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 !26_39 !26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 26_39 !26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 26_39 !26_40 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 !26_39 26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 !26_36 26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 !26_36 !26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 !26_36 !26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 !26_36 26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 26_36 !26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 !26_55 !26_56 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 !26_55 !26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 26_55 !26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 26_55 !26_56 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 !26_55 26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 !26_52 26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 !26_52 !26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 !26_52 !26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 !26_52 26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 26_52 !26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 !26_71 !26_72 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 !26_71 !26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 26_71 !26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 26_71 !26_72 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 !26_71 26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 !26_68 26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 !26_68 !26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 !26_68 !26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 !26_68 26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 26_68 !26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 !26_87 !26_88 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 !26_87 !26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 26_87 !26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 26_87 !26_88 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 !26_87 26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 !26_84 26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 !26_84 !26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 !26_84 !26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 !26_84 26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 26_84 !26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 !26_103 !26_104 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 !26_103 !26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 26_103 !26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 26_103 !26_104 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 !26_103 26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 !26_100 26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 !26_100 !26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 !26_100 !26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 !26_100 26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 26_100 !26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 !26_119 !26_120 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 !26_119 !26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 26_119 !26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 26_119 !26_120 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 !26_119 26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 !26_116 26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 !26_116 !26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 !26_116 !26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 !26_116 26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 26_116 !26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 !26_135 !26_136 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 !26_135 !26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 26_135 !26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 26_135 !26_136 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 !26_135 26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 !26_132 26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 !26_132 !26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 !26_132 !26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 !26_132 26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 26_132 !26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 !26_151 !26_152 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 !26_151 !26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 26_151 !26_152 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 26_151 !26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 !26_151 26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 !26_148 26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 !26_148 !26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 !26_148 26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 !26_148 !26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 26_148 !26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O 27_14
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK17.CLK_BUFG_BUFGCTRL1_O 27_30
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK18.CLK_BUFG_BUFGCTRL2_O 27_46
@ -174,163 +334,3 @@ CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK28.CLK_BUFG_BUFGCTRL12_O 27_206
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK29.CLK_BUFG_BUFGCTRL13_O 27_222
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK30.CLK_BUFG_BUFGCTRL14_O 27_238
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK31.CLK_BUFG_BUFGCTRL15_O 27_254
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 26_07 !26_08 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 26_07 !26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 !26_07 26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 !26_07 !26_08 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 !26_07 !26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 !26_04 26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 !26_04 !26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 26_04 !26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 !26_04 26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 !26_04 !26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 26_23 !26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 26_23 !26_24 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 !26_23 26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 !26_23 !26_24 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 !26_23 !26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 !26_20 !26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 !26_20 26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 26_20 !26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 !26_20 26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 !26_20 !26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 26_39 !26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 26_39 !26_40 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 !26_39 26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 !26_39 !26_40 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 !26_39 !26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 !26_36 !26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 !26_36 26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 26_36 !26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 !26_36 26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 !26_36 !26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 26_55 !26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 26_55 !26_56 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 !26_55 26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 !26_55 !26_56 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 !26_55 !26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 !26_52 !26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 !26_52 26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 26_52 !26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 !26_52 26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 !26_52 !26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 26_71 !26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 26_71 !26_72 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 !26_71 26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 !26_71 !26_72 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 !26_71 !26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 !26_68 !26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 !26_68 26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 26_68 !26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 !26_68 26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 !26_68 !26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 26_87 !26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 26_87 !26_88 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 !26_87 26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 !26_87 !26_88 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 !26_87 !26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 !26_84 !26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 !26_84 26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 26_84 !26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 !26_84 26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 !26_84 !26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 26_103 !26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 26_103 !26_104 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 !26_103 26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 !26_103 !26_104 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 !26_103 !26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 !26_100 !26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 !26_100 26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 26_100 !26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 !26_100 26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 !26_100 !26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 26_119 !26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 26_119 !26_120 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 !26_119 26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 !26_119 !26_120 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 !26_119 !26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 !26_116 !26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 !26_116 26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 26_116 !26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 !26_116 26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 !26_116 !26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 26_135 !26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 26_135 !26_136 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 !26_135 26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 !26_135 !26_136 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 !26_135 !26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 !26_132 !26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 !26_132 26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 26_132 !26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 !26_132 26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 !26_132 !26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 26_151 !26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 26_151 !26_152 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 !26_151 26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 !26_151 !26_152 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 !26_151 !26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 !26_148 !26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 !26_148 26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 26_148 !26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 !26_148 26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 !26_148 !26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 26_167 !26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 26_167 !26_168 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 !26_167 26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 !26_167 !26_168 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 !26_167 !26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 !26_164 !26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 !26_164 26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 26_164 !26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 !26_164 26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 !26_164 !26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 26_183 !26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 26_183 !26_184 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 !26_183 26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 !26_183 !26_184 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 !26_183 !26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 !26_180 !26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 !26_180 26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 26_180 !26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 !26_180 26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 !26_180 !26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 26_199 !26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 26_199 !26_200 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 !26_199 26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 !26_199 !26_200 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 !26_199 !26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 !26_196 !26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 !26_196 26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 26_196 !26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 !26_196 26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 !26_196 !26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 26_215 !26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 26_215 !26_216 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 !26_215 26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 !26_215 !26_216 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 !26_215 !26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 !26_212 !26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 !26_212 26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 26_212 !26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 !26_212 26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 !26_212 !26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 26_231 !26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 26_231 !26_232 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 !26_231 26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 !26_231 !26_232 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 !26_231 !26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 !26_228 !26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 !26_228 26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 26_228 !26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 !26_228 26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 !26_228 !26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 26_247 !26_248 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 26_247 !26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 !26_247 26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 !26_247 !26_248 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 !26_247 !26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 !26_244 26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 !26_244 !26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 26_244 !26_245 !27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 !26_244 26_245 !27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 !26_244 !26_245 !27_245

514
kintex7/segbits_clk_bufg_top_r.origin_info.db
View File

@ -1,5 +1,5 @@
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT origin:042-clk-bufg-config 27_13
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_01
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_12
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 origin:042-clk-bufg-config 26_12
@ -8,98 +8,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 origin:042-clk-bufg-config 27_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 origin:042-clk-bufg-config 27_03
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 origin:042-clk-bufg-config 26_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 origin:042-clk-bufg-config 26_02
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT origin:042-clk-bufg-config 27_173
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_161
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_172
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 origin:042-clk-bufg-config 26_172
@ -108,8 +18,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 origin:042-clk-bufg-config 27_17
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 origin:042-clk-bufg-config 27_163
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 origin:042-clk-bufg-config 26_171
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 origin:042-clk-bufg-config 26_162
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT origin:042-clk-bufg-config 27_189
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_177
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_188
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 origin:042-clk-bufg-config 26_188
@ -118,8 +28,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 origin:042-clk-bufg-config 27_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 origin:042-clk-bufg-config 27_179
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 origin:042-clk-bufg-config 26_187
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 origin:042-clk-bufg-config 26_178
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT origin:042-clk-bufg-config 27_205
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_193
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_204
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 origin:042-clk-bufg-config 26_204
@ -128,8 +38,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 origin:042-clk-bufg-config 27_20
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 origin:042-clk-bufg-config 27_195
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 origin:042-clk-bufg-config 26_203
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 origin:042-clk-bufg-config 26_194
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT origin:042-clk-bufg-config 27_221
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_209
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_220
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 origin:042-clk-bufg-config 26_220
@ -138,8 +48,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 origin:042-clk-bufg-config 27_21
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 origin:042-clk-bufg-config 27_211
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 origin:042-clk-bufg-config 26_219
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 origin:042-clk-bufg-config 26_210
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT origin:042-clk-bufg-config 27_237
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_225
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_236
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 origin:042-clk-bufg-config 26_236
@ -148,8 +58,8 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 origin:042-clk-bufg-config 27_23
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 origin:042-clk-bufg-config 27_227
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 origin:042-clk-bufg-config 26_235
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 origin:042-clk-bufg-config 26_226
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT origin:042-clk-bufg-config 27_253
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_241
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 origin:042-clk-bufg-config 26_252
@ -158,6 +68,256 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 origin:042-clk-bufg-config 27_25
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 origin:042-clk-bufg-config 27_243
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 origin:042-clk-bufg-config 26_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 origin:042-clk-bufg-config 26_242
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 origin:046-clk-bufg-muxed-pips !26_07 !27_06 26_08
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O origin:044-clk-bufg-pips 27_14
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK17.CLK_BUFG_BUFGCTRL1_O origin:044-clk-bufg-pips 27_30
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK18.CLK_BUFG_BUFGCTRL2_O origin:044-clk-bufg-pips 27_46
@ -174,163 +334,3 @@ CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK28.CLK_BUFG_BUFGCTRL12_O origin:044-clk-bufg-pips
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK29.CLK_BUFG_BUFGCTRL13_O origin:044-clk-bufg-pips 27_222
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK30.CLK_BUFG_BUFGCTRL14_O origin:044-clk-bufg-pips 27_238
CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK31.CLK_BUFG_BUFGCTRL15_O origin:044-clk-bufg-pips 27_254
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 origin:046-clk-bufg-muxed-pips !26_07 !27_06 26_08
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

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kintex7/segbits_clk_hrow_bot_r.db
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kintex7/segbits_clk_hrow_bot_r.origin_info.db
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kintex7/segbits_clk_hrow_top_r.db
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kintex7/segbits_clk_hrow_top_r.origin_info.db
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