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Added Kintex 7 PCIe segbits/tilegrid and GTX bit fixes

This commit is contained in:
regymm 2026-04-23 22:38:24 +09:00
parent 9b05f44f58
commit 6c02fde263
15 changed files with 10424 additions and 656 deletions
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1711
kintex7/mask_pcie_bot.db Normal file
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File diff suppressed because it is too large Load Diff

5
kintex7/segbits_gtx_channel_0.db
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@ -640,13 +640,16 @@ GTX_CHANNEL_0.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653
GTX_CHANNEL_0.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224
GTX_CHANNEL_0.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224
GTX_CHANNEL_0.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225
GTX_CHANNEL_0.GTXE2_CHANNEL.GTREFCLK0_USED 31_09
GTX_CHANNEL_0.GTXE2_CHANNEL.GTREFCLK1_USED 30_10
GTX_CHANNEL_0.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00
GTX_CHANNEL_0.GTXE2_CHANNEL.INV_DRPCLK 31_01
GTX_CHANNEL_0.GTXE2_CHANNEL.INV_RXUSRCLK 31_04
GTX_CHANNEL_0.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05
GTX_CHANNEL_0.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06
GTX_CHANNEL_0.GTXE2_CHANNEL.INV_TXUSRCLK 31_07
GTX_CHANNEL_0.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08
GTX_CHANNEL_0.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00
GTX_CHANNEL_0.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129
GTX_CHANNEL_0.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149
GTX_CHANNEL_0.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149
GTX_CHANNEL_0.GTXE2_CHANNEL.PCS_PCIE_EN 28_216

5
kintex7/segbits_gtx_channel_1.db
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@ -640,13 +640,16 @@ GTX_CHANNEL_1.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653
GTX_CHANNEL_1.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224
GTX_CHANNEL_1.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224
GTX_CHANNEL_1.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225
GTX_CHANNEL_1.GTXE2_CHANNEL.GTREFCLK0_USED 31_09
GTX_CHANNEL_1.GTXE2_CHANNEL.GTREFCLK1_USED 30_10
GTX_CHANNEL_1.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00
GTX_CHANNEL_1.GTXE2_CHANNEL.INV_DRPCLK 31_01
GTX_CHANNEL_1.GTXE2_CHANNEL.INV_RXUSRCLK 31_04
GTX_CHANNEL_1.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05
GTX_CHANNEL_1.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06
GTX_CHANNEL_1.GTXE2_CHANNEL.INV_TXUSRCLK 31_07
GTX_CHANNEL_1.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08
GTX_CHANNEL_1.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00
GTX_CHANNEL_1.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129
GTX_CHANNEL_1.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149
GTX_CHANNEL_1.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149
GTX_CHANNEL_1.GTXE2_CHANNEL.PCS_PCIE_EN 28_216

5
kintex7/segbits_gtx_channel_2.db
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@ -640,13 +640,16 @@ GTX_CHANNEL_2.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653
GTX_CHANNEL_2.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224
GTX_CHANNEL_2.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224
GTX_CHANNEL_2.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225
GTX_CHANNEL_2.GTXE2_CHANNEL.GTREFCLK0_USED 31_09
GTX_CHANNEL_2.GTXE2_CHANNEL.GTREFCLK1_USED 30_10
GTX_CHANNEL_2.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00
GTX_CHANNEL_2.GTXE2_CHANNEL.INV_DRPCLK 31_01
GTX_CHANNEL_2.GTXE2_CHANNEL.INV_RXUSRCLK 31_04
GTX_CHANNEL_2.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05
GTX_CHANNEL_2.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06
GTX_CHANNEL_2.GTXE2_CHANNEL.INV_TXUSRCLK 31_07
GTX_CHANNEL_2.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08
GTX_CHANNEL_2.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00
GTX_CHANNEL_2.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129
GTX_CHANNEL_2.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149
GTX_CHANNEL_2.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149
GTX_CHANNEL_2.GTXE2_CHANNEL.PCS_PCIE_EN 28_216

5
kintex7/segbits_gtx_channel_3.db
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@ -640,13 +640,16 @@ GTX_CHANNEL_3.GTXE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653
GTX_CHANNEL_3.GTXE2_CHANNEL.GEARBOX_MODE[0] 28_224
GTX_CHANNEL_3.GTXE2_CHANNEL.GEARBOX_MODE[1] 29_224
GTX_CHANNEL_3.GTXE2_CHANNEL.GEARBOX_MODE[2] 28_225
GTX_CHANNEL_3.GTXE2_CHANNEL.GTREFCLK0_USED 31_09
GTX_CHANNEL_3.GTXE2_CHANNEL.GTREFCLK1_USED 30_10
GTX_CHANNEL_3.GTXE2_CHANNEL.INV_CPLLLOCKDETCLK 31_00
GTX_CHANNEL_3.GTXE2_CHANNEL.INV_DRPCLK 31_01
GTX_CHANNEL_3.GTXE2_CHANNEL.INV_RXUSRCLK 31_04
GTX_CHANNEL_3.GTXE2_CHANNEL.INV_RXUSRCLK2 30_05
GTX_CHANNEL_3.GTXE2_CHANNEL.INV_TXPHDLYTSTCLK 30_06
GTX_CHANNEL_3.GTXE2_CHANNEL.INV_TXUSRCLK 31_07
GTX_CHANNEL_3.GTXE2_CHANNEL.INV_TXUSRCLK2 30_08
GTX_CHANNEL_3.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129 31_00
GTX_CHANNEL_3.GTXE2_CHANNEL.IN_USE 28_00 28_01 28_58 28_62 28_63 28_76 29_01 29_57 30_129
GTX_CHANNEL_3.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149
GTX_CHANNEL_3.GTXE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149
GTX_CHANNEL_3.GTXE2_CHANNEL.PCS_PCIE_EN 28_216

1711
kintex7/segbits_pcie_bot.db Normal file
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File diff suppressed because it is too large Load Diff

1711
kintex7/segbits_pcie_bot.origin_info.db Normal file
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File diff suppressed because it is too large Load Diff

27
kintex7/segbits_pcie_int_interface_l.db Normal file
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@ -0,0 +1,27 @@
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L_DELAY0 26_00
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L_DELAY1 27_08
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L_DELAY2 27_16
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L_DELAY3 27_24
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L_DELAY4 26_32
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L_DELAY5 27_40
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L_DELAY6 27_48
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L_DELAY7 27_56
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L_DELAY8 26_02
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L_DELAY9 26_10
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L_DELAY10 26_18
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L_DELAY11 26_26
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L_DELAY12 26_34
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L_DELAY13 26_42
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_DELAY14 26_50
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 26_58
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 26_03
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 26_11
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 26_19
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 27_05
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 27_13
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L_DELAY34 27_21
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L_DELAY35 27_29
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L_DELAY36 27_37
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L_DELAY37 27_45
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L_DELAY38 27_53
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L_DELAY39 27_61

27
kintex7/segbits_pcie_int_interface_l.origin_info.db Normal file
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@ -0,0 +1,27 @@
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L_DELAY0 origin:062-pcie-int-pips 26_00
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L_DELAY1 origin:062-pcie-int-pips 27_08
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L_DELAY2 origin:062-pcie-int-pips 27_16
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L_DELAY3 origin:062-pcie-int-pips 27_24
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L_DELAY4 origin:062-pcie-int-pips 26_32
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L_DELAY5 origin:062-pcie-int-pips 27_40
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L_DELAY6 origin:062-pcie-int-pips 27_48
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L_DELAY7 origin:062-pcie-int-pips 27_56
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L_DELAY8 origin:062-pcie-int-pips 26_02
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L_DELAY9 origin:062-pcie-int-pips 26_10
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L_DELAY10 origin:062-pcie-int-pips 26_18
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L_DELAY11 origin:062-pcie-int-pips 26_26
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L_DELAY12 origin:062-pcie-int-pips 26_34
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L_DELAY13 origin:062-pcie-int-pips 26_42
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_DELAY14 origin:062-pcie-int-pips 26_50
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 origin:062-pcie-int-pips 26_58
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 origin:062-pcie-int-pips 26_03
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 origin:062-pcie-int-pips 26_11
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 origin:062-pcie-int-pips 26_19
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 origin:062-pcie-int-pips 27_05
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 origin:062-pcie-int-pips 27_13
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L_DELAY34 origin:062-pcie-int-pips 27_21
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L_DELAY35 origin:062-pcie-int-pips 27_29
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L_DELAY36 origin:062-pcie-int-pips 27_37
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L_DELAY37 origin:062-pcie-int-pips 27_45
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L_DELAY38 origin:062-pcie-int-pips 27_53
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L_DELAY39 origin:062-pcie-int-pips 27_61

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kintex7/segbits_pcie_int_interface_r.db Normal file
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@ -0,0 +1,34 @@
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX_DELAY0 26_00
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX_DELAY1 27_08
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX_DELAY2 27_16
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX_DELAY3 27_24
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX_DELAY4 26_32
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX_DELAY5 27_40
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX_DELAY6 27_48
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX_DELAY7 27_56
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX_DELAY8 26_02
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX_DELAY9 26_10
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX_DELAY10 26_18
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX_DELAY11 26_26
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX_DELAY12 26_34
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX_DELAY13 26_42
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX_DELAY14 26_50
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX_DELAY15 26_58
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX_DELAY16 26_03
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX_DELAY17 26_11
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX_DELAY18 26_19
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 26_27
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 26_35
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 26_43
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 26_51
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 26_59
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 27_04
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 27_12
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 27_05
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX_DELAY33 27_13
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX_DELAY34 27_21
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX_DELAY35 27_29
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX_DELAY36 27_37
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX_DELAY37 27_45
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX_DELAY38 27_53
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX_DELAY39 27_61

34
kintex7/segbits_pcie_int_interface_r.origin_info.db Normal file
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@ -0,0 +1,34 @@
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX_DELAY0 origin:062-pcie-int-pips 26_00
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX_DELAY1 origin:062-pcie-int-pips 27_08
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX_DELAY2 origin:062-pcie-int-pips 27_16
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX_DELAY3 origin:062-pcie-int-pips 27_24
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX_DELAY4 origin:062-pcie-int-pips 26_32
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX_DELAY5 origin:062-pcie-int-pips 27_40
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX_DELAY6 origin:062-pcie-int-pips 27_48
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX_DELAY7 origin:062-pcie-int-pips 27_56
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX_DELAY8 origin:062-pcie-int-pips 26_02
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX_DELAY9 origin:062-pcie-int-pips 26_10
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX_DELAY10 origin:062-pcie-int-pips 26_18
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX_DELAY11 origin:062-pcie-int-pips 26_26
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX_DELAY12 origin:062-pcie-int-pips 26_34
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX_DELAY13 origin:062-pcie-int-pips 26_42
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX_DELAY14 origin:062-pcie-int-pips 26_50
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX_DELAY15 origin:062-pcie-int-pips 26_58
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX_DELAY16 origin:062-pcie-int-pips 26_03
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX_DELAY17 origin:062-pcie-int-pips 26_11
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX_DELAY18 origin:062-pcie-int-pips 26_19
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 origin:062-pcie-int-pips 26_27
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 origin:062-pcie-int-pips 26_35
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 origin:062-pcie-int-pips 26_43
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 origin:062-pcie-int-pips 26_51
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 origin:062-pcie-int-pips 26_59
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 origin:062-pcie-int-pips 27_04
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 origin:062-pcie-int-pips 27_12
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 origin:062-pcie-int-pips 27_05
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX_DELAY33 origin:062-pcie-int-pips 27_13
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX_DELAY34 origin:062-pcie-int-pips 27_21
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX_DELAY35 origin:062-pcie-int-pips 27_29
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX_DELAY36 origin:062-pcie-int-pips 27_37
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX_DELAY37 origin:062-pcie-int-pips 27_45
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX_DELAY38 origin:062-pcie-int-pips 27_53
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX_DELAY39 origin:062-pcie-int-pips 27_61

459
kintex7/xc7k160t/tilegrid.json
View File

@ -730340,7 +730340,14 @@
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@ -730352,7 +730359,14 @@
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@ -730361,7 +730375,14 @@
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@ -730370,7 +730391,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730379,7 +730407,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730388,7 +730423,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730397,7 +730439,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730406,7 +730455,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730415,7 +730471,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730424,7 +730487,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730433,7 +730503,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730442,7 +730519,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730451,7 +730535,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730460,7 +730551,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730469,7 +730567,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730478,7 +730583,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730487,7 +730599,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730496,7 +730615,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730505,7 +730631,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730514,7 +730647,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730523,7 +730663,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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@ -730532,7 +730679,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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@ -730541,7 +730695,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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@ -730550,7 +730711,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730559,7 +730727,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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@ -730568,7 +730743,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730577,7 +730759,14 @@
"type": "PCIE_INT_INTERFACE_L"
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@ -730586,7 +730775,14 @@
"type": "PCIE_INT_INTERFACE_R"
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@ -730595,7 +730791,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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@ -730604,7 +730807,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730613,7 +730823,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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"pin_functions": {},
@ -730622,7 +730839,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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"words": 2
}
},
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"pin_functions": {},
@ -730631,7 +730855,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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"pin_functions": {},
@ -730640,7 +730871,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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"pin_functions": {},
@ -730649,7 +730887,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730658,7 +730903,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730667,7 +730919,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X55Y160": {
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}
},
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@ -730676,7 +730935,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730685,7 +730951,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730694,7 +730967,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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"pin_functions": {},
@ -730703,7 +730983,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730712,7 +730999,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730721,7 +731015,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730730,7 +731031,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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"pin_functions": {},
@ -730739,7 +731047,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X55Y168": {
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}
},
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"pin_functions": {},
@ -730748,7 +731063,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730757,7 +731079,14 @@
"type": "PCIE_INT_INTERFACE_R"
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},
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"pin_functions": {},
@ -730766,7 +731095,14 @@
"type": "PCIE_INT_INTERFACE_R"
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},
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@ -730775,7 +731111,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
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}
},
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@ -730784,7 +731127,14 @@
"type": "PCIE_INT_INTERFACE_R"
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},
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@ -730793,7 +731143,14 @@
"type": "PCIE_INT_INTERFACE_R"
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}
},
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"pin_functions": {},

468
kintex7/xc7k325t/tilegrid.json
View File

@ -1330839,7 +1330839,14 @@
"type": "NULL"
},
"PCIE_BOT_X189Y167": {
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}
},
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@ -1330851,7 +1330858,14 @@
"type": "PCIE_BOT"
},
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"offset": 0,
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}
},
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"pin_functions": {},
@ -1330860,7 +1330874,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y151": {
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}
},
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@ -1330869,7 +1330890,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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"words": 2
}
},
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@ -1330878,7 +1330906,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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"offset": 6,
"words": 2
}
},
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@ -1330887,7 +1330922,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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"offset": 8,
"words": 2
}
},
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"pin_functions": {},
@ -1330896,7 +1330938,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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"bits": {},
"bits": {
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"offset": 10,
"words": 2
}
},
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"pin_functions": {},
@ -1330905,7 +1330954,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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"bits": {
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"offset": 12,
"words": 2
}
},
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"pin_functions": {},
@ -1330914,7 +1330970,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 14,
"words": 2
}
},
"grid_x": 194,
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"pin_functions": {},
@ -1330923,7 +1330986,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y158": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 16,
"words": 2
}
},
"grid_x": 194,
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"pin_functions": {},
@ -1330932,7 +1331002,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y159": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 18,
"words": 2
}
},
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"pin_functions": {},
@ -1330941,7 +1331018,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y160": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 20,
"words": 2
}
},
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@ -1330950,7 +1331034,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y161": {
"bits": {},
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"CLB_IO_CLK": {
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"offset": 22,
"words": 2
}
},
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"pin_functions": {},
@ -1330959,7 +1331050,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
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"offset": 24,
"words": 2
}
},
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"pin_functions": {},
@ -1330968,7 +1331066,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y163": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 26,
"words": 2
}
},
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@ -1330977,7 +1331082,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y164": {
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"bits": {
"CLB_IO_CLK": {
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"offset": 28,
"words": 2
}
},
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"pin_functions": {},
@ -1330986,7 +1331098,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y165": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 30,
"words": 2
}
},
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"pin_functions": {},
@ -1330995,7 +1331114,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y166": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 32,
"words": 2
}
},
"grid_x": 194,
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"pin_functions": {},
@ -1331004,7 +1331130,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y167": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 34,
"words": 2
}
},
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"pin_functions": {},
@ -1331013,7 +1331146,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y168": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 36,
"words": 2
}
},
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"pin_functions": {},
@ -1331022,7 +1331162,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y169": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 38,
"words": 2
}
},
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"pin_functions": {},
@ -1331031,7 +1331178,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y170": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 40,
"words": 2
}
},
"grid_x": 194,
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"pin_functions": {},
@ -1331040,7 +1331194,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y171": {
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"bits": {
"CLB_IO_CLK": {
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"offset": 42,
"words": 2
}
},
"grid_x": 194,
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"pin_functions": {},
@ -1331049,7 +1331210,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y172": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 44,
"words": 2
}
},
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"pin_functions": {},
@ -1331058,7 +1331226,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y173": {
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"bits": {
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"offset": 46,
"words": 2
}
},
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"pin_functions": {},
@ -1331067,7 +1331242,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X80Y174": {
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"bits": {
"CLB_IO_CLK": {
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"offset": 48,
"words": 2
}
},
"grid_x": 194,
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"pin_functions": {},
@ -1331076,7 +1331258,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_R_X77Y150": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 0,
"words": 2
}
},
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"pin_functions": {},
@ -1331085,7 +1331274,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y151": {
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"bits": {
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"offset": 2,
"words": 2
}
},
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"pin_functions": {},
@ -1331094,7 +1331290,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y152": {
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"bits": {
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"words": 2
}
},
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"pin_functions": {},
@ -1331103,7 +1331306,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y153": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 6,
"words": 2
}
},
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"pin_functions": {},
@ -1331112,7 +1331322,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y154": {
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"offset": 8,
"words": 2
}
},
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"pin_functions": {},
@ -1331121,7 +1331338,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y155": {
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"words": 2
}
},
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"pin_functions": {},
@ -1331130,7 +1331354,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y156": {
"bits": {},
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"offset": 12,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331139,7 +1331370,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y157": {
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"bits": {
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"offset": 14,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331148,7 +1331386,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y158": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 16,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331157,7 +1331402,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y159": {
"bits": {},
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"offset": 18,
"words": 2
}
},
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"pin_functions": {},
@ -1331166,7 +1331418,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y160": {
"bits": {},
"bits": {
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"offset": 20,
"words": 2
}
},
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"pin_functions": {},
@ -1331175,7 +1331434,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y161": {
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"words": 2
}
},
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"pin_functions": {},
@ -1331184,7 +1331450,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y162": {
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"bits": {
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"words": 2
}
},
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"pin_functions": {},
@ -1331193,7 +1331466,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y163": {
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"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331202,7 +1331482,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y164": {
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"offset": 28,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331211,7 +1331498,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y165": {
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"bits": {
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"offset": 30,
"words": 2
}
},
"grid_x": 188,
"grid_y": 192,
"pin_functions": {},
@ -1331220,7 +1331514,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y166": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 32,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331229,7 +1331530,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y167": {
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"bits": {
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"frames": 28,
"offset": 34,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331238,7 +1331546,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y168": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 36,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331247,7 +1331562,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y169": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 38,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331256,7 +1331578,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y170": {
"bits": {},
"bits": {
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"offset": 40,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331265,7 +1331594,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y171": {
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"bits": {
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"offset": 42,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331274,7 +1331610,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y172": {
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"bits": {
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"offset": 44,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331283,7 +1331626,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y173": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 46,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1331292,7 +1331642,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X77Y174": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"offset": 48,
"words": 2
}
},
"grid_x": 188,
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"pin_functions": {},
@ -1334949,14 +1335306,7 @@
"type": "RIOI"
},
"RIOI_X95Y9": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00442F80",
"frames": 42,
"offset": 18,
"words": 4
}
},
"bits": {},
"clock_region": "X1Y0",
"grid_x": 235,
"grid_y": 354,

4419
kintex7/xc7k480t/tilegrid.json
View File

File diff suppressed because it is too large Load Diff

459
kintex7/xc7k70t/tilegrid.json
View File

@ -338034,7 +338034,14 @@
"type": "NULL"
},
"PCIE_BOT_X73Y115": {
"bits": {},
"bits": {
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"frames": 36,
"offset": 0,
"words": 101
}
},
"clock_region": "X1Y2",
"grid_x": 73,
"grid_y": 93,
@ -338046,7 +338053,14 @@
"type": "PCIE_BOT"
},
"PCIE_INT_INTERFACE_L_X30Y100": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 0,
"words": 2
}
},
"grid_x": 78,
"grid_y": 103,
"pin_functions": {},
@ -338055,7 +338069,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y101": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 2,
"words": 2
}
},
"grid_x": 78,
"grid_y": 102,
"pin_functions": {},
@ -338064,7 +338085,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y102": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 4,
"words": 2
}
},
"grid_x": 78,
"grid_y": 101,
"pin_functions": {},
@ -338073,7 +338101,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y103": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 6,
"words": 2
}
},
"grid_x": 78,
"grid_y": 100,
"pin_functions": {},
@ -338082,7 +338117,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y104": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
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"frames": 28,
"offset": 8,
"words": 2
}
},
"grid_x": 78,
"grid_y": 99,
"pin_functions": {},
@ -338091,7 +338133,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y105": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 10,
"words": 2
}
},
"grid_x": 78,
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@ -338100,7 +338149,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y106": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 12,
"words": 2
}
},
"grid_x": 78,
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"pin_functions": {},
@ -338109,7 +338165,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y107": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 14,
"words": 2
}
},
"grid_x": 78,
"grid_y": 96,
"pin_functions": {},
@ -338118,7 +338181,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y108": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 16,
"words": 2
}
},
"grid_x": 78,
"grid_y": 95,
"pin_functions": {},
@ -338127,7 +338197,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y109": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 18,
"words": 2
}
},
"grid_x": 78,
"grid_y": 94,
"pin_functions": {},
@ -338136,7 +338213,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y110": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 20,
"words": 2
}
},
"grid_x": 78,
"grid_y": 93,
"pin_functions": {},
@ -338145,7 +338229,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y111": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 22,
"words": 2
}
},
"grid_x": 78,
"grid_y": 92,
"pin_functions": {},
@ -338154,7 +338245,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y112": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 24,
"words": 2
}
},
"grid_x": 78,
"grid_y": 91,
"pin_functions": {},
@ -338163,7 +338261,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y113": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 26,
"words": 2
}
},
"grid_x": 78,
"grid_y": 90,
"pin_functions": {},
@ -338172,7 +338277,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y114": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 28,
"words": 2
}
},
"grid_x": 78,
"grid_y": 89,
"pin_functions": {},
@ -338181,7 +338293,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y115": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 30,
"words": 2
}
},
"grid_x": 78,
"grid_y": 88,
"pin_functions": {},
@ -338190,7 +338309,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y116": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 32,
"words": 2
}
},
"grid_x": 78,
"grid_y": 87,
"pin_functions": {},
@ -338199,7 +338325,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y117": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 34,
"words": 2
}
},
"grid_x": 78,
"grid_y": 86,
"pin_functions": {},
@ -338208,7 +338341,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y118": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 36,
"words": 2
}
},
"grid_x": 78,
"grid_y": 85,
"pin_functions": {},
@ -338217,7 +338357,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y119": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 38,
"words": 2
}
},
"grid_x": 78,
"grid_y": 84,
"pin_functions": {},
@ -338226,7 +338373,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y120": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 40,
"words": 2
}
},
"grid_x": 78,
"grid_y": 83,
"pin_functions": {},
@ -338235,7 +338389,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y121": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 42,
"words": 2
}
},
"grid_x": 78,
"grid_y": 82,
"pin_functions": {},
@ -338244,7 +338405,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y122": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 44,
"words": 2
}
},
"grid_x": 78,
"grid_y": 81,
"pin_functions": {},
@ -338253,7 +338421,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y123": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 46,
"words": 2
}
},
"grid_x": 78,
"grid_y": 80,
"pin_functions": {},
@ -338262,7 +338437,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_L_X30Y124": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000F00",
"frames": 28,
"offset": 48,
"words": 2
}
},
"grid_x": 78,
"grid_y": 79,
"pin_functions": {},
@ -338271,7 +338453,14 @@
"type": "PCIE_INT_INTERFACE_L"
},
"PCIE_INT_INTERFACE_R_X27Y100": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 0,
"words": 2
}
},
"grid_x": 72,
"grid_y": 103,
"pin_functions": {},
@ -338280,7 +338469,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y101": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 2,
"words": 2
}
},
"grid_x": 72,
"grid_y": 102,
"pin_functions": {},
@ -338289,7 +338485,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y102": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 4,
"words": 2
}
},
"grid_x": 72,
"grid_y": 101,
"pin_functions": {},
@ -338298,7 +338501,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y103": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 6,
"words": 2
}
},
"grid_x": 72,
"grid_y": 100,
"pin_functions": {},
@ -338307,7 +338517,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y104": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 8,
"words": 2
}
},
"grid_x": 72,
"grid_y": 99,
"pin_functions": {},
@ -338316,7 +338533,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y105": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 10,
"words": 2
}
},
"grid_x": 72,
"grid_y": 98,
"pin_functions": {},
@ -338325,7 +338549,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y106": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 12,
"words": 2
}
},
"grid_x": 72,
"grid_y": 97,
"pin_functions": {},
@ -338334,7 +338565,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y107": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 14,
"words": 2
}
},
"grid_x": 72,
"grid_y": 96,
"pin_functions": {},
@ -338343,7 +338581,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y108": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 16,
"words": 2
}
},
"grid_x": 72,
"grid_y": 95,
"pin_functions": {},
@ -338352,7 +338597,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y109": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 18,
"words": 2
}
},
"grid_x": 72,
"grid_y": 94,
"pin_functions": {},
@ -338361,7 +338613,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y110": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 20,
"words": 2
}
},
"grid_x": 72,
"grid_y": 93,
"pin_functions": {},
@ -338370,7 +338629,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y111": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 22,
"words": 2
}
},
"grid_x": 72,
"grid_y": 92,
"pin_functions": {},
@ -338379,7 +338645,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y112": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 24,
"words": 2
}
},
"grid_x": 72,
"grid_y": 91,
"pin_functions": {},
@ -338388,7 +338661,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y113": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 26,
"words": 2
}
},
"grid_x": 72,
"grid_y": 90,
"pin_functions": {},
@ -338397,7 +338677,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y114": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 28,
"words": 2
}
},
"grid_x": 72,
"grid_y": 89,
"pin_functions": {},
@ -338406,7 +338693,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y115": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 30,
"words": 2
}
},
"grid_x": 72,
"grid_y": 88,
"pin_functions": {},
@ -338415,7 +338709,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y116": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 32,
"words": 2
}
},
"grid_x": 72,
"grid_y": 87,
"pin_functions": {},
@ -338424,7 +338725,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y117": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 34,
"words": 2
}
},
"grid_x": 72,
"grid_y": 86,
"pin_functions": {},
@ -338433,7 +338741,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y118": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 36,
"words": 2
}
},
"grid_x": 72,
"grid_y": 85,
"pin_functions": {},
@ -338442,7 +338757,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y119": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 38,
"words": 2
}
},
"grid_x": 72,
"grid_y": 84,
"pin_functions": {},
@ -338451,7 +338773,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y120": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 40,
"words": 2
}
},
"grid_x": 72,
"grid_y": 83,
"pin_functions": {},
@ -338460,7 +338789,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y121": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 42,
"words": 2
}
},
"grid_x": 72,
"grid_y": 82,
"pin_functions": {},
@ -338469,7 +338805,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y122": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 44,
"words": 2
}
},
"grid_x": 72,
"grid_y": 81,
"pin_functions": {},
@ -338478,7 +338821,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y123": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 46,
"words": 2
}
},
"grid_x": 72,
"grid_y": 80,
"pin_functions": {},
@ -338487,7 +338837,14 @@
"type": "PCIE_INT_INTERFACE_R"
},
"PCIE_INT_INTERFACE_R_X27Y124": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000D80",
"frames": 28,
"offset": 48,
"words": 2
}
},
"grid_x": 72,
"grid_y": 79,
"pin_functions": {},