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kintex7: HP-bank IOB18/INT IOB_COL segbits (virtex7 arch mirror) 

RIOB18: IBUFDS_BANK_GLUE, LVDS/SSTL IN_DIFF + IN_ONLY groups,
LVCMOS12_LVCMOS15.IN, LVDS DRIVE/IN_USE, SSTL*.IN_USE, Y1
LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY, OBUF_HP_BANK_GLUE
Y0/Y1 and the LVCMOS-family SLEW.SLOW group (LIOB18 mirror).
INT_L/INT_R: IOB_COL_BANK_ACTIVE, IOB_COL_OBUF_CASCADE_Y1.

kintex7 and virtex7 are bit-identical for these tile types (55 shared
RIOB18 + 2020 shared INT_L + 2020 shared INT_R entries, zero
differences), so virtex7 fuzz data transfers directly.  Entries
validated with a Vivado 2017.2 golden bitstream on xc7k70tfbg676-2
(IBUFDS input, LVCMOS15/SSTL15 outputs on HP bank 33, SE input):
bitread + bit2fasm decode confirms OBUF_HP_BANK_GLUE, long SLEW.SLOW
group, Y1 IBUF_HP_BANK_GLUE and INT_R IOB_COL bits.  Origin tags
record provenance (virtex7-arch-mirror / liob18-arch-mirror).

Unblocks kintex7 open-flow builds using LVDS/diff clocks or HP-bank
pins (previously FasmLookupError in fasm2frames).
This commit is contained in:
Hans Baier 2026-08-06 20:01:27 +07:00
parent 7a36171801
commit 3bd17eb8d9
6 changed files with 32 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
kintex7/segbits_int_l.db
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@ -3634,3 +3634,5 @@ INT_L.WW4BEG3.SW2END2 02_49 04_49
INT_L.WW4BEG3.SW6END2 04_49 05_48
INT_L.WW4BEG3.WW2END2 03_48 03_49
INT_L.WW4BEG3.WW4END3 03_49 05_48
INT_L.IOB_COL_BANK_ACTIVE 38_012 38_032 38_034
INT_L.IOB_COL_OBUF_CASCADE_Y1 30_041 32_016 33_061

2
kintex7/segbits_int_l.origin_info.db
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@ -3634,3 +3634,5 @@ INT_L.WW4BEG3.SW2END2 origin:050-pip-seed 02_49 04_49
INT_L.WW4BEG3.SW6END2 origin:050-pip-seed 04_49 05_48
INT_L.WW4BEG3.WW2END2 origin:050-pip-seed 03_48 03_49
INT_L.WW4BEG3.WW4END3 origin:050-pip-seed 03_49 05_48
INT_L.IOB_COL_BANK_ACTIVE origin:virtex7-arch-mirror 38_012 38_032 38_034
INT_L.IOB_COL_OBUF_CASCADE_Y1 origin:virtex7-arch-mirror 30_041 32_016 33_061

2
kintex7/segbits_int_r.db
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@ -3634,3 +3634,5 @@ INT_R.WW4BEG3.SW2END2 02_49 04_49
INT_R.WW4BEG3.SW6END2 04_49 05_48
INT_R.WW4BEG3.WW2END2 03_48 03_49
INT_R.WW4BEG3.WW4END3 03_49 05_48
INT_R.IOB_COL_BANK_ACTIVE 38_012 38_032 38_034
INT_R.IOB_COL_OBUF_CASCADE_Y1 30_041 32_016 33_061

2
kintex7/segbits_int_r.origin_info.db
View File

@ -3634,3 +3634,5 @@ INT_R.WW4BEG3.SW2END2 origin:050-pip-seed 02_49 04_49
INT_R.WW4BEG3.SW6END2 origin:050-pip-seed 04_49 05_48
INT_R.WW4BEG3.WW2END2 origin:050-pip-seed 03_48 03_49
INT_R.WW4BEG3.WW4END3 origin:050-pip-seed 03_49 05_48
INT_R.IOB_COL_BANK_ACTIVE origin:virtex7-arch-mirror 38_012 38_032 38_034
INT_R.IOB_COL_OBUF_CASCADE_Y1 origin:virtex7-arch-mirror 30_041 32_016 33_061

12
kintex7/segbits_riob18.db
View File

@ -60,3 +60,15 @@ RIOB18.IOB_Y1.SSTL15.SLEW.FAST !38_38 !38_46 38_14 38_16 38_22 38_26 38_50 39_13
RIOB18.IOB_Y1.SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
RIOB18.IOB_Y1.ZIBUF_LOW_PWR 38_02
RIOB18.OUT_DIFF 39_17 39_43
RIOB18.IOB_Y0.IBUFDS_BANK_GLUE 38_008 38_028 38_040 39_015 39_021 39_037 39_041
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15.IN !39_01 38_126 39_127
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
RIOB18.IOB_Y0.LVDS.IN_DIFF !38_126 !39_127 39_01
RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN_DIFF !39_127 38_126 39_01
RIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN_DIFF 38_00 38_126 39_01
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY !38_30 !38_44 !39_23 !39_55 38_24 38_48 39_33 39_47 39_49
RIOB18.IOB_Y0.OBUF_HP_BANK_GLUE 31_086 32_066 33_111
RIOB18.IOB_Y1.OBUF_HP_BANK_GLUE 30_041 32_016 33_061
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_81 !39_89
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_14 !38_16 !38_22 !38_26 !38_38 !38_46 !38_50 !39_13 !39_45
RIOB18.IOB_Y1.IBUF_HP_BANK_GLUE 29_109

12
kintex7/segbits_riob18.origin_info.db
View File

@ -60,3 +60,15 @@ RIOB18.IOB_Y1.SSTL15.SLEW.FAST origin:030-iob18 !38_38 !38_46 38_14 38_16 38_22
RIOB18.IOB_Y1.SSTL15.SLEW.SLOW origin:030-iob18 !38_14 !38_16 !38_22 !38_26 !39_13 38_38 38_46 38_50 39_45
RIOB18.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob18 38_02
RIOB18.OUT_DIFF origin:030-iob18 39_17 39_43
RIOB18.IOB_Y0.IBUFDS_BANK_GLUE origin:virtex7-arch-mirror 38_008 38_028 38_040 39_015 39_021 39_037 39_041
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15.IN origin:virtex7-arch-mirror !39_01 38_126 39_127
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY origin:virtex7-arch-mirror !38_104 !38_72 !38_86 !39_73 !39_83 !39_93 !39_95 !39_97 38_78 38_80 38_94 39_103 39_79
RIOB18.IOB_Y0.LVDS.IN_DIFF origin:virtex7-arch-mirror !38_126 !39_127 39_01
RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN_DIFF origin:virtex7-arch-mirror !39_127 38_126 39_01
RIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN_DIFF origin:virtex7-arch-mirror 38_00 38_126 39_01
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY origin:kintex7-y1-in-only-mirror !38_30 !38_44 !39_23 !39_55 38_24 38_48 39_33 39_47 39_49
RIOB18.IOB_Y0.OBUF_HP_BANK_GLUE origin:liob18-arch-mirror 31_086 32_066 33_111
RIOB18.IOB_Y1.OBUF_HP_BANK_GLUE origin:liob18-arch-mirror 30_041 32_016 33_061
RIOB18.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:liob18-arch-mirror !38_114 !38_82 !39_101 !39_105 !39_111 !39_113 !39_77 !39_81 !39_89
RIOB18.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:liob18-arch-mirror !38_14 !38_16 !38_22 !38_26 !38_38 !38_46 !38_50 !39_13 !39_45
RIOB18.IOB_Y1.IBUF_HP_BANK_GLUE origin:liob18-arch-mirror-verify 29_109