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add virtex7, contribution courtesy Jonathan Kimmit

This commit is contained in:
Hans Baier 2026-07-28 07:04:52 +07:00
parent 5191a7ba8a
commit 7a36171801
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# Segbit fixes carried in this database
Substantive corrections this virtex7 DB carries over a stock prjxray fuzz.
These are what make the fully-open VC707 flow produce correct bitstreams.
(Commit hashes refer to the prjxray fuzzer-code repo that produced them.)
## CLB OUTMUX.O5 duplicate → incomplete encoding (`6fd1d26`)
The "telegraph bug." Duplicate `OUTMUX.O5` segbit definitions; last-wins
picked the incomplete one (missing the shared xMUX-enable bit) → output muxes
encoded as `0x55`. Fix: dedupe keeping the **complete** definition. This was
the root cause of long-chased open-flow output corruption.
## IOB18 OLOGIC SING-row segbits (`afb49cc`, fuzzer `036-iob18-ologic-sing`)
SING-row IOB18 sites had no OLOGIC segbits. Added via a dedicated sub-fuzzer.
## LIOI / RIOI OLOGIC inversion segbits (local fuzz, superset)
`segbits_lioi*.db` / `segbits_rioi_sing.db` gained the `OLOGIC_Y*.IS_*_INVERTED`
features (`IS_CLKDIV_INVERTED`, `IS_D1..D4_INVERTED`, etc.) — +88 lines per
file over the last release (216 vs 128). Plus `mask_lioi*.db` and
`tileconn.json`. This is why the build-area copy is a strict superset of the
released DB.
## LIOB18 / RIOB18 IOB_Y1 IN_ONLY (`09588f3`)
Dropped spurious bits `!38_32 !38_34` from the Y1 (slave-site) input-only
encoding, fixing left-HP single-ended LVCMOS inputs.
## Tilegrid SING propagation for HP-only LIOB18 / LIOI columns (`1c63972`, `1574e9c`)
Propagated SING-row bits and added the `iob18_sing` sub-fuzzer so HP-only
columns get correct SING-row geometry.
## Top-SING tile alias start_offset (OLOGIC/IOB "invalid word address")
`tilegrid.json`: the **top** SING-row tiles (`LIOI_SING`/`RIOI_SING`/`LIOB18_SING`/
`RIOB18_SING` at `bits.CLB_IO_CLK.offset == 99`) had alias `start_offset: 0`,
but it must be **2** (matching the bottom SING tiles at `offset 0`). With
`start_offset 0` the aliased regular OLOGIC_Y0 / IOB features (regular words
2–3) mapped to absolute frame words 101–102, which don't exist — fasm2frames
emitted `invalid word address` and silently dropped them (e.g. VC707 counter
LED on `LIOI_SING_X82Y51.OLOGIC_Y0.OMUX.D1`). With `start_offset 2` the
effective offset becomes `99-2=97`, so regular word 3 → abs 100, word 2 → abs
99 — landing in the tile's real 2-word window.
Confirmed empirically: fuzzer `036-iob18-ologic-sing` (re-run at N=50) places
`OLOGIC_Y0.OMUX.D1` at abs word 100, exactly what `start_offset 2` produces.
28 tiles fixed (7 each of LIOI/RIOI/LIOB18/RIOB18_SING). (The dedicated
`segbits_*_sing.db` are NOT consulted for aliased tiles, so this is a tilegrid
fix, not a segbits one.) Follow-up: fix the generator (`fuzzers/005-tilegrid`)
so a regenerated tilegrid doesn't reintroduce `start_offset 0`.
## Known remaining gap (worked around downstream, not yet fixed in DB)
LVCMOS18 single-ended **input** on certain HP-bank sites (e.g. AU33) is missing
segbit `bit_0042101c_063_18` and sets a spurious `IBUF_HP_BANK_GLUE` — the
rx-distortion bug. Currently patched at the frame level in the demo
(`uartram/patch_rx_iob.py`); a proper fix belongs here as a segbit correction.
## 2026-06-10: SING-tile OLOGIC route-thru features are bit-free (ppips)
`ppips_{l,r}ioi_sing.db`: added `*IOI_SING.OLOGIC_Y{0,1}.{OQUSED, OMUX.D1,
OSERDES.DATA_RATE_TQ.BUF} always`. The SING tilegrid entries alias into the
regular LIOI/RIOI segbits with start_offset 2, so these route-thru features
resolved to WRONG physical bits and poisoned the pad output path (HW symptom:
led[4]/AR35 = IO_0_VRN_13 on LIOI_SING_X82Y51 stuck high in every open-flow
VC707 build, confirmed in both picosoc and johnson). Raw-frame diff against
a HW-working Vivado golden shows Vivado sets NO OLOGIC config bits in the
SING window — the D1->OQ pass-through is bit-free there — while on regular
LIOI tiles it sets the same OQUSED/OMUX.D1 bits we do. Declaring the
features as pseudo-pips makes fasm2frames emit no bits for them
(TileSegbitsAlias.feature_to_bits short-circuits on the tile's own ppips).
RIOI_SING entries added by symmetry (same alias structure), not HW-verified.
Suspected same misalias issue for SING ILOGIC input features (not yet seen).
## 2026-06-11: targeted solve of 3 HCLK_CMT_L CK_IN <- MUX_CLK segbits
Added to `segbits_hclk_cmt_l.db` (3 bits each):
CK_IN1 <- MUX_CLK_8: 28_183 29_152 29_155
CK_IN0 <- MUX_CLK_7: 26_152 26_154 29_182
CK_IN10 <- MUX_CLK_5: 29_181 29_203 29_206
Method: one Vivado specimen per pip (pipsolve/ in v7-johnson-demo) with
FIXED_ROUTE forced through the pip; residual = raw window bits minus the
bit2fasm->fasm2frames re-encoding. KEY: these "MUX_CLK_<n>" wires are the
GT MGT clock spine (node of HCLK_CMT_L_X305Y26/MUX_CLK_8 is
GTX_COMMON_X394Y23/GTXE2_COMMON_MGT_CLK4; MUX_CLK_7=MGT_CLK3<-TXOUTCLK_1,
MUX_CLK_5=MGT_CLK1<-RXOUTCLK_1) - which is why the 045 fuzzer (no GT in
specimens) could never solve them. Each entry's 3rd bit (~_181..183) looks
like a per-lane spine-tap enable shared with other consumers of the same
MUX_CLK lane; included in the pip entry since lanes are single-consumer in
practice. Remaining family members (other CK_IN x MUX_CLK combos) still
unsolved - a proper fuzz needs GT-driven specimens.
## 2026-06-11: BRAM_L_X114Y0 tilegrid entry was empty
`xc7vx485t/tilegrid.json`: BRAM_L_X114Y0 had `bits: {}` (tilegrid fuzzer
gap at the column bottom), silently dropping every feature for any BRAM
placed there. Filled from the column pattern (same baseaddrs as
BRAM_L_X114Y5/Y10, offset 0): BLOCK_RAM 0x00C20500/128f/10w,
CLB_IO_CLK 0x00423900/28f/10w. Found by the dcp2fasm bit-equivalence
campaign (ethsoc Vivado DCP -> fasm -> frames vs golden bit).
## 2026-06-11: SING IOB tiles - prefer own segbits db over broken alias
`prjxray/grid.py get_tile_segbits_at_tilename()`: tiles whose tilegrid
bits carry an `alias` (LIOB18_SING etc.) were ALWAYS resolved through
TileSegbitsAlias, but the virtex7 SING alias metadata is wrong (sites
map names IOB33_* on an IOB18 part; start_offset arithmetic places the
LIOB18-db Y1 bits 2 words below the SING window) -- features for e.g.
led[4]'s LIOB18_SING_X81Y51 silently CORRUPTED the neighbouring
LIOB18_X81Y49 frames (6 stray bits, found by the bit-equivalence
ledger). Fix: when the tile type has its own segbits db
(segbits_liob18_sing.db exists), use it directly; alias only as
fallback. Applied to deps/prjxray and $HOME/prjxray.
## 2026-06-17: kintex7 transplant removal — IOI ILOGIC + ISERDES re-fuzzed
The LIOI/RIOI segbits carried features whose origin_info recorded fuzzers
that CANNOT run on this HP-only part (IOB33/HR-targeted), i.e. kintex7
transplants. Audited via the per-bit `origin:` provenance; retired so far:
- `035-iob-ilogic` (114 bits): replaced by new fuzzer fuzzers/035-iob18-ilogic
(IOB18 sites, L+R, tag-grouped enums). Real ILOGIC/IFF config measured on
both sides. IMPORTANT: `ILOGIC_Y{0,1}.ZINV_D` has NO virtex7 frame bit
(exhaustive frame search = zero correlation; kintex7/artix7 don't carry it
as a bit either) — the transplant was wrong, not just incomplete. Now
declared bit-free via `<tile>.ILOGIC_Y{0,1}.ZINV_D always` in the IOI ppips.
- `035b-iob-iserdes` (156 bits): replaced by fuzzers/035b-iob18-iserdes
(IOB18 ISERDESE2, L+R). Real ISERDES taxonomy
(MEMORY/NETWORKING/OVERSAMPLE x rate x width, MODE, DYN_*, IN_USE).
Method: utils/strip_transplant.py drops bits by origin from both the .db and
.origin_info.db, then the new fuzzer's `make pushdb` merges real L+R data
(segmaker's IOI. prefix -> mergedb rewrites per side). Validated by rebuilding
the open-flow picosoc: ILOGIC/ISERDES warnings gone, bit configures on VC707.
Still transplanted (to do): `f4pga` (768 bits, lioi left-side IOI pips — needs
037-iob18-pips driven to cover the left column) and `hand-copied-from-LIOB18`
(5 bits, LIOB18_SING IOB_Y1 DRIVE/SLEW/PULLTYPE/STEPDOWN + OBUF_HP_BANK_GLUE).
## 2026-06-18: SING IOB18 — hand-copied transplant replaced by validated mirror
LIOB18_SING / RIOB18_SING IOB18 carried 5 hand-copied (origin
hand-copied-from-LIOB18), partly mis-addressed entries. Built
fuzzers/030-iob18-sing (OBUF/IBUF/unused mix on the ~28 SING IOB18 sites) and
confirmed by real measurement that the SING IOB18 DRIVE/SLEW/PULLTYPE/IN bits
are BIT-IDENTICAL to the regular LIOB18 (e.g. Y1 DRIVE 38_32/38_34/39_23/39_55).
Finding: nextpnr emits the regular LIOB18 feature *names* for SING tiles, and
the ~28 rare SING sites cannot make segmatch resolve the multi-bit DRIVE enum
(OUT stays <N candidates> at any N). So the SING IOB db must mirror LIOB18's
names exactly; it cannot be independently fuzzed into a nextpnr-consumable form.
Resolution: replaced the hand-copy with a COMPLETE, correct mirror of every
LIOB18/RIOB18 IOB_Y0/Y1 feature (origin liob18-arch-mirror), excluding STEPDOWN
whose !00_127 (frame 0) bit overflows the SING tilegrid word window (word 102)
and corrupts neighbours -- left as a tolerated "not found" rather than the
corrupting "invalid word address". picosoc now builds with only that one
benign STEPDOWN warning. This is a same-part architectural mirror, NOT a
kintex7 transplant.
## SLICEM DOUTMUX.MC31 spurious A5FFMUX bit (2026-07-02)
`CLBLM_{L,R}.SLICEM_X0.DOUTMUX.MC31` carried a spurious `30_10` — that bit is
`A5FFMUX.IN_B` (fuzzer-specimen contamination). A real Vivado SRL cascade
(SRLC32E chain crossing a slice: A-LUT MC31 -> DMUX -> fabric -> next slice's
DI pin) sets only `{30_52, 30_57}` in the DOUTMUX group, so bit2fasm decoded NO
DOUTMUX feature and the cascade link was silently dropped. Fix: remove `30_10`;
the remaining `!30_51 30_52 !30_56 30_57` is distinct from every other DOUTMUX
leg. Found via the bit2verilog srl differential test (160-deep SRL, d3 diverged
at cycle 129 = the first value needing the cross-slice hop).

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# openXC7 Virtex-7 device database (prjxray `database/virtex7`)
Canonical, version-controlled copy of the prjxray **virtex7** device database
(segbits / tilegrid / part data) used by the openXC7 flow for the VC707
(`xc7vx485tffg1761-2`).
Upstream prjxray **gitignores its `database/` tree** (it is fuzzer *output*),
so this data has historically lived only on the fuzzing machine. This repo
exists to make it a first-class, diffable, releasable artifact — the canonical
source of truth and the durable off-machine backup.
## What's here
The full `database/virtex7` tree, committed **raw** (no `.gitignore` hiding the
generated `.db`/`.json`):
* `segbits_*.db` — feature → bit mappings (the fuzzed encoding)
* `tilegrid.json`, `tileconn.json`, `*.json` — geometry / connectivity
* `part.yaml`, `*.csv` — part metadata
These are text and `diff`/`blame` cleanly — every segbit change is reviewable.
## Derived artifacts (NOT stored here — regenerated, published as release assets)
These are also derivatives of licensed code, but the **build tooling that
produces them is kept in a separate repo** under its own licence (see
*Provenance & licensing* below) — it is not part of this database.
* **nextpnr chipdb** `xc7vx485t.bin` — built **from this DB** by nextpnr-xilinx
`bbaexport.py --xray <this repo>` + `bbasm` (the xc7 / Project X-Ray path; no
RapidWright). Its `.bba` binary format is tied to a specific nextpnr-xilinx
commit, pinned in the tooling's `manifest.json`.
* **json2dcp wire oracle** `xc7vx485tffg1761-2.oracle.txt.gz` — built from
RapidWright (`BuildWireOracle`); independent of these segbits.
Build recipes (`build-chipdb.sh`, `build-oracle.sh`, `cut-release.sh`) and the
release `manifest.json` live in **`v7-johnson-demo/device-db-tools/`**.
A release tag bundles this DB commit + the chipdb + the oracle + `SHA256SUMS`,
so the three can never drift out of sync (the previous failure mode, where the
chipdb and DB carried different dates from different repos).
## Reconciliation workflow
Fuzzing / hand-patching happens **in place in this directory** (it is the
prjxray build area). Because the DB is now tracked:
```
# after a fuzz/patch session that improves the DB:
git status # shows exactly which segbits changed (invisible before)
git diff # review the encoding deltas
git add -A && git commit -m "..." # capture the local patches
git tag device-db-YYYY-MM-DD # cut a release
```
Then run `device-db-tools/recipes/cut-release.sh` (in the demo repo) to build
the chipdb + oracle from this commit and stamp the manifest.
Pulling a newer upstream release is a `git merge` against this repo —
conflicts between local patches and the release surface explicitly instead of
one copy silently clobbering the other.
See `FIXES.md` for the substantive segbit corrections this DB carries over a
stock prjxray fuzz.
## Provenance & licensing
This database is **fuzzer output**: the bit↔feature correlations were derived
by Project X-Ray's fuzzers, which drive Vivado to generate and diff bitstreams.
It is distributed under the Project X-Ray licence (ISC) — see `LICENSE` — as a
mirror/extension of the upstream prjxray database, and contains no Xilinx
source or proprietary files.
This repo deliberately contains **only the database** (a derivative-of-licensed-
tools artifact). Original tooling that consumes or rebuilds it
(`device-db-tools/`, the SVS suite, json2dcp, the demo) lives in separate repos
under their own licences, to keep our original code cleanly separated from
derivatives of licensed code.

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type,count
tiles,150380
sites,140823
site_pins,5720456
site_pips,11194048
pips,207253149
package_pins,1760
nodes,19243715
wires,56847864
1 type count
2 tiles 150380
3 sites 140823
4 site_pins 5720456
5 site_pips 11194048
6 pips 207253149
7 package_pins 1760
8 nodes 19243715
9 wires 56847864

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# device to fabric mapping
"xc7vx485t":
fabric: "xc7vx485t"

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xc7vx485tffg1157-1:
device: xc7vx485t
package: ffg1157
speedgrade: '1'
xc7vx485tffg1157-2:
device: xc7vx485t
package: ffg1157
speedgrade: '2'
xc7vx485tffg1157-2L:
device: xc7vx485t
package: ffg1157
speedgrade: 2L
xc7vx485tffg1157-3:
device: xc7vx485t
package: ffg1157
speedgrade: '3'
xc7vx485tffg1158-1:
device: xc7vx485t
package: ffg1158
speedgrade: '1'
xc7vx485tffg1158-2:
device: xc7vx485t
package: ffg1158
speedgrade: '2'
xc7vx485tffg1158-2L:
device: xc7vx485t
package: ffg1158
speedgrade: 2L
xc7vx485tffg1158-3:
device: xc7vx485t
package: ffg1158
speedgrade: '3'
xc7vx485tffg1761-1:
device: xc7vx485t
package: ffg1761
speedgrade: '1'
xc7vx485tffg1761-2:
device: xc7vx485t
package: ffg1761
speedgrade: '2'
xc7vx485tffg1761-2L:
device: xc7vx485t
package: ffg1761
speedgrade: 2L
xc7vx485tffg1761-3:
device: xc7vx485t
package: ffg1761
speedgrade: '3'
xc7vx485tffg1927-1:
device: xc7vx485t
package: ffg1927
speedgrade: '1'
xc7vx485tffg1927-2:
device: xc7vx485t
package: ffg1927
speedgrade: '2'
xc7vx485tffg1927-2L:
device: xc7vx485t
package: ffg1927
speedgrade: 2L
xc7vx485tffg1927-3:
device: xc7vx485t
package: ffg1927
speedgrade: '3'
xc7vx485tffg1930-1:
device: xc7vx485t
package: ffg1930
speedgrade: '1'
xc7vx485tffg1930-2:
device: xc7vx485t
package: ffg1930
speedgrade: '2'
xc7vx485tffg1930-2L:
device: xc7vx485t
package: ffg1930
speedgrade: 2L
xc7vx485tffg1930-3:
device: xc7vx485t
package: ffg1930
speedgrade: '3'

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bit 26_163
bit 26_179
bit 26_195
bit 26_211
bit 26_227
bit 26_243
bit 26_291
bit 26_307
bit 26_323
bit 26_339
bit 26_355
bit 26_371
bit 27_163
bit 27_166
bit 27_167
bit 27_179
bit 27_182
bit 27_183
bit 27_195
bit 27_198
bit 27_199
bit 27_211
bit 27_214
bit 27_215
bit 27_227
bit 27_230
bit 27_231
bit 27_243
bit 27_246
bit 27_247
bit 27_291
bit 27_294
bit 27_295
bit 27_307
bit 27_310
bit 27_311
bit 27_323
bit 27_326
bit 27_327
bit 27_339
bit 27_342
bit 27_343
bit 27_355
bit 27_358
bit 27_359
bit 27_371
bit 27_374
bit 27_375
bit 28_163
bit 28_179
bit 28_195
bit 28_211
bit 28_227
bit 28_243
bit 28_291
bit 28_307
bit 28_323
bit 28_339
bit 28_355
bit 28_371
bit 29_163
bit 29_166
bit 29_167
bit 29_179
bit 29_182
bit 29_183
bit 29_195
bit 29_198
bit 29_199
bit 29_211
bit 29_214
bit 29_215
bit 29_227
bit 29_230
bit 29_231
bit 29_243
bit 29_246
bit 29_247
bit 29_291
bit 29_294
bit 29_295
bit 29_307
bit 29_310
bit 29_311
bit 29_323
bit 29_326
bit 29_327
bit 29_339
bit 29_342
bit 29_343
bit 29_355
bit 29_358
bit 29_359
bit 29_371
bit 29_374
bit 29_375

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bit 26_163
bit 26_179
bit 26_195
bit 26_211
bit 26_227
bit 26_243
bit 26_291
bit 26_307
bit 26_323
bit 26_339
bit 26_355
bit 26_371
bit 27_163
bit 27_166
bit 27_167
bit 27_179
bit 27_182
bit 27_183
bit 27_195
bit 27_198
bit 27_199
bit 27_211
bit 27_214
bit 27_215
bit 27_227
bit 27_230
bit 27_231
bit 27_243
bit 27_246
bit 27_247
bit 27_291
bit 27_294
bit 27_295
bit 27_307
bit 27_310
bit 27_311
bit 27_323
bit 27_326
bit 27_327
bit 27_339
bit 27_342
bit 27_343
bit 27_355
bit 27_358
bit 27_359
bit 27_371
bit 27_374
bit 27_375
bit 28_163
bit 28_179
bit 28_195
bit 28_211
bit 28_227
bit 28_243
bit 28_291
bit 28_307
bit 28_323
bit 28_339
bit 28_355
bit 28_371
bit 29_163
bit 29_166
bit 29_167
bit 29_179
bit 29_182
bit 29_183
bit 29_195
bit 29_198
bit 29_199
bit 29_211
bit 29_214
bit 29_215
bit 29_227
bit 29_230
bit 29_231
bit 29_243
bit 29_246
bit 29_247
bit 29_291
bit 29_294
bit 29_295
bit 29_307
bit 29_310
bit 29_311
bit 29_323
bit 29_326
bit 29_327
bit 29_339
bit 29_342
bit 29_343
bit 29_355
bit 29_358
bit 29_359
bit 29_371
bit 29_374
bit 29_375

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bit 31_20
bit 32_16
bit 32_17
bit 32_19
bit 32_20
bit 32_22
bit 32_26
bit 32_28
bit 32_30
bit 33_14
bit 33_15
bit 33_16
bit 33_17
bit 33_18
bit 33_19
bit 33_20
bit 33_21
bit 33_23
bit 33_24
bit 33_25
bit 33_26
bit 33_27
bit 33_28
bit 33_29
bit 33_30
bit 33_31
bit 34_15
bit 34_16
bit 34_23
bit 34_24
bit 34_31
bit 35_19
bit 35_21
bit 35_23
bit 35_24
bit 35_25
bit 36_24
bit 36_25
bit 36_26
bit 36_27

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bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

0
virtex7/mask_hclk_l.origin_info.db Normal file
View File

104
virtex7/mask_hclk_r.db Normal file
View File

@ -0,0 +1,104 @@
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

0
virtex7/mask_hclk_r.origin_info.db Normal file
View File

272
virtex7/mask_lioi.db Normal file
View File

@ -0,0 +1,272 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_87
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97

96
virtex7/mask_lioi_sing.db Normal file
View File

@ -0,0 +1,96 @@
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_15
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_31
bit 30_33
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_49
bit 30_51
bit 30_57
bit 30_59
bit 30_61
bit 30_63
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_12
bit 31_14
bit 31_19
bit 31_22
bit 31_25
bit 31_26
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_36
bit 31_38
bit 31_42
bit 31_46
bit 31_47
bit 31_48
bit 31_50
bit 31_52
bit 31_54
bit 31_56
bit 31_57
bit 31_59
bit 31_60
bit 31_62
bit 32_02
bit 32_06
bit 32_08
bit 32_16
bit 32_18
bit 32_20
bit 32_26
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_48
bit 32_52
bit 32_54
bit 32_58
bit 33_05
bit 33_09
bit 33_11
bit 33_15
bit 33_17
bit 33_19
bit 33_25
bit 33_27
bit 33_29
bit 33_31
bit 33_33
bit 33_37
bit 33_43
bit 33_45
bit 33_47
bit 33_55
bit 33_57
bit 33_61

272
virtex7/mask_lioi_tbytesrc.db Normal file
View File

@ -0,0 +1,272 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_87
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97

272
virtex7/mask_lioi_tbyteterm.db Normal file
View File

@ -0,0 +1,272 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_87
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97

75
virtex7/mask_riob18.db Normal file
View File

@ -0,0 +1,75 @@
bit 38_00
bit 38_02
bit 38_04
bit 38_08
bit 38_10
bit 38_104
bit 38_114
bit 38_12
bit 38_124
bit 38_126
bit 38_14
bit 38_16
bit 38_20
bit 38_22
bit 38_24
bit 38_26
bit 38_28
bit 38_30
bit 38_32
bit 38_34
bit 38_38
bit 38_40
bit 38_44
bit 38_46
bit 38_48
bit 38_50
bit 38_62
bit 38_72
bit 38_78
bit 38_80
bit 38_82
bit 38_86
bit 38_88
bit 38_92
bit 38_94
bit 38_96
bit 39_01
bit 39_03
bit 39_101
bit 39_103
bit 39_105
bit 39_107
bit 39_111
bit 39_113
bit 39_115
bit 39_117
bit 39_123
bit 39_125
bit 39_127
bit 39_13
bit 39_15
bit 39_17
bit 39_21
bit 39_23
bit 39_31
bit 39_33
bit 39_35
bit 39_37
bit 39_39
bit 39_41
bit 39_43
bit 39_45
bit 39_47
bit 39_49
bit 39_55
bit 39_65
bit 39_73
bit 39_77
bit 39_79
bit 39_81
bit 39_83
bit 39_89
bit 39_93
bit 39_95
bit 39_97

373
virtex7/mask_rioi.db Normal file
View File

@ -0,0 +1,373 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_87
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 34_08
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_109
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_55
bit 34_58
bit 34_72
bit 34_73
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_18
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_54
bit 35_55
bit 35_69
bit 35_72
bit 35_81
bit 35_89
bit 36_08
bit 36_100
bit 36_102
bit 36_108
bit 36_110
bit 36_114
bit 36_116
bit 36_120
bit 36_122
bit 36_14
bit 36_38
bit 36_72
bit 36_88
bit 36_94
bit 36_96
bit 37_05
bit 37_07
bit 37_11
bit 37_113
bit 37_119
bit 37_13
bit 37_17
bit 37_19
bit 37_25
bit 37_27
bit 37_31
bit 37_33
bit 37_39
bit 37_55
bit 37_89
bit 38_00
bit 38_12
bit 38_126
bit 38_24
bit 38_32
bit 38_34
bit 38_48
bit 38_52
bit 38_78
bit 38_80
bit 38_94
bit 39_01
bit 39_103
bit 39_115
bit 39_117
bit 39_127
bit 39_33
bit 39_47
bit 39_49
bit 39_75
bit 39_79
bit 39_93
bit 39_95

96
virtex7/mask_rioi_sing.db Normal file
View File

@ -0,0 +1,96 @@
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_13
bit 30_15
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_31
bit 30_33
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_49
bit 30_51
bit 30_57
bit 30_59
bit 30_61
bit 30_63
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_12
bit 31_14
bit 31_19
bit 31_22
bit 31_25
bit 31_26
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_36
bit 31_38
bit 31_42
bit 31_46
bit 31_47
bit 31_48
bit 31_50
bit 31_52
bit 31_54
bit 31_56
bit 31_57
bit 31_59
bit 31_60
bit 31_62
bit 32_02
bit 32_06
bit 32_08
bit 32_16
bit 32_18
bit 32_20
bit 32_26
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_48
bit 32_52
bit 32_54
bit 32_58
bit 33_05
bit 33_09
bit 33_11
bit 33_15
bit 33_17
bit 33_19
bit 33_25
bit 33_27
bit 33_29
bit 33_31
bit 33_33
bit 33_37
bit 33_43
bit 33_45
bit 33_47
bit 33_55
bit 33_57
bit 33_61

373
virtex7/mask_rioi_tbytesrc.db Normal file
View File

@ -0,0 +1,373 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_87
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 34_08
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_109
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_55
bit 34_58
bit 34_72
bit 34_73
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_18
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_54
bit 35_55
bit 35_69
bit 35_72
bit 35_81
bit 35_89
bit 36_08
bit 36_100
bit 36_102
bit 36_108
bit 36_110
bit 36_114
bit 36_116
bit 36_120
bit 36_122
bit 36_14
bit 36_38
bit 36_72
bit 36_88
bit 36_94
bit 36_96
bit 37_05
bit 37_07
bit 37_11
bit 37_113
bit 37_119
bit 37_13
bit 37_17
bit 37_19
bit 37_25
bit 37_27
bit 37_31
bit 37_33
bit 37_39
bit 37_55
bit 37_89
bit 38_00
bit 38_12
bit 38_126
bit 38_24
bit 38_32
bit 38_34
bit 38_48
bit 38_52
bit 38_78
bit 38_80
bit 38_94
bit 39_01
bit 39_103
bit 39_115
bit 39_117
bit 39_127
bit 39_33
bit 39_47
bit 39_49
bit 39_75
bit 39_79
bit 39_93
bit 39_95

373
virtex7/mask_rioi_tbyteterm.db Normal file
View File

@ -0,0 +1,373 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_111
bit 25_112
bit 25_115
bit 25_116
bit 25_122
bit 25_124
bit 25_16
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_47
bit 25_48
bit 25_51
bit 25_52
bit 25_58
bit 25_60
bit 25_71
bit 25_84
bit 25_85
bit 25_87
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 26_09
bit 26_101
bit 26_107
bit 26_109
bit 26_111
bit 26_115
bit 26_117
bit 26_119
bit 26_121
bit 26_15
bit 26_17
bit 26_19
bit 26_21
bit 26_25
bit 26_29
bit 26_47
bit 26_57
bit 26_71
bit 26_99
bit 27_06
bit 27_08
bit 27_10
bit 27_102
bit 27_106
bit 27_108
bit 27_110
bit 27_112
bit 27_118
bit 27_12
bit 27_16
bit 27_18
bit 27_20
bit 27_26
bit 27_28
bit 27_56
bit 27_70
bit 27_80
bit 27_98
bit 28_00
bit 28_02
bit 28_04
bit 28_110
bit 28_111
bit 28_116
bit 28_121
bit 28_123
bit 28_124
bit 28_126
bit 28_14
bit 28_18
bit 28_24
bit 28_26
bit 28_33
bit 28_34
bit 28_42
bit 28_47
bit 28_49
bit 28_52
bit 28_56
bit 28_60
bit 28_64
bit 28_67
bit 28_72
bit 28_75
bit 28_76
bit 28_77
bit 28_79
bit 28_81
bit 28_83
bit 28_86
bit 28_89
bit 28_93
bit 28_94
bit 28_95
bit 28_97
bit 29_01
bit 29_03
bit 29_04
bit 29_06
bit 29_101
bit 29_103
bit 29_109
bit 29_11
bit 29_113
bit 29_123
bit 29_125
bit 29_127
bit 29_16
bit 29_17
bit 29_30
bit 29_32
bit 29_33
bit 29_34
bit 29_38
bit 29_41
bit 29_44
bit 29_46
bit 29_48
bit 29_50
bit 29_51
bit 29_52
bit 29_55
bit 29_60
bit 29_63
bit 29_67
bit 29_71
bit 29_75
bit 29_78
bit 29_80
bit 29_85
bit 29_93
bit 29_94
bit 30_01
bit 30_03
bit 30_04
bit 30_06
bit 30_07
bit 30_09
bit 30_11
bit 30_113
bit 30_121
bit 30_123
bit 30_125
bit 30_127
bit 30_13
bit 30_16
bit 30_17
bit 30_21
bit 30_25
bit 30_27
bit 30_29
bit 30_30
bit 30_32
bit 30_34
bit 30_35
bit 30_37
bit 30_38
bit 30_41
bit 30_44
bit 30_46
bit 30_48
bit 30_50
bit 30_51
bit 30_52
bit 30_60
bit 30_67
bit 30_71
bit 30_75
bit 30_78
bit 30_79
bit 30_80
bit 30_85
bit 30_94
bit 30_95
bit 30_97
bit 30_99
bit 31_00
bit 31_02
bit 31_04
bit 31_06
bit 31_100
bit 31_102
bit 31_106
bit 31_110
bit 31_111
bit 31_114
bit 31_116
bit 31_118
bit 31_120
bit 31_121
bit 31_123
bit 31_124
bit 31_126
bit 31_14
bit 31_28
bit 31_30
bit 31_32
bit 31_33
bit 31_42
bit 31_47
bit 31_48
bit 31_49
bit 31_52
bit 31_56
bit 31_60
bit 31_67
bit 31_75
bit 31_76
bit 31_77
bit 31_79
bit 31_81
bit 31_83
bit 31_86
bit 31_89
bit 31_90
bit 31_92
bit 31_93
bit 31_95
bit 31_97
bit 31_98
bit 32_108
bit 32_109
bit 32_112
bit 32_16
bit 32_20
bit 32_30
bit 32_32
bit 32_34
bit 32_36
bit 32_38
bit 32_44
bit 32_46
bit 32_52
bit 32_54
bit 32_55
bit 32_58
bit 32_66
bit 32_70
bit 32_72
bit 32_73
bit 32_82
bit 32_90
bit 32_94
bit 33_107
bit 33_111
bit 33_15
bit 33_18
bit 33_19
bit 33_33
bit 33_37
bit 33_45
bit 33_54
bit 33_55
bit 33_57
bit 33_61
bit 33_69
bit 33_72
bit 33_73
bit 33_75
bit 33_81
bit 33_83
bit 33_89
bit 33_91
bit 33_93
bit 33_95
bit 33_97
bit 34_08
bit 34_100
bit 34_102
bit 34_106
bit 34_108
bit 34_109
bit 34_110
bit 34_114
bit 34_116
bit 34_120
bit 34_122
bit 34_14
bit 34_38
bit 34_46
bit 34_55
bit 34_58
bit 34_72
bit 34_73
bit 34_88
bit 34_94
bit 34_96
bit 35_05
bit 35_07
bit 35_11
bit 35_113
bit 35_119
bit 35_13
bit 35_17
bit 35_18
bit 35_19
bit 35_21
bit 35_25
bit 35_27
bit 35_31
bit 35_33
bit 35_39
bit 35_54
bit 35_55
bit 35_69
bit 35_72
bit 35_81
bit 35_89
bit 36_08
bit 36_100
bit 36_102
bit 36_108
bit 36_110
bit 36_114
bit 36_116
bit 36_120
bit 36_122
bit 36_14
bit 36_38
bit 36_72
bit 36_88
bit 36_94
bit 36_96
bit 37_05
bit 37_07
bit 37_11
bit 37_113
bit 37_119
bit 37_13
bit 37_17
bit 37_19
bit 37_25
bit 37_27
bit 37_31
bit 37_33
bit 37_39
bit 37_55
bit 37_89
bit 38_00
bit 38_12
bit 38_126
bit 38_24
bit 38_32
bit 38_34
bit 38_48
bit 38_52
bit 38_78
bit 38_80
bit 38_94
bit 39_01
bit 39_103
bit 39_115
bit 39_117
bit 39_127
bit 39_33
bit 39_47
bit 39_49
bit 39_75
bit 39_79
bit 39_93
bit 39_95

24
virtex7/ppips_bram_int_interface_l.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

0
virtex7/ppips_bram_int_interface_l.origin_info.db Normal file
View File

24
virtex7/ppips_bram_int_interface_r.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

0
virtex7/ppips_bram_int_interface_r.origin_info.db Normal file
View File

794
virtex7/ppips_bram_l.db Normal file
View File

@ -0,0 +1,794 @@
BRAM_L.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_L.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_L.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_L.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_L.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_L.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_L.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_L.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_L.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_L.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_L.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_L.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_L.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_L.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_L.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_L.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_L.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_L.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_L.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_L.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_L.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_L.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_L.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_L.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_L.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_L.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_L.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_L.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_L.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_L.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_L.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_L.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_L.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_L.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_L.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_L.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_L.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_L.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_L.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_L.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_L.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_L.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_L.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_L.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_L.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_L.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_L.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_L.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_L.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_L.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_L.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_L.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_L.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_L.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_L.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_L.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_L.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_L.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_L.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_L.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_L.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_L.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_L.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_L.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_L.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_L.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_L.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_L.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_L.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_L.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_L.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_L.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_L.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_L.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_L.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_L.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_L.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_L.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_L.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_L.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_L.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_L.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_L.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_L.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_L.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_L.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_L.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_L.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_L.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_L.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_L.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_L.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_L.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_L.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_L.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_L.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_L.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_L.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_L.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_L.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_L.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_L.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_L.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_L.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_L.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_L.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_L.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_L.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_L.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_L.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_L.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_L.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_L.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_L.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_L.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_L.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_L.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_L.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_L.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_L.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_L.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_L.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_L.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_L.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_L.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_L.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_L.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_L.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_L.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_L.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_L.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_L.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_L.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_L.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_L.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_L.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_L.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_L.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_L.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_L.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_L.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_L.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_L.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_L.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_L.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_L.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_L.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_L.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_L.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_L.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_L.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_L.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_L.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_L.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_L.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_L.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_L.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_L.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_L.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_L.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_L.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_L.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_L.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always
BRAM_L.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_L.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_L.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_L.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_L.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_L.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_L.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_L.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_L.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_L.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_L.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_L.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_L.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_L.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_L.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_L.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_L.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_L.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_L.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_L.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_L.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_L.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always

0
virtex7/ppips_bram_l.origin_info.db Normal file
View File

794
virtex7/ppips_bram_r.db Normal file
View File

@ -0,0 +1,794 @@
BRAM_R.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_R.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_R.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_R.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_R.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_R.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_R.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_R.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_R.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_R.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_R.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_R.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_R.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_R.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_R.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_R.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_R.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_R.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_R.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_R.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_R.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_R.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_R.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_R.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_R.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_R.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_R.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_R.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_R.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_R.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_R.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_R.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_R.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_R.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_R.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_R.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_R.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_R.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_R.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_R.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_R.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_R.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_R.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_R.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_R.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_R.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_R.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_R.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_R.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_R.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_R.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_R.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_R.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_R.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_R.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_R.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_R.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_R.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_R.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_R.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_R.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_R.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_R.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_R.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_R.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_R.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_R.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_R.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_R.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_R.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_R.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_R.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_R.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_R.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_R.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_R.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_R.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_R.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_R.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_R.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_R.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_R.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_R.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_R.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_R.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_R.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_R.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_R.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_R.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_R.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_R.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_R.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_R.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_R.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_R.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_R.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_R.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_R.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_R.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_R.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_R.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_R.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_R.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_R.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_R.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_R.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_R.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_R.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_R.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_R.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_R.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_R.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_R.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_R.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_R.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_R.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_R.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_R.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_R.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_R.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_R.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_R.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_R.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_R.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_R.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_R.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_R.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_R.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_R.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_R.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_R.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_R.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_R.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_R.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_R.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_R.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_R.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_R.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_R.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_R.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_R.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_R.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_R.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_R.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_R.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_R.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_R.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_R.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_R.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_R.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_R.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_R.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_R.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_R.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_R.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_R.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_R.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_R.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_R.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_R.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_R.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_R.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_R.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always
BRAM_R.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_R.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_R.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_R.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_R.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_R.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_R.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_R.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_R.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_R.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_R.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_R.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_R.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_R.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_R.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_R.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_R.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_R.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_R.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_R.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_R.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_R.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always

0
virtex7/ppips_bram_r.origin_info.db Normal file
View File

14
virtex7/ppips_brkh_int.db Normal file
View File

@ -0,0 +1,14 @@
BRKH_INT.BRKH_INT_NL1BEG0_SLOW.BRKH_INT_NL1BEG0 always
BRKH_INT.BRKH_INT_NL1BEG1_SLOW.BRKH_INT_NL1BEG1 always
BRKH_INT.BRKH_INT_NL1BEG2_SLOW.BRKH_INT_NL1BEG2 always
BRKH_INT.BRKH_INT_NR1BEG0_SLOW.BRKH_INT_NR1BEG0 always
BRKH_INT.BRKH_INT_NR1BEG1_SLOW.BRKH_INT_NR1BEG1 always
BRKH_INT.BRKH_INT_NR1BEG2_SLOW.BRKH_INT_NR1BEG2 always
BRKH_INT.BRKH_INT_NR1BEG3_SLOW.BRKH_INT_NR1BEG3 always
BRKH_INT.BRKH_INT_SL1END0.BRKH_INT_SL1END0_SLOW always
BRKH_INT.BRKH_INT_SL1END1.BRKH_INT_SL1END1_SLOW always
BRKH_INT.BRKH_INT_SL1END2.BRKH_INT_SL1END2_SLOW always
BRKH_INT.BRKH_INT_SL1END3.BRKH_INT_SL1END3_SLOW always
BRKH_INT.BRKH_INT_SR1END1.BRKH_INT_SR1END1_SLOW always
BRKH_INT.BRKH_INT_SR1END2.BRKH_INT_SR1END2_SLOW always
BRKH_INT.BRKH_INT_SR1END3.BRKH_INT_SR1END3_SLOW always

13
virtex7/ppips_cfg_center_bot.db Normal file
View File

@ -0,0 +1,13 @@
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B13_19.CFG_CENTER_BOT_USR_ACCESS_DATA2 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B14_19.CFG_CENTER_BOT_USR_ACCESS_DATA3 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B15_19.CFG_CENTER_BOT_USR_ACCESS_DATA4 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B16_19.CFG_CENTER_BOT_USR_ACCESS_DATA5 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B17_19.CFG_CENTER_BOT_USR_ACCESS_DATA6 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B18_19.CFG_CENTER_BOT_USR_ACCESS_DATA7 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B19_19.CFG_CENTER_BOT_USR_ACCESS_DATA8 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B20_19.CFG_CENTER_BOT_USR_ACCESS_DATA9 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B21_19.CFG_CENTER_BOT_USR_ACCESS_DATA10 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B22_19.CFG_CENTER_BOT_USR_ACCESS_DATA11 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B23_19.CFG_CENTER_BOT_USR_ACCESS_DATA12 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B10_19.CFG_CENTER_BOT_USR_ACCESS_DATA13 always
CFG_CENTER_BOT.CFG_CENTER_LOGIC_OUTS_B11_19.CFG_CENTER_BOT_USR_ACCESS_DATA14 always

285
virtex7/ppips_cfg_center_mid.db Normal file
View File

@ -0,0 +1,285 @@
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_2.CFG_CENTER_BSCAN1_CAPTURE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_2.CFG_CENTER_BSCAN1_DRCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_2.CFG_CENTER_BSCAN1_RESET always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B8_2.CFG_CENTER_BSCAN1_RUNTEST always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_2.CFG_CENTER_BSCAN1_SEL always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_3.CFG_CENTER_BSCAN1_SHIFT always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_3.CFG_CENTER_BSCAN1_TCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_3.CFG_CENTER_BSCAN1_TDI always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_3.CFG_CENTER_BSCAN1_TMS always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_2.CFG_CENTER_BSCAN1_UPDATE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_2.CFG_CENTER_BSCAN2_CAPTURE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_2.CFG_CENTER_BSCAN2_DRCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_2.CFG_CENTER_BSCAN2_RESET always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B9_2.CFG_CENTER_BSCAN2_RUNTEST always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_2.CFG_CENTER_BSCAN2_SEL always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_3.CFG_CENTER_BSCAN2_SHIFT always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_3.CFG_CENTER_BSCAN2_TCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_3.CFG_CENTER_BSCAN2_TDI always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_3.CFG_CENTER_BSCAN2_TMS always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_2.CFG_CENTER_BSCAN2_UPDATE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_11.CFG_CENTER_BSCAN3_CAPTURE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_10.CFG_CENTER_BSCAN3_DRCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_10.CFG_CENTER_BSCAN3_RESET always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_11.CFG_CENTER_BSCAN3_RUNTEST always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_10.CFG_CENTER_BSCAN3_SEL always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_11.CFG_CENTER_BSCAN3_SHIFT always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_11.CFG_CENTER_BSCAN3_TCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_11.CFG_CENTER_BSCAN3_TDI always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_11.CFG_CENTER_BSCAN3_TMS always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_10.CFG_CENTER_BSCAN3_UPDATE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_11.CFG_CENTER_BSCAN4_CAPTURE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_10.CFG_CENTER_BSCAN4_DRCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_10.CFG_CENTER_BSCAN4_RESET always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_11.CFG_CENTER_BSCAN4_RUNTEST always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_10.CFG_CENTER_BSCAN4_SEL always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_11.CFG_CENTER_BSCAN4_SHIFT always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_11.CFG_CENTER_BSCAN4_TCK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_11.CFG_CENTER_BSCAN4_TDI always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_11.CFG_CENTER_BSCAN4_TMS always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_10.CFG_CENTER_BSCAN4_UPDATE always
CFG_CENTER_MID.CFG_CENTER_STARTUP_CLK.CFG_CENTER_CLK1_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_CLK.CFG_CENTER_CLK1_6 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_USRCCLKO.CFG_CENTER_CLK1_7 always
CFG_CENTER_MID.CFG_CENTER_MID_DNA_PORT_CLK.CFG_CENTER_CLK1_8 always
CFG_CENTER_MID.CFG_CENTER_CAPTURE_CLK.CFG_CENTER_CLK1_9 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_9.CFG_CENTER_DCIRESET_LOCKED always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_10.CFG_CENTER_FRAME_ECC_CRCERROR always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_9.CFG_CENTER_FRAME_ECC_ECCERROR always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_8.CFG_CENTER_FRAME_ECC_ECCERRORSINGLE always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_6.CFG_CENTER_FRAME_ECC_FAR0 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_7.CFG_CENTER_FRAME_ECC_FAR16 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_6.CFG_CENTER_FRAME_ECC_FAR1 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_7.CFG_CENTER_FRAME_ECC_FAR17 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_6.CFG_CENTER_FRAME_ECC_FAR2 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_7.CFG_CENTER_FRAME_ECC_FAR18 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_6.CFG_CENTER_FRAME_ECC_FAR3 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_7.CFG_CENTER_FRAME_ECC_FAR19 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_6.CFG_CENTER_FRAME_ECC_FAR4 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_7.CFG_CENTER_FRAME_ECC_FAR20 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_6.CFG_CENTER_FRAME_ECC_FAR5 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_7.CFG_CENTER_FRAME_ECC_FAR21 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_6.CFG_CENTER_FRAME_ECC_FAR6 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_7.CFG_CENTER_FRAME_ECC_FAR22 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_6.CFG_CENTER_FRAME_ECC_FAR7 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_7.CFG_CENTER_FRAME_ECC_FAR23 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_6.CFG_CENTER_FRAME_ECC_FAR8 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_7.CFG_CENTER_FRAME_ECC_FAR24 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_6.CFG_CENTER_FRAME_ECC_FAR9 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_7.CFG_CENTER_FRAME_ECC_FAR25 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_6.CFG_CENTER_FRAME_ECC_FAR10 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_6.CFG_CENTER_FRAME_ECC_FAR11 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_6.CFG_CENTER_FRAME_ECC_FAR12 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_6.CFG_CENTER_FRAME_ECC_FAR13 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B8_6.CFG_CENTER_FRAME_ECC_FAR14 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B9_6.CFG_CENTER_FRAME_ECC_FAR15 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_8.CFG_CENTER_FRAME_ECC_SYNBIT0 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_8.CFG_CENTER_FRAME_ECC_SYNBIT1 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_8.CFG_CENTER_FRAME_ECC_SYNBIT2 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_8.CFG_CENTER_FRAME_ECC_SYNBIT3 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_8.CFG_CENTER_FRAME_ECC_SYNBIT4 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_1.CFG_CENTER_FRAME_ECC_SYNDROME0 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_1.CFG_CENTER_FRAME_ECC_SYNDROME1 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_1.CFG_CENTER_FRAME_ECC_SYNDROME2 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_1.CFG_CENTER_FRAME_ECC_SYNDROME3 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_1.CFG_CENTER_FRAME_ECC_SYNDROME4 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_1.CFG_CENTER_FRAME_ECC_SYNDROME5 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_1.CFG_CENTER_FRAME_ECC_SYNDROME6 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_1.CFG_CENTER_FRAME_ECC_SYNDROME7 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_1.CFG_CENTER_FRAME_ECC_SYNDROME8 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_1.CFG_CENTER_FRAME_ECC_SYNDROME9 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_2.CFG_CENTER_FRAME_ECC_SYNDROME10 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_2.CFG_CENTER_FRAME_ECC_SYNDROME11 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_2.CFG_CENTER_FRAME_ECC_SYNDROME12 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_2.CFG_CENTER_FRAME_ECC_SYNDROMEVALID always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_7.CFG_CENTER_FRAME_ECC_SYNWORD0 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_7.CFG_CENTER_FRAME_ECC_SYNWORD1 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_7.CFG_CENTER_FRAME_ECC_SYNWORD2 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_7.CFG_CENTER_FRAME_ECC_SYNWORD3 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B8_7.CFG_CENTER_FRAME_ECC_SYNWORD4 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B9_7.CFG_CENTER_FRAME_ECC_SYNWORD5 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_8.CFG_CENTER_FRAME_ECC_SYNWORD6 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_4.CFG_CENTER_ICAP0_O0 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_5.CFG_CENTER_ICAP0_O16 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_4.CFG_CENTER_ICAP0_O1 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_5.CFG_CENTER_ICAP0_O17 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_3.CFG_CENTER_ICAP0_O2 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_4.CFG_CENTER_ICAP0_O18 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_3.CFG_CENTER_ICAP0_O3 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_4.CFG_CENTER_ICAP0_O19 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_3.CFG_CENTER_ICAP0_O4 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_4.CFG_CENTER_ICAP0_O20 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_3.CFG_CENTER_ICAP0_O5 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_4.CFG_CENTER_ICAP0_O21 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_3.CFG_CENTER_ICAP0_O6 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_4.CFG_CENTER_ICAP0_O22 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_3.CFG_CENTER_ICAP0_O7 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_4.CFG_CENTER_ICAP0_O23 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B8_3.CFG_CENTER_ICAP0_O8 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B8_4.CFG_CENTER_ICAP0_O24 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B9_3.CFG_CENTER_ICAP0_O9 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B9_4.CFG_CENTER_ICAP0_O25 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_4.CFG_CENTER_ICAP0_O10 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_5.CFG_CENTER_ICAP0_O26 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_4.CFG_CENTER_ICAP0_O11 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_5.CFG_CENTER_ICAP0_O27 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_4.CFG_CENTER_ICAP0_O12 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_5.CFG_CENTER_ICAP0_O28 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_4.CFG_CENTER_ICAP0_O13 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_5.CFG_CENTER_ICAP0_O29 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_4.CFG_CENTER_ICAP0_O14 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_5.CFG_CENTER_ICAP0_O30 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_4.CFG_CENTER_ICAP0_O15 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_5.CFG_CENTER_ICAP0_O31 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_11.CFG_CENTER_ICAP1_O0 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_12.CFG_CENTER_ICAP1_O12 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_13.CFG_CENTER_ICAP1_O24 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_12.CFG_CENTER_ICAP1_O1 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_13.CFG_CENTER_ICAP1_O13 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_14.CFG_CENTER_ICAP1_O27 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_12.CFG_CENTER_ICAP1_O2 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_13.CFG_CENTER_ICAP1_O14 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_14.CFG_CENTER_ICAP1_O28 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_12.CFG_CENTER_ICAP1_O3 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_13.CFG_CENTER_ICAP1_O15 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_14.CFG_CENTER_ICAP1_O29 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_12.CFG_CENTER_ICAP1_O4 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_13.CFG_CENTER_ICAP1_O16 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_14.CFG_CENTER_ICAP1_O30 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_12.CFG_CENTER_ICAP1_O5 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_13.CFG_CENTER_ICAP1_O17 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_14.CFG_CENTER_ICAP1_O31 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_12.CFG_CENTER_ICAP1_O6 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_13.CFG_CENTER_ICAP1_O18 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_12.CFG_CENTER_ICAP1_O7 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_13.CFG_CENTER_ICAP1_O19 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_12.CFG_CENTER_ICAP1_O8 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_13.CFG_CENTER_ICAP1_O20 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_12.CFG_CENTER_ICAP1_O9 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_13.CFG_CENTER_ICAP1_O21 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_12.CFG_CENTER_ICAP1_O10 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_13.CFG_CENTER_ICAP1_O22 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_12.CFG_CENTER_ICAP1_O11 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_13.CFG_CENTER_ICAP1_O23 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_14.CFG_CENTER_ICAP1_O25 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_14.CFG_CENTER_ICAP1_O26 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I16.CFG_CENTER_IMUX27_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I0.CFG_CENTER_IMUX28_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I17.CFG_CENTER_IMUX28_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I0.CFG_CENTER_IMUX28_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I16.CFG_CENTER_IMUX28_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I1.CFG_CENTER_IMUX29_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I18.CFG_CENTER_IMUX29_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I1.CFG_CENTER_IMUX29_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I17.CFG_CENTER_IMUX29_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I2.CFG_CENTER_IMUX30_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I19.CFG_CENTER_IMUX30_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I2.CFG_CENTER_IMUX30_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I18.CFG_CENTER_IMUX30_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I3.CFG_CENTER_IMUX31_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I20.CFG_CENTER_IMUX31_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I3.CFG_CENTER_IMUX31_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I19.CFG_CENTER_IMUX31_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I4.CFG_CENTER_IMUX32_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I21.CFG_CENTER_IMUX32_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I4.CFG_CENTER_IMUX32_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I20.CFG_CENTER_IMUX32_13 always
CFG_CENTER_MID.CFG_CENTER_BSCAN1_TDO.CFG_CENTER_IMUX33_3 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I5.CFG_CENTER_IMUX33_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I22.CFG_CENTER_IMUX33_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I5.CFG_CENTER_IMUX33_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I21.CFG_CENTER_IMUX33_13 always
CFG_CENTER_MID.CFG_CENTER_BSCAN2_TDO.CFG_CENTER_IMUX34_3 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I6.CFG_CENTER_IMUX34_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I23.CFG_CENTER_IMUX34_5 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I6.CFG_CENTER_IMUX34_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I22.CFG_CENTER_IMUX34_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I7.CFG_CENTER_IMUX35_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I24.CFG_CENTER_IMUX35_5 always
CFG_CENTER_MID.CFG_CENTER_DCIRESET_RST.CFG_CENTER_IMUX35_8 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I7.CFG_CENTER_IMUX35_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I23.CFG_CENTER_IMUX35_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I8.CFG_CENTER_IMUX36_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I25.CFG_CENTER_IMUX36_5 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_KEYCLEARB.CFG_CENTER_IMUX36_8 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I8.CFG_CENTER_IMUX36_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I24.CFG_CENTER_IMUX36_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I9.CFG_CENTER_IMUX37_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I26.CFG_CENTER_IMUX37_5 always
CFG_CENTER_MID.CFG_CENTER_CAPTURE_CAP.CFG_CENTER_IMUX37_8 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I9.CFG_CENTER_IMUX37_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I25.CFG_CENTER_IMUX37_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I10.CFG_CENTER_IMUX38_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I27.CFG_CENTER_IMUX38_5 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_USRCCLKTS.CFG_CENTER_IMUX38_8 always
CFG_CENTER_MID.CFG_CENTER_BSCAN3_TDO.CFG_CENTER_IMUX38_11 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I10.CFG_CENTER_IMUX38_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I26.CFG_CENTER_IMUX38_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I11.CFG_CENTER_IMUX39_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I28.CFG_CENTER_IMUX39_5 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_GTS.CFG_CENTER_IMUX39_8 always
CFG_CENTER_MID.CFG_CENTER_BSCAN4_TDO.CFG_CENTER_IMUX39_11 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I11.CFG_CENTER_IMUX39_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I27.CFG_CENTER_IMUX39_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I12.CFG_CENTER_IMUX40_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I29.CFG_CENTER_IMUX40_5 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_GSR.CFG_CENTER_IMUX40_8 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_CSIB.CFG_CENTER_IMUX40_11 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I12.CFG_CENTER_IMUX40_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I28.CFG_CENTER_IMUX40_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I13.CFG_CENTER_IMUX41_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I30.CFG_CENTER_IMUX41_5 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_USRDONETS.CFG_CENTER_IMUX41_8 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_RDWRB.CFG_CENTER_IMUX41_11 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I13.CFG_CENTER_IMUX41_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I29.CFG_CENTER_IMUX41_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I14.CFG_CENTER_IMUX42_4 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I31.CFG_CENTER_IMUX42_5 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_USRDONEO.CFG_CENTER_IMUX42_8 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_RDWRB.CFG_CENTER_IMUX42_11 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I14.CFG_CENTER_IMUX42_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I30.CFG_CENTER_IMUX42_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP0_I15.CFG_CENTER_IMUX43_4 always
CFG_CENTER_MID.CFG_CENTER_STARTUP_PACK.CFG_CENTER_IMUX43_8 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_CSIB.CFG_CENTER_IMUX43_11 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I15.CFG_CENTER_IMUX43_12 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_I31.CFG_CENTER_IMUX43_13 always
CFG_CENTER_MID.CFG_CENTER_ICAP1_CLK.CFG_CENTER_MID_ICAP1_CLK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_10.CFG_CENTER_STARTUP_CFGCLK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_5.CFG_CENTER_STARTUP_CFGMCLK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_9.CFG_CENTER_STARTUP_EOS always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_9.CFG_CENTER_STARTUP_PREQ always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B9_5.CFG_CENTER_USR_ACCESS_CFGCLK always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_0.CFG_CENTER_USR_ACCESS_DATA0 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B11_1.CFG_CENTER_USR_ACCESS_DATA16 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_0.CFG_CENTER_USR_ACCESS_DATA1 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B12_1.CFG_CENTER_USR_ACCESS_DATA17 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA2.CFG_CENTER_USR_ACCESS_DATA2 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA3.CFG_CENTER_USR_ACCESS_DATA3 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA4.CFG_CENTER_USR_ACCESS_DATA4 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA5.CFG_CENTER_USR_ACCESS_DATA5 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA6.CFG_CENTER_USR_ACCESS_DATA6 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA7.CFG_CENTER_USR_ACCESS_DATA7 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA8.CFG_CENTER_USR_ACCESS_DATA8 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA9.CFG_CENTER_USR_ACCESS_DATA9 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA10.CFG_CENTER_USR_ACCESS_DATA10 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA11.CFG_CENTER_USR_ACCESS_DATA11 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA12.CFG_CENTER_USR_ACCESS_DATA12 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA13.CFG_CENTER_USR_ACCESS_DATA13 always
CFG_CENTER_MID.CFG_CENTER_MID_USR_ACCESS_DATA14.CFG_CENTER_USR_ACCESS_DATA14 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_0.CFG_CENTER_USR_ACCESS_DATA15 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B10_1.CFG_CENTER_USR_ACCESS_DATA31 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_0.CFG_CENTER_USR_ACCESS_DATA18 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B14_0.CFG_CENTER_USR_ACCESS_DATA19 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B15_0.CFG_CENTER_USR_ACCESS_DATA20 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B16_0.CFG_CENTER_USR_ACCESS_DATA21 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B17_0.CFG_CENTER_USR_ACCESS_DATA22 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B18_0.CFG_CENTER_USR_ACCESS_DATA23 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B19_0.CFG_CENTER_USR_ACCESS_DATA24 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B20_0.CFG_CENTER_USR_ACCESS_DATA25 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_0.CFG_CENTER_USR_ACCESS_DATA26 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B22_0.CFG_CENTER_USR_ACCESS_DATA27 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B23_0.CFG_CENTER_USR_ACCESS_DATA28 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B8_0.CFG_CENTER_USR_ACCESS_DATA29 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B9_0.CFG_CENTER_USR_ACCESS_DATA30 always
CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B13_1.CFG_CENTER_USR_ACCESS_DATAVALID always

38
virtex7/ppips_cfg_center_top.db Normal file
View File

@ -0,0 +1,38 @@
CFG_CENTER_TOP.CFG_CENTER_TOP_ICAP1_CLK.CFG_CENTER_CLK1_0 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B23_5.CFG_CENTER_DNA_PORT_DOUT always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B16_6.CFG_CENTER_EFUSE_USR_EFUSEUSR0 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B16_7.CFG_CENTER_EFUSE_USR_EFUSEUSR8 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B16_8.CFG_CENTER_EFUSE_USR_EFUSEUSR16 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B16_9.CFG_CENTER_EFUSE_USR_EFUSEUSR24 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B17_6.CFG_CENTER_EFUSE_USR_EFUSEUSR1 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B17_7.CFG_CENTER_EFUSE_USR_EFUSEUSR9 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B17_8.CFG_CENTER_EFUSE_USR_EFUSEUSR17 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B17_9.CFG_CENTER_EFUSE_USR_EFUSEUSR25 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B18_6.CFG_CENTER_EFUSE_USR_EFUSEUSR2 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B18_7.CFG_CENTER_EFUSE_USR_EFUSEUSR10 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B18_8.CFG_CENTER_EFUSE_USR_EFUSEUSR18 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B18_9.CFG_CENTER_EFUSE_USR_EFUSEUSR26 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B19_6.CFG_CENTER_EFUSE_USR_EFUSEUSR3 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B19_7.CFG_CENTER_EFUSE_USR_EFUSEUSR11 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B19_8.CFG_CENTER_EFUSE_USR_EFUSEUSR19 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B19_9.CFG_CENTER_EFUSE_USR_EFUSEUSR27 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B20_6.CFG_CENTER_EFUSE_USR_EFUSEUSR4 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B20_7.CFG_CENTER_EFUSE_USR_EFUSEUSR12 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B20_8.CFG_CENTER_EFUSE_USR_EFUSEUSR20 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B20_9.CFG_CENTER_EFUSE_USR_EFUSEUSR28 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B21_6.CFG_CENTER_EFUSE_USR_EFUSEUSR5 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B21_7.CFG_CENTER_EFUSE_USR_EFUSEUSR13 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B21_8.CFG_CENTER_EFUSE_USR_EFUSEUSR21 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B21_9.CFG_CENTER_EFUSE_USR_EFUSEUSR29 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B22_6.CFG_CENTER_EFUSE_USR_EFUSEUSR6 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B22_7.CFG_CENTER_EFUSE_USR_EFUSEUSR14 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B22_8.CFG_CENTER_EFUSE_USR_EFUSEUSR22 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B22_9.CFG_CENTER_EFUSE_USR_EFUSEUSR30 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B23_6.CFG_CENTER_EFUSE_USR_EFUSEUSR7 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B23_7.CFG_CENTER_EFUSE_USR_EFUSEUSR15 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B23_8.CFG_CENTER_EFUSE_USR_EFUSEUSR23 always
CFG_CENTER_TOP.CFG_CENTER_LOGIC_OUTS_B23_9.CFG_CENTER_EFUSE_USR_EFUSEUSR31 always
CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_READ.CFG_CENTER_IMUX41_5 always
CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_SHIFT.CFG_CENTER_IMUX42_5 always
CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_DIN.CFG_CENTER_IMUX43_5 always
CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_CLK.CFG_CENTER_TOP_DNA_PORT_CLK always

146
virtex7/ppips_clbll_l.db Normal file
View File

@ -0,0 +1,146 @@
CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always

0
virtex7/ppips_clbll_l.origin_info.db Normal file
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146
virtex7/ppips_clbll_r.db Normal file
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CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always

0
virtex7/ppips_clbll_r.origin_info.db Normal file
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virtex7/ppips_clblm_l.db Normal file
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CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always

0
virtex7/ppips_clblm_l.origin_info.db Normal file
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virtex7/ppips_clblm_r.db Normal file
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CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always

0
virtex7/ppips_clblm_r.origin_info.db Normal file
View File

128
virtex7/ppips_clk_bufg_bot_r.db Normal file
View File

@ -0,0 +1,128 @@
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_S1.CLK_BUFG_IMUX0_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_S1.CLK_BUFG_IMUX0_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_IGNORE1.CLK_BUFG_IMUX10_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_IGNORE1.CLK_BUFG_IMUX10_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_IGNORE1.CLK_BUFG_IMUX11_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_IGNORE1.CLK_BUFG_IMUX11_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_IGNORE0.CLK_BUFG_IMUX12_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_IGNORE0.CLK_BUFG_IMUX12_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_IGNORE0.CLK_BUFG_IMUX13_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_IGNORE0.CLK_BUFG_IMUX14_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_IGNORE0.CLK_BUFG_IMUX14_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_IGNORE0.CLK_BUFG_IMUX15_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_IGNORE0.CLK_BUFG_IMUX15_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_CE1.CLK_BUFG_IMUX16_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_CE1.CLK_BUFG_IMUX16_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_CE1.CLK_BUFG_IMUX17_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_CE1.CLK_BUFG_IMUX17_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_CE1.CLK_BUFG_IMUX18_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_CE1.CLK_BUFG_IMUX18_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_CE1.CLK_BUFG_IMUX19_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_CE1.CLK_BUFG_IMUX19_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_S1.CLK_BUFG_IMUX1_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_S1.CLK_BUFG_IMUX1_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_CE0.CLK_BUFG_IMUX20_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_CE0.CLK_BUFG_IMUX20_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_CE0.CLK_BUFG_IMUX21_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_CE0.CLK_BUFG_IMUX21_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_CE0.CLK_BUFG_IMUX22_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_CE0.CLK_BUFG_IMUX22_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_CE0.CLK_BUFG_IMUX23_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_CE0.CLK_BUFG_IMUX23_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_S1.CLK_BUFG_IMUX2_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_S1.CLK_BUFG_IMUX2_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_S1.CLK_BUFG_IMUX3_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_S1.CLK_BUFG_IMUX3_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_S0.CLK_BUFG_IMUX4_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_S0.CLK_BUFG_IMUX4_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_S0.CLK_BUFG_IMUX5_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_S0.CLK_BUFG_IMUX5_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_S0.CLK_BUFG_IMUX6_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_S0.CLK_BUFG_IMUX6_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_S0.CLK_BUFG_IMUX7_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_S0.CLK_BUFG_IMUX7_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_IGNORE1.CLK_BUFG_IMUX8_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_IGNORE1.CLK_BUFG_IMUX8_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_IGNORE1.CLK_BUFG_IMUX9_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_IGNORE1.CLK_BUFG_IMUX9_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always

128
virtex7/ppips_clk_bufg_top_r.db Normal file
View File

@ -0,0 +1,128 @@
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_S1.CLK_BUFG_IMUX0_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_S1.CLK_BUFG_IMUX0_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_IGNORE1.CLK_BUFG_IMUX10_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_IGNORE1.CLK_BUFG_IMUX10_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_IGNORE1.CLK_BUFG_IMUX11_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_IGNORE1.CLK_BUFG_IMUX11_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_IGNORE0.CLK_BUFG_IMUX12_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_IGNORE0.CLK_BUFG_IMUX12_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_IGNORE0.CLK_BUFG_IMUX13_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_IGNORE0.CLK_BUFG_IMUX14_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_IGNORE0.CLK_BUFG_IMUX14_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_IGNORE0.CLK_BUFG_IMUX15_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_IGNORE0.CLK_BUFG_IMUX15_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_CE1.CLK_BUFG_IMUX16_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_CE1.CLK_BUFG_IMUX16_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_CE1.CLK_BUFG_IMUX17_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_CE1.CLK_BUFG_IMUX17_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_CE1.CLK_BUFG_IMUX18_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_CE1.CLK_BUFG_IMUX18_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_CE1.CLK_BUFG_IMUX19_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_CE1.CLK_BUFG_IMUX19_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_S1.CLK_BUFG_IMUX1_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_S1.CLK_BUFG_IMUX1_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_CE0.CLK_BUFG_IMUX20_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_CE0.CLK_BUFG_IMUX20_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_CE0.CLK_BUFG_IMUX21_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_CE0.CLK_BUFG_IMUX21_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_CE0.CLK_BUFG_IMUX22_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_CE0.CLK_BUFG_IMUX22_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_CE0.CLK_BUFG_IMUX23_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_CE0.CLK_BUFG_IMUX23_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_S1.CLK_BUFG_IMUX2_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_S1.CLK_BUFG_IMUX2_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_S1.CLK_BUFG_IMUX3_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_S1.CLK_BUFG_IMUX3_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_S0.CLK_BUFG_IMUX4_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_S0.CLK_BUFG_IMUX4_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_S0.CLK_BUFG_IMUX5_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_S0.CLK_BUFG_IMUX5_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_S0.CLK_BUFG_IMUX6_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_S0.CLK_BUFG_IMUX6_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_S0.CLK_BUFG_IMUX7_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_S0.CLK_BUFG_IMUX7_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_IGNORE1.CLK_BUFG_IMUX8_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_IGNORE1.CLK_BUFG_IMUX8_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_IGNORE1.CLK_BUFG_IMUX9_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_IGNORE1.CLK_BUFG_IMUX9_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always

168
virtex7/ppips_clk_hrow_bot_r.db Normal file
View File

@ -0,0 +1,168 @@
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R4.CLK_HROW_CE_INT_BOT4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R5.CLK_HROW_CE_INT_BOT5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L4.CLK_HROW_CE_INT_BOT10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L5.CLK_HROW_CE_INT_BOT11 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN13.CLK_HROW_CK_GCLK_IN_TEST13 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN14.CLK_HROW_CK_GCLK_IN_TEST14 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN15.CLK_HROW_CK_GCLK_IN_TEST15 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN23.CLK_HROW_CK_GCLK_IN_TEST23 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN24.CLK_HROW_CK_GCLK_IN_TEST24 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN25.CLK_HROW_CK_GCLK_IN_TEST25 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST13.CLK_HROW_CK_GCLK_TEST_OUT13 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST14.CLK_HROW_CK_GCLK_TEST_OUT14 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST15.CLK_HROW_CK_GCLK_TEST_OUT15 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST23.CLK_HROW_CK_GCLK_TEST_OUT23 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST24.CLK_HROW_CK_GCLK_TEST_OUT24 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST25.CLK_HROW_CK_GCLK_TEST_OUT25 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L4.CLK_HROW_CK_HCLK_OUT_L4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L5.CLK_HROW_CK_HCLK_OUT_L5 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R4.CLK_HROW_CK_HCLK_OUT_R4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R5.CLK_HROW_CK_HCLK_OUT_R5 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_OUT.CLK_HROW_CK_IN_R_OUT_TEST always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4.CLK_HROW_CK_MUX_OUT_L4 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5.CLK_HROW_CK_MUX_OUT_L5 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4.CLK_HROW_CK_MUX_OUT_R4 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5.CLK_HROW_CK_MUX_OUT_R5 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0.CLK_HROW_CLK0_3 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0.CLK_HROW_CLK0_4 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1.CLK_HROW_CLK1_3 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1.CLK_HROW_CLK1_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4.CLK_HROW_IMUX4_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4.CLK_HROW_IMUX4_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5.CLK_HROW_IMUX5_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5.CLK_HROW_IMUX5_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always

168
virtex7/ppips_clk_hrow_top_r.db Normal file
View File

@ -0,0 +1,168 @@
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R4.CLK_HROW_CE_INT_BOT4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R5.CLK_HROW_CE_INT_BOT5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L4.CLK_HROW_CE_INT_BOT10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L5.CLK_HROW_CE_INT_BOT11 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN13.CLK_HROW_CK_GCLK_IN_TEST13 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN14.CLK_HROW_CK_GCLK_IN_TEST14 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN15.CLK_HROW_CK_GCLK_IN_TEST15 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN23.CLK_HROW_CK_GCLK_IN_TEST23 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN24.CLK_HROW_CK_GCLK_IN_TEST24 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN25.CLK_HROW_CK_GCLK_IN_TEST25 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST13.CLK_HROW_CK_GCLK_TEST_OUT13 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST14.CLK_HROW_CK_GCLK_TEST_OUT14 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST15.CLK_HROW_CK_GCLK_TEST_OUT15 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST23.CLK_HROW_CK_GCLK_TEST_OUT23 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST24.CLK_HROW_CK_GCLK_TEST_OUT24 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST25.CLK_HROW_CK_GCLK_TEST_OUT25 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L4.CLK_HROW_CK_HCLK_OUT_L4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L5.CLK_HROW_CK_HCLK_OUT_L5 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R4.CLK_HROW_CK_HCLK_OUT_R4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R5.CLK_HROW_CK_HCLK_OUT_R5 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_OUT.CLK_HROW_CK_IN_R_OUT_TEST always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4.CLK_HROW_CK_MUX_OUT_L4 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5.CLK_HROW_CK_MUX_OUT_L5 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4.CLK_HROW_CK_MUX_OUT_R4 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5.CLK_HROW_CK_MUX_OUT_R5 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0.CLK_HROW_CLK0_3 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0.CLK_HROW_CLK0_4 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1.CLK_HROW_CLK1_3 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1.CLK_HROW_CLK1_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4.CLK_HROW_IMUX4_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4.CLK_HROW_IMUX4_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5.CLK_HROW_IMUX5_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5.CLK_HROW_IMUX5_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always

155
virtex7/ppips_cmt_top_l_lower_b.db Normal file
View File

@ -0,0 +1,155 @@
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always

234
virtex7/ppips_cmt_top_l_lower_t.db Normal file
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@ -0,0 +1,234 @@
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always

325
virtex7/ppips_cmt_top_l_upper_b.db Normal file
View File

@ -0,0 +1,325 @@
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDENABLE_FIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_R_PHASER_IN_C_WRCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_R_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_R_PHASER_OUT_C_RDCLK_FIFO always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always

136
virtex7/ppips_cmt_top_l_upper_t.db Normal file
View File

@ -0,0 +1,136 @@
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always

155
virtex7/ppips_cmt_top_r_lower_b.db Normal file
View File

@ -0,0 +1,155 @@
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always

234
virtex7/ppips_cmt_top_r_lower_t.db Normal file
View File

@ -0,0 +1,234 @@
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always

325
virtex7/ppips_cmt_top_r_upper_b.db Normal file
View File

@ -0,0 +1,325 @@
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_PHASER_IN_C_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_PHASER_IN_D_WRCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDENABLE_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_PHASER_OUT_C_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_PHASER_OUT_D_RDCLK_TOFIFO always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always

136
virtex7/ppips_cmt_top_r_upper_t.db Normal file
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@ -0,0 +1,136 @@
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always

560
virtex7/ppips_dsp_l.db Normal file
View File

@ -0,0 +1,560 @@
DSP_L.DSP_1_ACIN0.DSP_0_ACOUT0 always
DSP_L.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_L.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_L.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_L.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_L.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_L.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_L.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_L.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_L.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_L.DSP_1_ACIN10.DSP_0_ACOUT10 always
DSP_L.DSP_1_ACIN11.DSP_0_ACOUT11 always
DSP_L.DSP_1_ACIN12.DSP_0_ACOUT12 always
DSP_L.DSP_1_ACIN13.DSP_0_ACOUT13 always
DSP_L.DSP_1_ACIN14.DSP_0_ACOUT14 always
DSP_L.DSP_1_ACIN15.DSP_0_ACOUT15 always
DSP_L.DSP_1_ACIN16.DSP_0_ACOUT16 always
DSP_L.DSP_1_ACIN17.DSP_0_ACOUT17 always
DSP_L.DSP_1_ACIN18.DSP_0_ACOUT18 always
DSP_L.DSP_1_ACIN19.DSP_0_ACOUT19 always
DSP_L.DSP_1_ACIN20.DSP_0_ACOUT20 always
DSP_L.DSP_1_ACIN21.DSP_0_ACOUT21 always
DSP_L.DSP_1_ACIN22.DSP_0_ACOUT22 always
DSP_L.DSP_1_ACIN23.DSP_0_ACOUT23 always
DSP_L.DSP_1_ACIN24.DSP_0_ACOUT24 always
DSP_L.DSP_1_ACIN25.DSP_0_ACOUT25 always
DSP_L.DSP_1_ACIN26.DSP_0_ACOUT26 always
DSP_L.DSP_1_ACIN27.DSP_0_ACOUT27 always
DSP_L.DSP_1_ACIN28.DSP_0_ACOUT28 always
DSP_L.DSP_1_ACIN29.DSP_0_ACOUT29 always
DSP_L.DSP_1_BCIN0.DSP_0_BCOUT0 always
DSP_L.DSP_1_BCIN1.DSP_0_BCOUT1 always
DSP_L.DSP_1_BCIN2.DSP_0_BCOUT2 always
DSP_L.DSP_1_BCIN3.DSP_0_BCOUT3 always
DSP_L.DSP_1_BCIN4.DSP_0_BCOUT4 always
DSP_L.DSP_1_BCIN5.DSP_0_BCOUT5 always
DSP_L.DSP_1_BCIN6.DSP_0_BCOUT6 always
DSP_L.DSP_1_BCIN7.DSP_0_BCOUT7 always
DSP_L.DSP_1_BCIN8.DSP_0_BCOUT8 always
DSP_L.DSP_1_BCIN9.DSP_0_BCOUT9 always
DSP_L.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_L.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_L.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_L.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_L.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_L.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_L.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_L.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_L.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_L.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_L.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_L.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_L.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_L.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_L.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_L.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_L.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_L.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_L.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_L.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_L.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_L.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_L.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_L.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_L.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_L.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_L.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_L.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_L.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_L.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_L.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_L.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_L.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_L.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_L.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_L.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_L.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_L.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_L.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_L.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_L.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_L.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_L.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_L.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_L.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_L.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_L.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_L.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_L.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_L.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_L.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_L.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_L.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_L.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_L.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_L.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_L.DSP_LOGIC_OUTS_B9_0.DSP_0_P42 always
DSP_L.DSP_LOGIC_OUTS_B9_4.DSP_0_P44 always
DSP_L.DSP_LOGIC_OUTS_B8_0.DSP_0_P43 always
DSP_L.DSP_LOGIC_OUTS_B8_4.DSP_0_P47 always
DSP_L.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_L.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_L.DSP_1_PCIN0.DSP_0_PCOUT0 always
DSP_L.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_L.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_L.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_L.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_L.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_L.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_L.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_L.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_L.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_L.DSP_1_PCIN10.DSP_0_PCOUT10 always
DSP_L.DSP_1_PCIN11.DSP_0_PCOUT11 always
DSP_L.DSP_1_PCIN12.DSP_0_PCOUT12 always
DSP_L.DSP_1_PCIN13.DSP_0_PCOUT13 always
DSP_L.DSP_1_PCIN14.DSP_0_PCOUT14 always
DSP_L.DSP_1_PCIN15.DSP_0_PCOUT15 always
DSP_L.DSP_1_PCIN16.DSP_0_PCOUT16 always
DSP_L.DSP_1_PCIN17.DSP_0_PCOUT17 always
DSP_L.DSP_1_PCIN18.DSP_0_PCOUT18 always
DSP_L.DSP_1_PCIN19.DSP_0_PCOUT19 always
DSP_L.DSP_1_PCIN20.DSP_0_PCOUT20 always
DSP_L.DSP_1_PCIN21.DSP_0_PCOUT21 always
DSP_L.DSP_1_PCIN22.DSP_0_PCOUT22 always
DSP_L.DSP_1_PCIN23.DSP_0_PCOUT23 always
DSP_L.DSP_1_PCIN24.DSP_0_PCOUT24 always
DSP_L.DSP_1_PCIN25.DSP_0_PCOUT25 always
DSP_L.DSP_1_PCIN26.DSP_0_PCOUT26 always
DSP_L.DSP_1_PCIN27.DSP_0_PCOUT27 always
DSP_L.DSP_1_PCIN28.DSP_0_PCOUT28 always
DSP_L.DSP_1_PCIN29.DSP_0_PCOUT29 always
DSP_L.DSP_1_PCIN30.DSP_0_PCOUT30 always
DSP_L.DSP_1_PCIN31.DSP_0_PCOUT31 always
DSP_L.DSP_1_PCIN32.DSP_0_PCOUT32 always
DSP_L.DSP_1_PCIN33.DSP_0_PCOUT33 always
DSP_L.DSP_1_PCIN34.DSP_0_PCOUT34 always
DSP_L.DSP_1_PCIN35.DSP_0_PCOUT35 always
DSP_L.DSP_1_PCIN36.DSP_0_PCOUT36 always
DSP_L.DSP_1_PCIN37.DSP_0_PCOUT37 always
DSP_L.DSP_1_PCIN38.DSP_0_PCOUT38 always
DSP_L.DSP_1_PCIN39.DSP_0_PCOUT39 always
DSP_L.DSP_1_PCIN40.DSP_0_PCOUT40 always
DSP_L.DSP_1_PCIN41.DSP_0_PCOUT41 always
DSP_L.DSP_1_PCIN42.DSP_0_PCOUT42 always
DSP_L.DSP_1_PCIN43.DSP_0_PCOUT43 always
DSP_L.DSP_1_PCIN44.DSP_0_PCOUT44 always
DSP_L.DSP_1_PCIN45.DSP_0_PCOUT45 always
DSP_L.DSP_1_PCIN46.DSP_0_PCOUT46 always
DSP_L.DSP_1_PCIN47.DSP_0_PCOUT47 always
DSP_L.DSP_LOGIC_OUTS_B9_2.DSP_0_UNDERFLOW always
DSP_L.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_L.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_L.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_L.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_L.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_L.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_L.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_L.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_L.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_L.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_L.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_L.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_L.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_L.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_L.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_L.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_L.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_L.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_L.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_L.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_L.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_L.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_L.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_L.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_L.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_L.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_L.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_L.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_L.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_L.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_L.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_L.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_L.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_L.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_L.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_L.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_L.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_L.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_L.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_L.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_L.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_L.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_L.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_L.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_L.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_L.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_L.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_L.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_L.DSP_CARRYCASCOUT.DSP_1_CARRYCASCOUT always
DSP_L.DSP_LOGIC_OUTS_B8_3.DSP_1_CARRYOUT0 always
DSP_L.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_L.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_L.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_L.DSP_MULTSIGNOUT.DSP_1_MULTSIGNOUT always
DSP_L.DSP_LOGIC_OUTS_B8_2.DSP_1_OVERFLOW always
DSP_L.DSP_LOGIC_OUTS_B3_0.DSP_1_P0 always
DSP_L.DSP_LOGIC_OUTS_B3_1.DSP_1_P4 always
DSP_L.DSP_LOGIC_OUTS_B3_2.DSP_1_P8 always
DSP_L.DSP_LOGIC_OUTS_B3_3.DSP_1_P12 always
DSP_L.DSP_LOGIC_OUTS_B3_4.DSP_1_P16 always
DSP_L.DSP_LOGIC_OUTS_B1_0.DSP_1_P1 always
DSP_L.DSP_LOGIC_OUTS_B1_1.DSP_1_P5 always
DSP_L.DSP_LOGIC_OUTS_B1_2.DSP_1_P9 always
DSP_L.DSP_LOGIC_OUTS_B1_3.DSP_1_P13 always
DSP_L.DSP_LOGIC_OUTS_B1_4.DSP_1_P17 always
DSP_L.DSP_LOGIC_OUTS_B6_0.DSP_1_P2 always
DSP_L.DSP_LOGIC_OUTS_B6_1.DSP_1_P6 always
DSP_L.DSP_LOGIC_OUTS_B6_2.DSP_1_P10 always
DSP_L.DSP_LOGIC_OUTS_B6_3.DSP_1_P14 always
DSP_L.DSP_LOGIC_OUTS_B6_4.DSP_1_P18 always
DSP_L.DSP_LOGIC_OUTS_B4_0.DSP_1_P3 always
DSP_L.DSP_LOGIC_OUTS_B4_1.DSP_1_P7 always
DSP_L.DSP_LOGIC_OUTS_B4_2.DSP_1_P11 always
DSP_L.DSP_LOGIC_OUTS_B4_3.DSP_1_P15 always
DSP_L.DSP_LOGIC_OUTS_B4_4.DSP_1_P19 always
DSP_L.DSP_LOGIC_OUTS_B7_0.DSP_1_P20 always
DSP_L.DSP_LOGIC_OUTS_B7_1.DSP_1_P24 always
DSP_L.DSP_LOGIC_OUTS_B7_2.DSP_1_P28 always
DSP_L.DSP_LOGIC_OUTS_B7_3.DSP_1_P32 always
DSP_L.DSP_LOGIC_OUTS_B7_4.DSP_1_P36 always
DSP_L.DSP_LOGIC_OUTS_B5_0.DSP_1_P21 always
DSP_L.DSP_LOGIC_OUTS_B5_1.DSP_1_P25 always
DSP_L.DSP_LOGIC_OUTS_B5_2.DSP_1_P29 always
DSP_L.DSP_LOGIC_OUTS_B5_3.DSP_1_P33 always
DSP_L.DSP_LOGIC_OUTS_B5_4.DSP_1_P39 always
DSP_L.DSP_LOGIC_OUTS_B2_0.DSP_1_P22 always
DSP_L.DSP_LOGIC_OUTS_B2_1.DSP_1_P26 always
DSP_L.DSP_LOGIC_OUTS_B2_2.DSP_1_P30 always
DSP_L.DSP_LOGIC_OUTS_B2_3.DSP_1_P34 always
DSP_L.DSP_LOGIC_OUTS_B2_4.DSP_1_P38 always
DSP_L.DSP_LOGIC_OUTS_B0_0.DSP_1_P23 always
DSP_L.DSP_LOGIC_OUTS_B0_1.DSP_1_P27 always
DSP_L.DSP_LOGIC_OUTS_B0_2.DSP_1_P31 always
DSP_L.DSP_LOGIC_OUTS_B0_3.DSP_1_P35 always
DSP_L.DSP_LOGIC_OUTS_B0_4.DSP_1_P37 always
DSP_L.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_L.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_L.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_L.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_L.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_L.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_L.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_L.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_L.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_L.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_L.DSP_PCOUT0.DSP_1_PCOUT0 always
DSP_L.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_L.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_L.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_L.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_L.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_L.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_L.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_L.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_L.DSP_PCOUT9.DSP_1_PCOUT9 always
DSP_L.DSP_PCOUT10.DSP_1_PCOUT10 always
DSP_L.DSP_PCOUT11.DSP_1_PCOUT11 always
DSP_L.DSP_PCOUT12.DSP_1_PCOUT12 always
DSP_L.DSP_PCOUT13.DSP_1_PCOUT13 always
DSP_L.DSP_PCOUT14.DSP_1_PCOUT14 always
DSP_L.DSP_PCOUT15.DSP_1_PCOUT15 always
DSP_L.DSP_PCOUT16.DSP_1_PCOUT16 always
DSP_L.DSP_PCOUT17.DSP_1_PCOUT17 always
DSP_L.DSP_PCOUT18.DSP_1_PCOUT18 always
DSP_L.DSP_PCOUT19.DSP_1_PCOUT19 always
DSP_L.DSP_PCOUT20.DSP_1_PCOUT20 always
DSP_L.DSP_PCOUT21.DSP_1_PCOUT21 always
DSP_L.DSP_PCOUT22.DSP_1_PCOUT22 always
DSP_L.DSP_PCOUT23.DSP_1_PCOUT23 always
DSP_L.DSP_PCOUT24.DSP_1_PCOUT24 always
DSP_L.DSP_PCOUT25.DSP_1_PCOUT25 always
DSP_L.DSP_PCOUT26.DSP_1_PCOUT26 always
DSP_L.DSP_PCOUT27.DSP_1_PCOUT27 always
DSP_L.DSP_PCOUT28.DSP_1_PCOUT28 always
DSP_L.DSP_PCOUT29.DSP_1_PCOUT29 always
DSP_L.DSP_PCOUT30.DSP_1_PCOUT30 always
DSP_L.DSP_PCOUT31.DSP_1_PCOUT31 always
DSP_L.DSP_PCOUT32.DSP_1_PCOUT32 always
DSP_L.DSP_PCOUT33.DSP_1_PCOUT33 always
DSP_L.DSP_PCOUT34.DSP_1_PCOUT34 always
DSP_L.DSP_PCOUT35.DSP_1_PCOUT35 always
DSP_L.DSP_PCOUT36.DSP_1_PCOUT36 always
DSP_L.DSP_PCOUT37.DSP_1_PCOUT37 always
DSP_L.DSP_PCOUT38.DSP_1_PCOUT38 always
DSP_L.DSP_PCOUT39.DSP_1_PCOUT39 always
DSP_L.DSP_PCOUT40.DSP_1_PCOUT40 always
DSP_L.DSP_PCOUT41.DSP_1_PCOUT41 always
DSP_L.DSP_PCOUT42.DSP_1_PCOUT42 always
DSP_L.DSP_PCOUT43.DSP_1_PCOUT43 always
DSP_L.DSP_PCOUT44.DSP_1_PCOUT44 always
DSP_L.DSP_PCOUT45.DSP_1_PCOUT45 always
DSP_L.DSP_PCOUT46.DSP_1_PCOUT46 always
DSP_L.DSP_PCOUT47.DSP_1_PCOUT47 always
DSP_L.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_L.DSP_0_CLK.DSP_CLK0_1 always
DSP_L.DSP_1_CLK.DSP_CLK0_3 always
DSP_L.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_L.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_L.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_L.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_L.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_L.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_L.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_L.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_L.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_L.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_L.DSP_1_B3.DSP_IMUX0_0 always
DSP_L.DSP_1_B15.DSP_IMUX0_3 always
DSP_L.DSP_0_CEA2.DSP_IMUX0_1 always
DSP_L.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_L.DSP_1_ALUMODE0.DSP_IMUX0_4 always
DSP_L.DSP_1_C21.DSP_IMUX10_0 always
DSP_L.DSP_1_C29.DSP_IMUX10_2 always
DSP_L.DSP_1_C33.DSP_IMUX10_3 always
DSP_L.DSP_1_C39.DSP_IMUX10_4 always
DSP_L.DSP_1_B5.DSP_IMUX10_1 always
DSP_L.DSP_1_A1.DSP_IMUX11_0 always
DSP_L.DSP_1_A5.DSP_IMUX11_1 always
DSP_L.DSP_1_A9.DSP_IMUX11_2 always
DSP_L.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_L.DSP_1_C46.DSP_IMUX11_4 always
DSP_L.DSP_1_C22.DSP_IMUX12_0 always
DSP_L.DSP_1_C26.DSP_IMUX12_1 always
DSP_L.DSP_1_C34.DSP_IMUX12_3 always
DSP_L.DSP_1_C38.DSP_IMUX12_4 always
DSP_L.DSP_0_OPMODE5.DSP_IMUX12_2 always
DSP_L.DSP_1_A2.DSP_IMUX13_0 always
DSP_L.DSP_1_A6.DSP_IMUX13_1 always
DSP_L.DSP_1_A10.DSP_IMUX13_2 always
DSP_L.DSP_0_ALUMODE1.DSP_IMUX13_3 always
DSP_L.DSP_1_C18.DSP_IMUX13_4 always
DSP_L.DSP_1_B0.DSP_IMUX14_0 always
DSP_L.DSP_1_B8.DSP_IMUX14_2 always
DSP_L.DSP_1_C24.DSP_IMUX14_1 always
DSP_L.DSP_0_CARRYINSEL1.DSP_IMUX14_3 always
DSP_L.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_L.DSP_1_A0.DSP_IMUX15_0 always
DSP_L.DSP_1_A4.DSP_IMUX15_1 always
DSP_L.DSP_1_A8.DSP_IMUX15_2 always
DSP_L.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_L.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_L.DSP_0_C41.DSP_IMUX16_0 always
DSP_L.DSP_0_B7.DSP_IMUX16_1 always
DSP_L.DSP_0_B11.DSP_IMUX16_2 always
DSP_L.DSP_1_CEB2.DSP_IMUX16_3 always
DSP_L.DSP_1_OPMODE3.DSP_IMUX16_4 always
DSP_L.DSP_0_A3.DSP_IMUX17_0 always
DSP_L.DSP_0_A7.DSP_IMUX17_1 always
DSP_L.DSP_0_A11.DSP_IMUX17_2 always
DSP_L.DSP_1_CEA2.DSP_IMUX17_3 always
DSP_L.DSP_1_OPMODE4.DSP_IMUX17_4 always
DSP_L.DSP_0_C21.DSP_IMUX18_0 always
DSP_L.DSP_0_C33.DSP_IMUX18_3 always
DSP_L.DSP_0_C39.DSP_IMUX18_4 always
DSP_L.DSP_0_B5.DSP_IMUX18_1 always
DSP_L.DSP_0_B9.DSP_IMUX18_2 always
DSP_L.DSP_0_A1.DSP_IMUX19_0 always
DSP_L.DSP_0_A5.DSP_IMUX19_1 always
DSP_L.DSP_0_A9.DSP_IMUX19_2 always
DSP_L.DSP_1_CEM.DSP_IMUX19_3 always
DSP_L.DSP_0_C46.DSP_IMUX19_4 always
DSP_L.DSP_0_C3.DSP_IMUX1_0 always
DSP_L.DSP_0_C19.DSP_IMUX1_4 always
DSP_L.DSP_0_CEB2.DSP_IMUX1_1 always
DSP_L.DSP_0_CEM.DSP_IMUX1_2 always
DSP_L.DSP_1_B13.DSP_IMUX1_3 always
DSP_L.DSP_0_C22.DSP_IMUX20_0 always
DSP_L.DSP_0_C26.DSP_IMUX20_1 always
DSP_L.DSP_0_C34.DSP_IMUX20_3 always
DSP_L.DSP_0_C38.DSP_IMUX20_4 always
DSP_L.DSP_0_OPMODE4.DSP_IMUX20_2 always
DSP_L.DSP_0_A2.DSP_IMUX21_0 always
DSP_L.DSP_0_A6.DSP_IMUX21_1 always
DSP_L.DSP_0_A10.DSP_IMUX21_2 always
DSP_L.DSP_0_ALUMODE0.DSP_IMUX21_3 always
DSP_L.DSP_0_C18.DSP_IMUX21_4 always
DSP_L.DSP_0_B0.DSP_IMUX22_0 always
DSP_L.DSP_0_B8.DSP_IMUX22_2 always
DSP_L.DSP_0_C24.DSP_IMUX22_1 always
DSP_L.DSP_1_C32.DSP_IMUX22_3 always
DSP_L.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_L.DSP_0_A0.DSP_IMUX23_0 always
DSP_L.DSP_0_A4.DSP_IMUX23_1 always
DSP_L.DSP_0_A8.DSP_IMUX23_2 always
DSP_L.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_L.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_L.DSP_1_C23.DSP_IMUX24_0 always
DSP_L.DSP_1_C27.DSP_IMUX24_1 always
DSP_L.DSP_1_C31.DSP_IMUX24_2 always
DSP_L.DSP_1_C35.DSP_IMUX24_3 always
DSP_L.DSP_1_C37.DSP_IMUX24_4 always
DSP_L.DSP_1_C43.DSP_IMUX25_0 always
DSP_L.DSP_1_C7.DSP_IMUX25_1 always
DSP_L.DSP_1_C11.DSP_IMUX25_2 always
DSP_L.DSP_1_C15.DSP_IMUX25_3 always
DSP_L.DSP_1_C47.DSP_IMUX25_4 always
DSP_L.DSP_1_B1.DSP_IMUX26_0 always
DSP_L.DSP_1_C25.DSP_IMUX26_1 always
DSP_L.DSP_1_C44.DSP_IMUX26_4 always
DSP_L.DSP_1_CEP.DSP_IMUX26_2 always
DSP_L.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_L.DSP_1_C40.DSP_IMUX27_0 always
DSP_L.DSP_1_C5.DSP_IMUX27_1 always
DSP_L.DSP_1_C13.DSP_IMUX27_3 always
DSP_L.DSP_1_C17.DSP_IMUX27_4 always
DSP_L.DSP_0_OPMODE2.DSP_IMUX27_2 always
DSP_L.DSP_1_B2.DSP_IMUX28_0 always
DSP_L.DSP_1_B6.DSP_IMUX28_1 always
DSP_L.DSP_1_C30.DSP_IMUX28_2 always
DSP_L.DSP_1_OPMODE0.DSP_IMUX28_3 always
DSP_L.DSP_1_CARRYINSEL1.DSP_IMUX28_4 always
DSP_L.DSP_1_C2.DSP_IMUX29_0 always
DSP_L.DSP_1_C6.DSP_IMUX29_1 always
DSP_L.DSP_1_C10.DSP_IMUX29_2 always
DSP_L.DSP_1_C14.DSP_IMUX29_3 always
DSP_L.DSP_1_C45.DSP_IMUX29_4 always
DSP_L.DSP_1_C42.DSP_IMUX2_0 always
DSP_L.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_L.DSP_0_C29.DSP_IMUX2_2 always
DSP_L.DSP_0_B15.DSP_IMUX2_3 always
DSP_L.DSP_1_B17.DSP_IMUX2_4 always
DSP_L.DSP_1_C20.DSP_IMUX30_0 always
DSP_L.DSP_1_C36.DSP_IMUX30_4 always
DSP_L.DSP_1_B4.DSP_IMUX30_1 always
DSP_L.DSP_0_OPMODE1.DSP_IMUX30_2 always
DSP_L.DSP_0_CARRYINSEL0.DSP_IMUX30_3 always
DSP_L.DSP_1_C0.DSP_IMUX31_0 always
DSP_L.DSP_1_C4.DSP_IMUX31_1 always
DSP_L.DSP_1_C8.DSP_IMUX31_2 always
DSP_L.DSP_1_C12.DSP_IMUX31_3 always
DSP_L.DSP_1_C16.DSP_IMUX31_4 always
DSP_L.DSP_0_C23.DSP_IMUX32_0 always
DSP_L.DSP_0_C27.DSP_IMUX32_1 always
DSP_L.DSP_0_C31.DSP_IMUX32_2 always
DSP_L.DSP_0_C35.DSP_IMUX32_3 always
DSP_L.DSP_0_C37.DSP_IMUX32_4 always
DSP_L.DSP_0_C43.DSP_IMUX33_0 always
DSP_L.DSP_0_C7.DSP_IMUX33_1 always
DSP_L.DSP_0_C11.DSP_IMUX33_2 always
DSP_L.DSP_0_C15.DSP_IMUX33_3 always
DSP_L.DSP_0_C47.DSP_IMUX33_4 always
DSP_L.DSP_0_B1.DSP_IMUX34_0 always
DSP_L.DSP_0_C25.DSP_IMUX34_1 always
DSP_L.DSP_0_C44.DSP_IMUX34_4 always
DSP_L.DSP_0_CEP.DSP_IMUX34_2 always
DSP_L.DSP_1_CEC.DSP_IMUX34_3 always
DSP_L.DSP_0_C40.DSP_IMUX35_0 always
DSP_L.DSP_0_C5.DSP_IMUX35_1 always
DSP_L.DSP_0_C13.DSP_IMUX35_3 always
DSP_L.DSP_0_C17.DSP_IMUX35_4 always
DSP_L.DSP_0_OPMODE0.DSP_IMUX35_2 always
DSP_L.DSP_0_B2.DSP_IMUX36_0 always
DSP_L.DSP_0_B6.DSP_IMUX36_1 always
DSP_L.DSP_0_B10.DSP_IMUX36_2 always
DSP_L.DSP_1_OPMODE2.DSP_IMUX36_3 always
DSP_L.DSP_1_CARRYINSEL0.DSP_IMUX36_4 always
DSP_L.DSP_0_C2.DSP_IMUX37_0 always
DSP_L.DSP_0_C6.DSP_IMUX37_1 always
DSP_L.DSP_0_C10.DSP_IMUX37_2 always
DSP_L.DSP_0_C14.DSP_IMUX37_3 always
DSP_L.DSP_0_C45.DSP_IMUX37_4 always
DSP_L.DSP_0_C20.DSP_IMUX38_0 always
DSP_L.DSP_0_C32.DSP_IMUX38_3 always
DSP_L.DSP_0_C36.DSP_IMUX38_4 always
DSP_L.DSP_0_B4.DSP_IMUX38_1 always
DSP_L.DSP_0_OPMODE3.DSP_IMUX38_2 always
DSP_L.DSP_0_C0.DSP_IMUX39_0 always
DSP_L.DSP_0_C4.DSP_IMUX39_1 always
DSP_L.DSP_0_C8.DSP_IMUX39_2 always
DSP_L.DSP_0_C12.DSP_IMUX39_3 always
DSP_L.DSP_0_C16.DSP_IMUX39_4 always
DSP_L.DSP_0_C1.DSP_IMUX3_0 always
DSP_L.DSP_0_C9.DSP_IMUX3_2 always
DSP_L.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_L.DSP_0_B13.DSP_IMUX3_3 always
DSP_L.DSP_0_B17.DSP_IMUX3_4 always
DSP_L.DSP_0_B3.DSP_IMUX40_0 always
DSP_L.DSP_0_CEA1.DSP_IMUX40_1 always
DSP_L.DSP_0_CEC.DSP_IMUX40_2 always
DSP_L.DSP_1_B14.DSP_IMUX40_3 always
DSP_L.DSP_1_ALUMODE1.DSP_IMUX40_4 always
DSP_L.DSP_1_C3.DSP_IMUX41_0 always
DSP_L.DSP_1_C19.DSP_IMUX41_4 always
DSP_L.DSP_0_CEB1.DSP_IMUX41_1 always
DSP_L.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_L.DSP_1_B12.DSP_IMUX41_3 always
DSP_L.DSP_0_C42.DSP_IMUX42_0 always
DSP_L.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_L.DSP_1_B9.DSP_IMUX42_2 always
DSP_L.DSP_1_B16.DSP_IMUX42_4 always
DSP_L.DSP_0_B14.DSP_IMUX42_3 always
DSP_L.DSP_1_C1.DSP_IMUX43_0 always
DSP_L.DSP_1_C9.DSP_IMUX43_2 always
DSP_L.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_L.DSP_0_B12.DSP_IMUX43_3 always
DSP_L.DSP_0_B16.DSP_IMUX43_4 always
DSP_L.DSP_1_A22.DSP_IMUX44_0 always
DSP_L.DSP_1_A26.DSP_IMUX44_1 always
DSP_L.DSP_1_A14.DSP_IMUX44_3 always
DSP_L.DSP_1_A18.DSP_IMUX44_4 always
DSP_L.DSP_1_B10.DSP_IMUX44_2 always
DSP_L.DSP_1_A20.DSP_IMUX45_0 always
DSP_L.DSP_1_A24.DSP_IMUX45_1 always
DSP_L.DSP_1_A28.DSP_IMUX45_2 always
DSP_L.DSP_1_A12.DSP_IMUX45_3 always
DSP_L.DSP_1_A16.DSP_IMUX45_4 always
DSP_L.DSP_0_A22.DSP_IMUX46_0 always
DSP_L.DSP_0_A26.DSP_IMUX46_1 always
DSP_L.DSP_0_A14.DSP_IMUX46_3 always
DSP_L.DSP_0_A18.DSP_IMUX46_4 always
DSP_L.DSP_1_C28.DSP_IMUX46_2 always
DSP_L.DSP_0_A20.DSP_IMUX47_0 always
DSP_L.DSP_0_A24.DSP_IMUX47_1 always
DSP_L.DSP_0_A28.DSP_IMUX47_2 always
DSP_L.DSP_0_A12.DSP_IMUX47_3 always
DSP_L.DSP_0_A16.DSP_IMUX47_4 always
DSP_L.DSP_1_A23.DSP_IMUX4_0 always
DSP_L.DSP_1_A27.DSP_IMUX4_1 always
DSP_L.DSP_1_A15.DSP_IMUX4_3 always
DSP_L.DSP_1_A19.DSP_IMUX4_4 always
DSP_L.DSP_0_C30.DSP_IMUX4_2 always
DSP_L.DSP_1_A21.DSP_IMUX5_0 always
DSP_L.DSP_1_A25.DSP_IMUX5_1 always
DSP_L.DSP_1_A29.DSP_IMUX5_2 always
DSP_L.DSP_1_A13.DSP_IMUX5_3 always
DSP_L.DSP_1_A17.DSP_IMUX5_4 always
DSP_L.DSP_0_A23.DSP_IMUX6_0 always
DSP_L.DSP_0_A27.DSP_IMUX6_1 always
DSP_L.DSP_0_A15.DSP_IMUX6_3 always
DSP_L.DSP_0_A19.DSP_IMUX6_4 always
DSP_L.DSP_0_C28.DSP_IMUX6_2 always
DSP_L.DSP_0_A21.DSP_IMUX7_0 always
DSP_L.DSP_0_A25.DSP_IMUX7_1 always
DSP_L.DSP_0_A29.DSP_IMUX7_2 always
DSP_L.DSP_0_A13.DSP_IMUX7_3 always
DSP_L.DSP_0_A17.DSP_IMUX7_4 always
DSP_L.DSP_1_C41.DSP_IMUX8_0 always
DSP_L.DSP_1_B7.DSP_IMUX8_1 always
DSP_L.DSP_1_B11.DSP_IMUX8_2 always
DSP_L.DSP_1_CEB1.DSP_IMUX8_3 always
DSP_L.DSP_1_OPMODE1.DSP_IMUX8_4 always
DSP_L.DSP_1_A3.DSP_IMUX9_0 always
DSP_L.DSP_1_A7.DSP_IMUX9_1 always
DSP_L.DSP_1_A11.DSP_IMUX9_2 always
DSP_L.DSP_1_CEA1.DSP_IMUX9_3 always
DSP_L.DSP_1_OPMODE5.DSP_IMUX9_4 always

0
virtex7/ppips_dsp_l.origin_info.db Normal file
View File

560
virtex7/ppips_dsp_r.db Normal file
View File

@ -0,0 +1,560 @@
DSP_R.DSP_1_ACIN0.DSP_0_ACOUT0 always
DSP_R.DSP_1_ACIN1.DSP_0_ACOUT1 always
DSP_R.DSP_1_ACIN2.DSP_0_ACOUT2 always
DSP_R.DSP_1_ACIN3.DSP_0_ACOUT3 always
DSP_R.DSP_1_ACIN4.DSP_0_ACOUT4 always
DSP_R.DSP_1_ACIN5.DSP_0_ACOUT5 always
DSP_R.DSP_1_ACIN6.DSP_0_ACOUT6 always
DSP_R.DSP_1_ACIN7.DSP_0_ACOUT7 always
DSP_R.DSP_1_ACIN8.DSP_0_ACOUT8 always
DSP_R.DSP_1_ACIN9.DSP_0_ACOUT9 always
DSP_R.DSP_1_ACIN10.DSP_0_ACOUT10 always
DSP_R.DSP_1_ACIN11.DSP_0_ACOUT11 always
DSP_R.DSP_1_ACIN12.DSP_0_ACOUT12 always
DSP_R.DSP_1_ACIN13.DSP_0_ACOUT13 always
DSP_R.DSP_1_ACIN14.DSP_0_ACOUT14 always
DSP_R.DSP_1_ACIN15.DSP_0_ACOUT15 always
DSP_R.DSP_1_ACIN16.DSP_0_ACOUT16 always
DSP_R.DSP_1_ACIN17.DSP_0_ACOUT17 always
DSP_R.DSP_1_ACIN18.DSP_0_ACOUT18 always
DSP_R.DSP_1_ACIN19.DSP_0_ACOUT19 always
DSP_R.DSP_1_ACIN20.DSP_0_ACOUT20 always
DSP_R.DSP_1_ACIN21.DSP_0_ACOUT21 always
DSP_R.DSP_1_ACIN22.DSP_0_ACOUT22 always
DSP_R.DSP_1_ACIN23.DSP_0_ACOUT23 always
DSP_R.DSP_1_ACIN24.DSP_0_ACOUT24 always
DSP_R.DSP_1_ACIN25.DSP_0_ACOUT25 always
DSP_R.DSP_1_ACIN26.DSP_0_ACOUT26 always
DSP_R.DSP_1_ACIN27.DSP_0_ACOUT27 always
DSP_R.DSP_1_ACIN28.DSP_0_ACOUT28 always
DSP_R.DSP_1_ACIN29.DSP_0_ACOUT29 always
DSP_R.DSP_1_BCIN0.DSP_0_BCOUT0 always
DSP_R.DSP_1_BCIN1.DSP_0_BCOUT1 always
DSP_R.DSP_1_BCIN2.DSP_0_BCOUT2 always
DSP_R.DSP_1_BCIN3.DSP_0_BCOUT3 always
DSP_R.DSP_1_BCIN4.DSP_0_BCOUT4 always
DSP_R.DSP_1_BCIN5.DSP_0_BCOUT5 always
DSP_R.DSP_1_BCIN6.DSP_0_BCOUT6 always
DSP_R.DSP_1_BCIN7.DSP_0_BCOUT7 always
DSP_R.DSP_1_BCIN8.DSP_0_BCOUT8 always
DSP_R.DSP_1_BCIN9.DSP_0_BCOUT9 always
DSP_R.DSP_1_BCIN10.DSP_0_BCOUT10 always
DSP_R.DSP_1_BCIN11.DSP_0_BCOUT11 always
DSP_R.DSP_1_BCIN12.DSP_0_BCOUT12 always
DSP_R.DSP_1_BCIN13.DSP_0_BCOUT13 always
DSP_R.DSP_1_BCIN14.DSP_0_BCOUT14 always
DSP_R.DSP_1_BCIN15.DSP_0_BCOUT15 always
DSP_R.DSP_1_BCIN16.DSP_0_BCOUT16 always
DSP_R.DSP_1_BCIN17.DSP_0_BCOUT17 always
DSP_R.DSP_1_CARRYCASCIN.DSP_0_CARRYCASCOUT always
DSP_R.DSP_LOGIC_OUTS_B12_1.DSP_0_CARRYOUT0 always
DSP_R.DSP_LOGIC_OUTS_B11_1.DSP_0_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B13_1.DSP_0_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B10_1.DSP_0_CARRYOUT3 always
DSP_R.DSP_1_MULTSIGNIN.DSP_0_MULTSIGNOUT always
DSP_R.DSP_LOGIC_OUTS_B10_2.DSP_0_OVERFLOW always
DSP_R.DSP_LOGIC_OUTS_B21_0.DSP_0_P0 always
DSP_R.DSP_LOGIC_OUTS_B21_1.DSP_0_P4 always
DSP_R.DSP_LOGIC_OUTS_B21_2.DSP_0_P8 always
DSP_R.DSP_LOGIC_OUTS_B21_3.DSP_0_P12 always
DSP_R.DSP_LOGIC_OUTS_B21_4.DSP_0_P16 always
DSP_R.DSP_LOGIC_OUTS_B23_0.DSP_0_P1 always
DSP_R.DSP_LOGIC_OUTS_B23_1.DSP_0_P5 always
DSP_R.DSP_LOGIC_OUTS_B23_2.DSP_0_P9 always
DSP_R.DSP_LOGIC_OUTS_B23_3.DSP_0_P13 always
DSP_R.DSP_LOGIC_OUTS_B23_4.DSP_0_P17 always
DSP_R.DSP_LOGIC_OUTS_B16_0.DSP_0_P2 always
DSP_R.DSP_LOGIC_OUTS_B16_1.DSP_0_P6 always
DSP_R.DSP_LOGIC_OUTS_B16_2.DSP_0_P10 always
DSP_R.DSP_LOGIC_OUTS_B16_3.DSP_0_P14 always
DSP_R.DSP_LOGIC_OUTS_B16_4.DSP_0_P18 always
DSP_R.DSP_LOGIC_OUTS_B18_0.DSP_0_P3 always
DSP_R.DSP_LOGIC_OUTS_B18_1.DSP_0_P7 always
DSP_R.DSP_LOGIC_OUTS_B18_2.DSP_0_P11 always
DSP_R.DSP_LOGIC_OUTS_B18_3.DSP_0_P15 always
DSP_R.DSP_LOGIC_OUTS_B18_4.DSP_0_P19 always
DSP_R.DSP_LOGIC_OUTS_B17_0.DSP_0_P20 always
DSP_R.DSP_LOGIC_OUTS_B17_1.DSP_0_P24 always
DSP_R.DSP_LOGIC_OUTS_B17_2.DSP_0_P28 always
DSP_R.DSP_LOGIC_OUTS_B17_3.DSP_0_P32 always
DSP_R.DSP_LOGIC_OUTS_B17_4.DSP_0_P36 always
DSP_R.DSP_LOGIC_OUTS_B19_0.DSP_0_P21 always
DSP_R.DSP_LOGIC_OUTS_B19_1.DSP_0_P25 always
DSP_R.DSP_LOGIC_OUTS_B19_2.DSP_0_P29 always
DSP_R.DSP_LOGIC_OUTS_B19_3.DSP_0_P33 always
DSP_R.DSP_LOGIC_OUTS_B19_4.DSP_0_P39 always
DSP_R.DSP_LOGIC_OUTS_B20_0.DSP_0_P22 always
DSP_R.DSP_LOGIC_OUTS_B20_1.DSP_0_P26 always
DSP_R.DSP_LOGIC_OUTS_B20_2.DSP_0_P30 always
DSP_R.DSP_LOGIC_OUTS_B20_3.DSP_0_P34 always
DSP_R.DSP_LOGIC_OUTS_B20_4.DSP_0_P38 always
DSP_R.DSP_LOGIC_OUTS_B22_0.DSP_0_P23 always
DSP_R.DSP_LOGIC_OUTS_B22_1.DSP_0_P27 always
DSP_R.DSP_LOGIC_OUTS_B22_2.DSP_0_P31 always
DSP_R.DSP_LOGIC_OUTS_B22_3.DSP_0_P35 always
DSP_R.DSP_LOGIC_OUTS_B22_4.DSP_0_P37 always
DSP_R.DSP_LOGIC_OUTS_B13_0.DSP_0_P40 always
DSP_R.DSP_LOGIC_OUTS_B13_4.DSP_0_P46 always
DSP_R.DSP_LOGIC_OUTS_B12_0.DSP_0_P41 always
DSP_R.DSP_LOGIC_OUTS_B9_0.DSP_0_P42 always
DSP_R.DSP_LOGIC_OUTS_B9_4.DSP_0_P44 always
DSP_R.DSP_LOGIC_OUTS_B8_0.DSP_0_P43 always
DSP_R.DSP_LOGIC_OUTS_B8_4.DSP_0_P47 always
DSP_R.DSP_LOGIC_OUTS_B10_4.DSP_0_P45 always
DSP_R.DSP_LOGIC_OUTS_B14_2.DSP_0_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B11_2.DSP_0_PATTERNDETECT always
DSP_R.DSP_1_PCIN0.DSP_0_PCOUT0 always
DSP_R.DSP_1_PCIN1.DSP_0_PCOUT1 always
DSP_R.DSP_1_PCIN2.DSP_0_PCOUT2 always
DSP_R.DSP_1_PCIN3.DSP_0_PCOUT3 always
DSP_R.DSP_1_PCIN4.DSP_0_PCOUT4 always
DSP_R.DSP_1_PCIN5.DSP_0_PCOUT5 always
DSP_R.DSP_1_PCIN6.DSP_0_PCOUT6 always
DSP_R.DSP_1_PCIN7.DSP_0_PCOUT7 always
DSP_R.DSP_1_PCIN8.DSP_0_PCOUT8 always
DSP_R.DSP_1_PCIN9.DSP_0_PCOUT9 always
DSP_R.DSP_1_PCIN10.DSP_0_PCOUT10 always
DSP_R.DSP_1_PCIN11.DSP_0_PCOUT11 always
DSP_R.DSP_1_PCIN12.DSP_0_PCOUT12 always
DSP_R.DSP_1_PCIN13.DSP_0_PCOUT13 always
DSP_R.DSP_1_PCIN14.DSP_0_PCOUT14 always
DSP_R.DSP_1_PCIN15.DSP_0_PCOUT15 always
DSP_R.DSP_1_PCIN16.DSP_0_PCOUT16 always
DSP_R.DSP_1_PCIN17.DSP_0_PCOUT17 always
DSP_R.DSP_1_PCIN18.DSP_0_PCOUT18 always
DSP_R.DSP_1_PCIN19.DSP_0_PCOUT19 always
DSP_R.DSP_1_PCIN20.DSP_0_PCOUT20 always
DSP_R.DSP_1_PCIN21.DSP_0_PCOUT21 always
DSP_R.DSP_1_PCIN22.DSP_0_PCOUT22 always
DSP_R.DSP_1_PCIN23.DSP_0_PCOUT23 always
DSP_R.DSP_1_PCIN24.DSP_0_PCOUT24 always
DSP_R.DSP_1_PCIN25.DSP_0_PCOUT25 always
DSP_R.DSP_1_PCIN26.DSP_0_PCOUT26 always
DSP_R.DSP_1_PCIN27.DSP_0_PCOUT27 always
DSP_R.DSP_1_PCIN28.DSP_0_PCOUT28 always
DSP_R.DSP_1_PCIN29.DSP_0_PCOUT29 always
DSP_R.DSP_1_PCIN30.DSP_0_PCOUT30 always
DSP_R.DSP_1_PCIN31.DSP_0_PCOUT31 always
DSP_R.DSP_1_PCIN32.DSP_0_PCOUT32 always
DSP_R.DSP_1_PCIN33.DSP_0_PCOUT33 always
DSP_R.DSP_1_PCIN34.DSP_0_PCOUT34 always
DSP_R.DSP_1_PCIN35.DSP_0_PCOUT35 always
DSP_R.DSP_1_PCIN36.DSP_0_PCOUT36 always
DSP_R.DSP_1_PCIN37.DSP_0_PCOUT37 always
DSP_R.DSP_1_PCIN38.DSP_0_PCOUT38 always
DSP_R.DSP_1_PCIN39.DSP_0_PCOUT39 always
DSP_R.DSP_1_PCIN40.DSP_0_PCOUT40 always
DSP_R.DSP_1_PCIN41.DSP_0_PCOUT41 always
DSP_R.DSP_1_PCIN42.DSP_0_PCOUT42 always
DSP_R.DSP_1_PCIN43.DSP_0_PCOUT43 always
DSP_R.DSP_1_PCIN44.DSP_0_PCOUT44 always
DSP_R.DSP_1_PCIN45.DSP_0_PCOUT45 always
DSP_R.DSP_1_PCIN46.DSP_0_PCOUT46 always
DSP_R.DSP_1_PCIN47.DSP_0_PCOUT47 always
DSP_R.DSP_LOGIC_OUTS_B9_2.DSP_0_UNDERFLOW always
DSP_R.DSP_ACOUT0.DSP_1_ACOUT0 always
DSP_R.DSP_ACOUT1.DSP_1_ACOUT1 always
DSP_R.DSP_ACOUT2.DSP_1_ACOUT2 always
DSP_R.DSP_ACOUT3.DSP_1_ACOUT3 always
DSP_R.DSP_ACOUT4.DSP_1_ACOUT4 always
DSP_R.DSP_ACOUT5.DSP_1_ACOUT5 always
DSP_R.DSP_ACOUT6.DSP_1_ACOUT6 always
DSP_R.DSP_ACOUT7.DSP_1_ACOUT7 always
DSP_R.DSP_ACOUT8.DSP_1_ACOUT8 always
DSP_R.DSP_ACOUT9.DSP_1_ACOUT9 always
DSP_R.DSP_ACOUT10.DSP_1_ACOUT10 always
DSP_R.DSP_ACOUT11.DSP_1_ACOUT11 always
DSP_R.DSP_ACOUT12.DSP_1_ACOUT12 always
DSP_R.DSP_ACOUT13.DSP_1_ACOUT13 always
DSP_R.DSP_ACOUT14.DSP_1_ACOUT14 always
DSP_R.DSP_ACOUT15.DSP_1_ACOUT15 always
DSP_R.DSP_ACOUT16.DSP_1_ACOUT16 always
DSP_R.DSP_ACOUT17.DSP_1_ACOUT17 always
DSP_R.DSP_ACOUT18.DSP_1_ACOUT18 always
DSP_R.DSP_ACOUT19.DSP_1_ACOUT19 always
DSP_R.DSP_ACOUT20.DSP_1_ACOUT20 always
DSP_R.DSP_ACOUT21.DSP_1_ACOUT21 always
DSP_R.DSP_ACOUT22.DSP_1_ACOUT22 always
DSP_R.DSP_ACOUT23.DSP_1_ACOUT23 always
DSP_R.DSP_ACOUT24.DSP_1_ACOUT24 always
DSP_R.DSP_ACOUT25.DSP_1_ACOUT25 always
DSP_R.DSP_ACOUT26.DSP_1_ACOUT26 always
DSP_R.DSP_ACOUT27.DSP_1_ACOUT27 always
DSP_R.DSP_ACOUT28.DSP_1_ACOUT28 always
DSP_R.DSP_ACOUT29.DSP_1_ACOUT29 always
DSP_R.DSP_BCOUT0.DSP_1_BCOUT0 always
DSP_R.DSP_BCOUT1.DSP_1_BCOUT1 always
DSP_R.DSP_BCOUT2.DSP_1_BCOUT2 always
DSP_R.DSP_BCOUT3.DSP_1_BCOUT3 always
DSP_R.DSP_BCOUT4.DSP_1_BCOUT4 always
DSP_R.DSP_BCOUT5.DSP_1_BCOUT5 always
DSP_R.DSP_BCOUT6.DSP_1_BCOUT6 always
DSP_R.DSP_BCOUT7.DSP_1_BCOUT7 always
DSP_R.DSP_BCOUT8.DSP_1_BCOUT8 always
DSP_R.DSP_BCOUT9.DSP_1_BCOUT9 always
DSP_R.DSP_BCOUT10.DSP_1_BCOUT10 always
DSP_R.DSP_BCOUT11.DSP_1_BCOUT11 always
DSP_R.DSP_BCOUT12.DSP_1_BCOUT12 always
DSP_R.DSP_BCOUT13.DSP_1_BCOUT13 always
DSP_R.DSP_BCOUT14.DSP_1_BCOUT14 always
DSP_R.DSP_BCOUT15.DSP_1_BCOUT15 always
DSP_R.DSP_BCOUT16.DSP_1_BCOUT16 always
DSP_R.DSP_BCOUT17.DSP_1_BCOUT17 always
DSP_R.DSP_CARRYCASCOUT.DSP_1_CARRYCASCOUT always
DSP_R.DSP_LOGIC_OUTS_B8_3.DSP_1_CARRYOUT0 always
DSP_R.DSP_LOGIC_OUTS_B11_3.DSP_1_CARRYOUT1 always
DSP_R.DSP_LOGIC_OUTS_B10_3.DSP_1_CARRYOUT2 always
DSP_R.DSP_LOGIC_OUTS_B15_3.DSP_1_CARRYOUT3 always
DSP_R.DSP_MULTSIGNOUT.DSP_1_MULTSIGNOUT always
DSP_R.DSP_LOGIC_OUTS_B8_2.DSP_1_OVERFLOW always
DSP_R.DSP_LOGIC_OUTS_B3_0.DSP_1_P0 always
DSP_R.DSP_LOGIC_OUTS_B3_1.DSP_1_P4 always
DSP_R.DSP_LOGIC_OUTS_B3_2.DSP_1_P8 always
DSP_R.DSP_LOGIC_OUTS_B3_3.DSP_1_P12 always
DSP_R.DSP_LOGIC_OUTS_B3_4.DSP_1_P16 always
DSP_R.DSP_LOGIC_OUTS_B1_0.DSP_1_P1 always
DSP_R.DSP_LOGIC_OUTS_B1_1.DSP_1_P5 always
DSP_R.DSP_LOGIC_OUTS_B1_2.DSP_1_P9 always
DSP_R.DSP_LOGIC_OUTS_B1_3.DSP_1_P13 always
DSP_R.DSP_LOGIC_OUTS_B1_4.DSP_1_P17 always
DSP_R.DSP_LOGIC_OUTS_B6_0.DSP_1_P2 always
DSP_R.DSP_LOGIC_OUTS_B6_1.DSP_1_P6 always
DSP_R.DSP_LOGIC_OUTS_B6_2.DSP_1_P10 always
DSP_R.DSP_LOGIC_OUTS_B6_3.DSP_1_P14 always
DSP_R.DSP_LOGIC_OUTS_B6_4.DSP_1_P18 always
DSP_R.DSP_LOGIC_OUTS_B4_0.DSP_1_P3 always
DSP_R.DSP_LOGIC_OUTS_B4_1.DSP_1_P7 always
DSP_R.DSP_LOGIC_OUTS_B4_2.DSP_1_P11 always
DSP_R.DSP_LOGIC_OUTS_B4_3.DSP_1_P15 always
DSP_R.DSP_LOGIC_OUTS_B4_4.DSP_1_P19 always
DSP_R.DSP_LOGIC_OUTS_B7_0.DSP_1_P20 always
DSP_R.DSP_LOGIC_OUTS_B7_1.DSP_1_P24 always
DSP_R.DSP_LOGIC_OUTS_B7_2.DSP_1_P28 always
DSP_R.DSP_LOGIC_OUTS_B7_3.DSP_1_P32 always
DSP_R.DSP_LOGIC_OUTS_B7_4.DSP_1_P36 always
DSP_R.DSP_LOGIC_OUTS_B5_0.DSP_1_P21 always
DSP_R.DSP_LOGIC_OUTS_B5_1.DSP_1_P25 always
DSP_R.DSP_LOGIC_OUTS_B5_2.DSP_1_P29 always
DSP_R.DSP_LOGIC_OUTS_B5_3.DSP_1_P33 always
DSP_R.DSP_LOGIC_OUTS_B5_4.DSP_1_P39 always
DSP_R.DSP_LOGIC_OUTS_B2_0.DSP_1_P22 always
DSP_R.DSP_LOGIC_OUTS_B2_1.DSP_1_P26 always
DSP_R.DSP_LOGIC_OUTS_B2_2.DSP_1_P30 always
DSP_R.DSP_LOGIC_OUTS_B2_3.DSP_1_P34 always
DSP_R.DSP_LOGIC_OUTS_B2_4.DSP_1_P38 always
DSP_R.DSP_LOGIC_OUTS_B0_0.DSP_1_P23 always
DSP_R.DSP_LOGIC_OUTS_B0_1.DSP_1_P27 always
DSP_R.DSP_LOGIC_OUTS_B0_2.DSP_1_P31 always
DSP_R.DSP_LOGIC_OUTS_B0_3.DSP_1_P35 always
DSP_R.DSP_LOGIC_OUTS_B0_4.DSP_1_P37 always
DSP_R.DSP_LOGIC_OUTS_B15_0.DSP_1_P40 always
DSP_R.DSP_LOGIC_OUTS_B15_4.DSP_1_P47 always
DSP_R.DSP_LOGIC_OUTS_B11_0.DSP_1_P41 always
DSP_R.DSP_LOGIC_OUTS_B11_4.DSP_1_P45 always
DSP_R.DSP_LOGIC_OUTS_B10_0.DSP_1_P42 always
DSP_R.DSP_LOGIC_OUTS_B14_0.DSP_1_P43 always
DSP_R.DSP_LOGIC_OUTS_B14_4.DSP_1_P46 always
DSP_R.DSP_LOGIC_OUTS_B12_4.DSP_1_P44 always
DSP_R.DSP_LOGIC_OUTS_B15_2.DSP_1_PATTERNBDETECT always
DSP_R.DSP_LOGIC_OUTS_B13_2.DSP_1_PATTERNDETECT always
DSP_R.DSP_PCOUT0.DSP_1_PCOUT0 always
DSP_R.DSP_PCOUT1.DSP_1_PCOUT1 always
DSP_R.DSP_PCOUT2.DSP_1_PCOUT2 always
DSP_R.DSP_PCOUT3.DSP_1_PCOUT3 always
DSP_R.DSP_PCOUT4.DSP_1_PCOUT4 always
DSP_R.DSP_PCOUT5.DSP_1_PCOUT5 always
DSP_R.DSP_PCOUT6.DSP_1_PCOUT6 always
DSP_R.DSP_PCOUT7.DSP_1_PCOUT7 always
DSP_R.DSP_PCOUT8.DSP_1_PCOUT8 always
DSP_R.DSP_PCOUT9.DSP_1_PCOUT9 always
DSP_R.DSP_PCOUT10.DSP_1_PCOUT10 always
DSP_R.DSP_PCOUT11.DSP_1_PCOUT11 always
DSP_R.DSP_PCOUT12.DSP_1_PCOUT12 always
DSP_R.DSP_PCOUT13.DSP_1_PCOUT13 always
DSP_R.DSP_PCOUT14.DSP_1_PCOUT14 always
DSP_R.DSP_PCOUT15.DSP_1_PCOUT15 always
DSP_R.DSP_PCOUT16.DSP_1_PCOUT16 always
DSP_R.DSP_PCOUT17.DSP_1_PCOUT17 always
DSP_R.DSP_PCOUT18.DSP_1_PCOUT18 always
DSP_R.DSP_PCOUT19.DSP_1_PCOUT19 always
DSP_R.DSP_PCOUT20.DSP_1_PCOUT20 always
DSP_R.DSP_PCOUT21.DSP_1_PCOUT21 always
DSP_R.DSP_PCOUT22.DSP_1_PCOUT22 always
DSP_R.DSP_PCOUT23.DSP_1_PCOUT23 always
DSP_R.DSP_PCOUT24.DSP_1_PCOUT24 always
DSP_R.DSP_PCOUT25.DSP_1_PCOUT25 always
DSP_R.DSP_PCOUT26.DSP_1_PCOUT26 always
DSP_R.DSP_PCOUT27.DSP_1_PCOUT27 always
DSP_R.DSP_PCOUT28.DSP_1_PCOUT28 always
DSP_R.DSP_PCOUT29.DSP_1_PCOUT29 always
DSP_R.DSP_PCOUT30.DSP_1_PCOUT30 always
DSP_R.DSP_PCOUT31.DSP_1_PCOUT31 always
DSP_R.DSP_PCOUT32.DSP_1_PCOUT32 always
DSP_R.DSP_PCOUT33.DSP_1_PCOUT33 always
DSP_R.DSP_PCOUT34.DSP_1_PCOUT34 always
DSP_R.DSP_PCOUT35.DSP_1_PCOUT35 always
DSP_R.DSP_PCOUT36.DSP_1_PCOUT36 always
DSP_R.DSP_PCOUT37.DSP_1_PCOUT37 always
DSP_R.DSP_PCOUT38.DSP_1_PCOUT38 always
DSP_R.DSP_PCOUT39.DSP_1_PCOUT39 always
DSP_R.DSP_PCOUT40.DSP_1_PCOUT40 always
DSP_R.DSP_PCOUT41.DSP_1_PCOUT41 always
DSP_R.DSP_PCOUT42.DSP_1_PCOUT42 always
DSP_R.DSP_PCOUT43.DSP_1_PCOUT43 always
DSP_R.DSP_PCOUT44.DSP_1_PCOUT44 always
DSP_R.DSP_PCOUT45.DSP_1_PCOUT45 always
DSP_R.DSP_PCOUT46.DSP_1_PCOUT46 always
DSP_R.DSP_PCOUT47.DSP_1_PCOUT47 always
DSP_R.DSP_LOGIC_OUTS_B14_3.DSP_1_UNDERFLOW always
DSP_R.DSP_0_CLK.DSP_CLK0_1 always
DSP_R.DSP_1_CLK.DSP_CLK0_3 always
DSP_R.DSP_0_RSTP.DSP_CTRL0_0 always
DSP_R.DSP_0_RSTC.DSP_CTRL0_1 always
DSP_R.DSP_0_RSTB.DSP_CTRL0_2 always
DSP_R.DSP_1_RSTC.DSP_CTRL0_3 always
DSP_R.DSP_1_RSTP.DSP_CTRL0_4 always
DSP_R.DSP_0_RSTA.DSP_CTRL1_0 always
DSP_R.DSP_0_RSTM.DSP_CTRL1_1 always
DSP_R.DSP_1_RSTA.DSP_CTRL1_2 always
DSP_R.DSP_1_RSTM.DSP_CTRL1_3 always
DSP_R.DSP_1_RSTB.DSP_CTRL1_4 always
DSP_R.DSP_1_B3.DSP_IMUX0_0 always
DSP_R.DSP_1_B15.DSP_IMUX0_3 always
DSP_R.DSP_0_CEA2.DSP_IMUX0_1 always
DSP_R.DSP_0_CECARRYIN.DSP_IMUX0_2 always
DSP_R.DSP_1_ALUMODE0.DSP_IMUX0_4 always
DSP_R.DSP_1_C21.DSP_IMUX10_0 always
DSP_R.DSP_1_C29.DSP_IMUX10_2 always
DSP_R.DSP_1_C33.DSP_IMUX10_3 always
DSP_R.DSP_1_C39.DSP_IMUX10_4 always
DSP_R.DSP_1_B5.DSP_IMUX10_1 always
DSP_R.DSP_1_A1.DSP_IMUX11_0 always
DSP_R.DSP_1_A5.DSP_IMUX11_1 always
DSP_R.DSP_1_A9.DSP_IMUX11_2 always
DSP_R.DSP_1_CECTRL.DSP_IMUX11_3 always
DSP_R.DSP_1_C46.DSP_IMUX11_4 always
DSP_R.DSP_1_C22.DSP_IMUX12_0 always
DSP_R.DSP_1_C26.DSP_IMUX12_1 always
DSP_R.DSP_1_C34.DSP_IMUX12_3 always
DSP_R.DSP_1_C38.DSP_IMUX12_4 always
DSP_R.DSP_0_OPMODE5.DSP_IMUX12_2 always
DSP_R.DSP_1_A2.DSP_IMUX13_0 always
DSP_R.DSP_1_A6.DSP_IMUX13_1 always
DSP_R.DSP_1_A10.DSP_IMUX13_2 always
DSP_R.DSP_0_ALUMODE1.DSP_IMUX13_3 always
DSP_R.DSP_1_C18.DSP_IMUX13_4 always
DSP_R.DSP_1_B0.DSP_IMUX14_0 always
DSP_R.DSP_1_B8.DSP_IMUX14_2 always
DSP_R.DSP_1_C24.DSP_IMUX14_1 always
DSP_R.DSP_0_CARRYINSEL1.DSP_IMUX14_3 always
DSP_R.DSP_1_RSTCTRL.DSP_IMUX14_4 always
DSP_R.DSP_1_A0.DSP_IMUX15_0 always
DSP_R.DSP_1_A4.DSP_IMUX15_1 always
DSP_R.DSP_1_A8.DSP_IMUX15_2 always
DSP_R.DSP_1_CARRYIN.DSP_IMUX15_3 always
DSP_R.DSP_1_RSTALLCARRYIN.DSP_IMUX15_4 always
DSP_R.DSP_0_C41.DSP_IMUX16_0 always
DSP_R.DSP_0_B7.DSP_IMUX16_1 always
DSP_R.DSP_0_B11.DSP_IMUX16_2 always
DSP_R.DSP_1_CEB2.DSP_IMUX16_3 always
DSP_R.DSP_1_OPMODE3.DSP_IMUX16_4 always
DSP_R.DSP_0_A3.DSP_IMUX17_0 always
DSP_R.DSP_0_A7.DSP_IMUX17_1 always
DSP_R.DSP_0_A11.DSP_IMUX17_2 always
DSP_R.DSP_1_CEA2.DSP_IMUX17_3 always
DSP_R.DSP_1_OPMODE4.DSP_IMUX17_4 always
DSP_R.DSP_0_C21.DSP_IMUX18_0 always
DSP_R.DSP_0_C33.DSP_IMUX18_3 always
DSP_R.DSP_0_C39.DSP_IMUX18_4 always
DSP_R.DSP_0_B5.DSP_IMUX18_1 always
DSP_R.DSP_0_B9.DSP_IMUX18_2 always
DSP_R.DSP_0_A1.DSP_IMUX19_0 always
DSP_R.DSP_0_A5.DSP_IMUX19_1 always
DSP_R.DSP_0_A9.DSP_IMUX19_2 always
DSP_R.DSP_1_CEM.DSP_IMUX19_3 always
DSP_R.DSP_0_C46.DSP_IMUX19_4 always
DSP_R.DSP_0_C3.DSP_IMUX1_0 always
DSP_R.DSP_0_C19.DSP_IMUX1_4 always
DSP_R.DSP_0_CEB2.DSP_IMUX1_1 always
DSP_R.DSP_0_CEM.DSP_IMUX1_2 always
DSP_R.DSP_1_B13.DSP_IMUX1_3 always
DSP_R.DSP_0_C22.DSP_IMUX20_0 always
DSP_R.DSP_0_C26.DSP_IMUX20_1 always
DSP_R.DSP_0_C34.DSP_IMUX20_3 always
DSP_R.DSP_0_C38.DSP_IMUX20_4 always
DSP_R.DSP_0_OPMODE4.DSP_IMUX20_2 always
DSP_R.DSP_0_A2.DSP_IMUX21_0 always
DSP_R.DSP_0_A6.DSP_IMUX21_1 always
DSP_R.DSP_0_A10.DSP_IMUX21_2 always
DSP_R.DSP_0_ALUMODE0.DSP_IMUX21_3 always
DSP_R.DSP_0_C18.DSP_IMUX21_4 always
DSP_R.DSP_0_B0.DSP_IMUX22_0 always
DSP_R.DSP_0_B8.DSP_IMUX22_2 always
DSP_R.DSP_0_C24.DSP_IMUX22_1 always
DSP_R.DSP_1_C32.DSP_IMUX22_3 always
DSP_R.DSP_1_RSTALUMODE.DSP_IMUX22_4 always
DSP_R.DSP_0_A0.DSP_IMUX23_0 always
DSP_R.DSP_0_A4.DSP_IMUX23_1 always
DSP_R.DSP_0_A8.DSP_IMUX23_2 always
DSP_R.DSP_0_CARRYIN.DSP_IMUX23_3 always
DSP_R.DSP_1_RSTINMODE.DSP_IMUX23_4 always
DSP_R.DSP_1_C23.DSP_IMUX24_0 always
DSP_R.DSP_1_C27.DSP_IMUX24_1 always
DSP_R.DSP_1_C31.DSP_IMUX24_2 always
DSP_R.DSP_1_C35.DSP_IMUX24_3 always
DSP_R.DSP_1_C37.DSP_IMUX24_4 always
DSP_R.DSP_1_C43.DSP_IMUX25_0 always
DSP_R.DSP_1_C7.DSP_IMUX25_1 always
DSP_R.DSP_1_C11.DSP_IMUX25_2 always
DSP_R.DSP_1_C15.DSP_IMUX25_3 always
DSP_R.DSP_1_C47.DSP_IMUX25_4 always
DSP_R.DSP_1_B1.DSP_IMUX26_0 always
DSP_R.DSP_1_C25.DSP_IMUX26_1 always
DSP_R.DSP_1_C44.DSP_IMUX26_4 always
DSP_R.DSP_1_CEP.DSP_IMUX26_2 always
DSP_R.DSP_1_CECARRYIN.DSP_IMUX26_3 always
DSP_R.DSP_1_C40.DSP_IMUX27_0 always
DSP_R.DSP_1_C5.DSP_IMUX27_1 always
DSP_R.DSP_1_C13.DSP_IMUX27_3 always
DSP_R.DSP_1_C17.DSP_IMUX27_4 always
DSP_R.DSP_0_OPMODE2.DSP_IMUX27_2 always
DSP_R.DSP_1_B2.DSP_IMUX28_0 always
DSP_R.DSP_1_B6.DSP_IMUX28_1 always
DSP_R.DSP_1_C30.DSP_IMUX28_2 always
DSP_R.DSP_1_OPMODE0.DSP_IMUX28_3 always
DSP_R.DSP_1_CARRYINSEL1.DSP_IMUX28_4 always
DSP_R.DSP_1_C2.DSP_IMUX29_0 always
DSP_R.DSP_1_C6.DSP_IMUX29_1 always
DSP_R.DSP_1_C10.DSP_IMUX29_2 always
DSP_R.DSP_1_C14.DSP_IMUX29_3 always
DSP_R.DSP_1_C45.DSP_IMUX29_4 always
DSP_R.DSP_1_C42.DSP_IMUX2_0 always
DSP_R.DSP_0_RSTALLCARRYIN.DSP_IMUX2_1 always
DSP_R.DSP_0_C29.DSP_IMUX2_2 always
DSP_R.DSP_0_B15.DSP_IMUX2_3 always
DSP_R.DSP_1_B17.DSP_IMUX2_4 always
DSP_R.DSP_1_C20.DSP_IMUX30_0 always
DSP_R.DSP_1_C36.DSP_IMUX30_4 always
DSP_R.DSP_1_B4.DSP_IMUX30_1 always
DSP_R.DSP_0_OPMODE1.DSP_IMUX30_2 always
DSP_R.DSP_0_CARRYINSEL0.DSP_IMUX30_3 always
DSP_R.DSP_1_C0.DSP_IMUX31_0 always
DSP_R.DSP_1_C4.DSP_IMUX31_1 always
DSP_R.DSP_1_C8.DSP_IMUX31_2 always
DSP_R.DSP_1_C12.DSP_IMUX31_3 always
DSP_R.DSP_1_C16.DSP_IMUX31_4 always
DSP_R.DSP_0_C23.DSP_IMUX32_0 always
DSP_R.DSP_0_C27.DSP_IMUX32_1 always
DSP_R.DSP_0_C31.DSP_IMUX32_2 always
DSP_R.DSP_0_C35.DSP_IMUX32_3 always
DSP_R.DSP_0_C37.DSP_IMUX32_4 always
DSP_R.DSP_0_C43.DSP_IMUX33_0 always
DSP_R.DSP_0_C7.DSP_IMUX33_1 always
DSP_R.DSP_0_C11.DSP_IMUX33_2 always
DSP_R.DSP_0_C15.DSP_IMUX33_3 always
DSP_R.DSP_0_C47.DSP_IMUX33_4 always
DSP_R.DSP_0_B1.DSP_IMUX34_0 always
DSP_R.DSP_0_C25.DSP_IMUX34_1 always
DSP_R.DSP_0_C44.DSP_IMUX34_4 always
DSP_R.DSP_0_CEP.DSP_IMUX34_2 always
DSP_R.DSP_1_CEC.DSP_IMUX34_3 always
DSP_R.DSP_0_C40.DSP_IMUX35_0 always
DSP_R.DSP_0_C5.DSP_IMUX35_1 always
DSP_R.DSP_0_C13.DSP_IMUX35_3 always
DSP_R.DSP_0_C17.DSP_IMUX35_4 always
DSP_R.DSP_0_OPMODE0.DSP_IMUX35_2 always
DSP_R.DSP_0_B2.DSP_IMUX36_0 always
DSP_R.DSP_0_B6.DSP_IMUX36_1 always
DSP_R.DSP_0_B10.DSP_IMUX36_2 always
DSP_R.DSP_1_OPMODE2.DSP_IMUX36_3 always
DSP_R.DSP_1_CARRYINSEL0.DSP_IMUX36_4 always
DSP_R.DSP_0_C2.DSP_IMUX37_0 always
DSP_R.DSP_0_C6.DSP_IMUX37_1 always
DSP_R.DSP_0_C10.DSP_IMUX37_2 always
DSP_R.DSP_0_C14.DSP_IMUX37_3 always
DSP_R.DSP_0_C45.DSP_IMUX37_4 always
DSP_R.DSP_0_C20.DSP_IMUX38_0 always
DSP_R.DSP_0_C32.DSP_IMUX38_3 always
DSP_R.DSP_0_C36.DSP_IMUX38_4 always
DSP_R.DSP_0_B4.DSP_IMUX38_1 always
DSP_R.DSP_0_OPMODE3.DSP_IMUX38_2 always
DSP_R.DSP_0_C0.DSP_IMUX39_0 always
DSP_R.DSP_0_C4.DSP_IMUX39_1 always
DSP_R.DSP_0_C8.DSP_IMUX39_2 always
DSP_R.DSP_0_C12.DSP_IMUX39_3 always
DSP_R.DSP_0_C16.DSP_IMUX39_4 always
DSP_R.DSP_0_C1.DSP_IMUX3_0 always
DSP_R.DSP_0_C9.DSP_IMUX3_2 always
DSP_R.DSP_0_RSTALUMODE.DSP_IMUX3_1 always
DSP_R.DSP_0_B13.DSP_IMUX3_3 always
DSP_R.DSP_0_B17.DSP_IMUX3_4 always
DSP_R.DSP_0_B3.DSP_IMUX40_0 always
DSP_R.DSP_0_CEA1.DSP_IMUX40_1 always
DSP_R.DSP_0_CEC.DSP_IMUX40_2 always
DSP_R.DSP_1_B14.DSP_IMUX40_3 always
DSP_R.DSP_1_ALUMODE1.DSP_IMUX40_4 always
DSP_R.DSP_1_C3.DSP_IMUX41_0 always
DSP_R.DSP_1_C19.DSP_IMUX41_4 always
DSP_R.DSP_0_CEB1.DSP_IMUX41_1 always
DSP_R.DSP_0_CECTRL.DSP_IMUX41_2 always
DSP_R.DSP_1_B12.DSP_IMUX41_3 always
DSP_R.DSP_0_C42.DSP_IMUX42_0 always
DSP_R.DSP_0_RSTINMODE.DSP_IMUX42_1 always
DSP_R.DSP_1_B9.DSP_IMUX42_2 always
DSP_R.DSP_1_B16.DSP_IMUX42_4 always
DSP_R.DSP_0_B14.DSP_IMUX42_3 always
DSP_R.DSP_1_C1.DSP_IMUX43_0 always
DSP_R.DSP_1_C9.DSP_IMUX43_2 always
DSP_R.DSP_0_RSTCTRL.DSP_IMUX43_1 always
DSP_R.DSP_0_B12.DSP_IMUX43_3 always
DSP_R.DSP_0_B16.DSP_IMUX43_4 always
DSP_R.DSP_1_A22.DSP_IMUX44_0 always
DSP_R.DSP_1_A26.DSP_IMUX44_1 always
DSP_R.DSP_1_A14.DSP_IMUX44_3 always
DSP_R.DSP_1_A18.DSP_IMUX44_4 always
DSP_R.DSP_1_B10.DSP_IMUX44_2 always
DSP_R.DSP_1_A20.DSP_IMUX45_0 always
DSP_R.DSP_1_A24.DSP_IMUX45_1 always
DSP_R.DSP_1_A28.DSP_IMUX45_2 always
DSP_R.DSP_1_A12.DSP_IMUX45_3 always
DSP_R.DSP_1_A16.DSP_IMUX45_4 always
DSP_R.DSP_0_A22.DSP_IMUX46_0 always
DSP_R.DSP_0_A26.DSP_IMUX46_1 always
DSP_R.DSP_0_A14.DSP_IMUX46_3 always
DSP_R.DSP_0_A18.DSP_IMUX46_4 always
DSP_R.DSP_1_C28.DSP_IMUX46_2 always
DSP_R.DSP_0_A20.DSP_IMUX47_0 always
DSP_R.DSP_0_A24.DSP_IMUX47_1 always
DSP_R.DSP_0_A28.DSP_IMUX47_2 always
DSP_R.DSP_0_A12.DSP_IMUX47_3 always
DSP_R.DSP_0_A16.DSP_IMUX47_4 always
DSP_R.DSP_1_A23.DSP_IMUX4_0 always
DSP_R.DSP_1_A27.DSP_IMUX4_1 always
DSP_R.DSP_1_A15.DSP_IMUX4_3 always
DSP_R.DSP_1_A19.DSP_IMUX4_4 always
DSP_R.DSP_0_C30.DSP_IMUX4_2 always
DSP_R.DSP_1_A21.DSP_IMUX5_0 always
DSP_R.DSP_1_A25.DSP_IMUX5_1 always
DSP_R.DSP_1_A29.DSP_IMUX5_2 always
DSP_R.DSP_1_A13.DSP_IMUX5_3 always
DSP_R.DSP_1_A17.DSP_IMUX5_4 always
DSP_R.DSP_0_A23.DSP_IMUX6_0 always
DSP_R.DSP_0_A27.DSP_IMUX6_1 always
DSP_R.DSP_0_A15.DSP_IMUX6_3 always
DSP_R.DSP_0_A19.DSP_IMUX6_4 always
DSP_R.DSP_0_C28.DSP_IMUX6_2 always
DSP_R.DSP_0_A21.DSP_IMUX7_0 always
DSP_R.DSP_0_A25.DSP_IMUX7_1 always
DSP_R.DSP_0_A29.DSP_IMUX7_2 always
DSP_R.DSP_0_A13.DSP_IMUX7_3 always
DSP_R.DSP_0_A17.DSP_IMUX7_4 always
DSP_R.DSP_1_C41.DSP_IMUX8_0 always
DSP_R.DSP_1_B7.DSP_IMUX8_1 always
DSP_R.DSP_1_B11.DSP_IMUX8_2 always
DSP_R.DSP_1_CEB1.DSP_IMUX8_3 always
DSP_R.DSP_1_OPMODE1.DSP_IMUX8_4 always
DSP_R.DSP_1_A3.DSP_IMUX9_0 always
DSP_R.DSP_1_A7.DSP_IMUX9_1 always
DSP_R.DSP_1_A11.DSP_IMUX9_2 always
DSP_R.DSP_1_CEA1.DSP_IMUX9_3 always
DSP_R.DSP_1_OPMODE5.DSP_IMUX9_4 always

0
virtex7/ppips_dsp_r.origin_info.db Normal file
View File

626
virtex7/ppips_gtx_channel_0.db Normal file
View File

@ -0,0 +1,626 @@
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_1.GTXE2_CHANNEL_CPLLFBCLKLOST always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_1.GTXE2_CHANNEL_CPLLLOCK always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_1.GTXE2_CHANNEL_CPLLREFCLKLOST always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_10.GTXE2_CHANNEL_DMONITOROUT0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_9.GTXE2_CHANNEL_DMONITOROUT1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_8.GTXE2_CHANNEL_DMONITOROUT2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_7.GTXE2_CHANNEL_DMONITOROUT3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_6.GTXE2_CHANNEL_DMONITOROUT4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_5.GTXE2_CHANNEL_DMONITOROUT5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_4.GTXE2_CHANNEL_DMONITOROUT6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_3.GTXE2_CHANNEL_DMONITOROUT7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_0.GTXE2_CHANNEL_DRPDO0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_1.GTXE2_CHANNEL_DRPDO8 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_0.GTXE2_CHANNEL_DRPDO1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_1.GTXE2_CHANNEL_DRPDO9 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_0.GTXE2_CHANNEL_DRPDO2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_1.GTXE2_CHANNEL_DRPDO10 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_0.GTXE2_CHANNEL_DRPDO3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_1.GTXE2_CHANNEL_DRPDO11 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_0.GTXE2_CHANNEL_DRPDO4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_1.GTXE2_CHANNEL_DRPDO12 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_0.GTXE2_CHANNEL_DRPDO5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_1.GTXE2_CHANNEL_DRPDO13 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_0.GTXE2_CHANNEL_DRPDO6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_1.GTXE2_CHANNEL_DRPDO14 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_0.GTXE2_CHANNEL_DRPDO7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_1.GTXE2_CHANNEL_DRPDO15 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_0.GTXE2_CHANNEL_DRPRDY always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_10.GTXE2_CHANNEL_EYESCANDATAERROR always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_2.GTXE2_CHANNEL_GTREFCLKMONITOR always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLK_0.GTXE2_CHANNEL_GTRXOUTCLK_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLK_0.GTXE2_CHANNEL_GTTXOUTCLK_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTNORTHREFCLK0.GTXE2_CHANNEL_NORTHREFCLK0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTNORTHREFCLK1.GTXE2_CHANNEL_NORTHREFCLK1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_0.GTXE2_CHANNEL_PCSRSVDOUT0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_1.GTXE2_CHANNEL_PCSRSVDOUT1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_2.GTXE2_CHANNEL_PCSRSVDOUT2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_3.GTXE2_CHANNEL_PCSRSVDOUT3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_4.GTXE2_CHANNEL_PCSRSVDOUT4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_5.GTXE2_CHANNEL_PCSRSVDOUT5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_6.GTXE2_CHANNEL_PCSRSVDOUT6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_7.GTXE2_CHANNEL_PCSRSVDOUT7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_8.GTXE2_CHANNEL_PCSRSVDOUT8 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_9.GTXE2_CHANNEL_PCSRSVDOUT9 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B13_10.GTXE2_CHANNEL_PCSRSVDOUT10 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_0.GTXE2_CHANNEL_PCSRSVDOUT11 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_1.GTXE2_CHANNEL_PCSRSVDOUT12 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B9_2.GTXE2_CHANNEL_PCSRSVDOUT13 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_0.GTXE2_CHANNEL_PCSRSVDOUT14 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_1.GTXE2_CHANNEL_PCSRSVDOUT15 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B10_9.GTXE2_CHANNEL_PHYSTATUS always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTQPLLCLK.GTXE2_CHANNEL_QPLLCLK always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTQPLLREFCLK.GTXE2_CHANNEL_QPLLREFCLK always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTREFCLK0.GTXE2_CHANNEL_REFCLK0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTREFCLK1.GTXE2_CHANNEL_REFCLK1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_10.GTXE2_CHANNEL_RXBUFSTATUS0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B19_10.GTXE2_CHANNEL_RXBUFSTATUS1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_10.GTXE2_CHANNEL_RXBUFSTATUS2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_10.GTXE2_CHANNEL_RXBYTEISALIGNED always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B10_10.GTXE2_CHANNEL_RXBYTEREALIGN always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_5.GTXE2_CHANNEL_RXCDRLOCK always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B10_8.GTXE2_CHANNEL_RXCHANBONDSEQ always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_9.GTXE2_CHANNEL_RXCHANISALIGNED always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_9.GTXE2_CHANNEL_RXCHANREALIGN always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_9.GTXE2_CHANNEL_RXCHARISCOMMA0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_7.GTXE2_CHANNEL_RXCHARISCOMMA1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_5.GTXE2_CHANNEL_RXCHARISCOMMA2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_3.GTXE2_CHANNEL_RXCHARISCOMMA3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_10.GTXE2_CHANNEL_RXCHARISCOMMA4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_8.GTXE2_CHANNEL_RXCHARISCOMMA5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_6.GTXE2_CHANNEL_RXCHARISCOMMA6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_4.GTXE2_CHANNEL_RXCHARISCOMMA7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_10.GTXE2_CHANNEL_RXCHARISK0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_8.GTXE2_CHANNEL_RXCHARISK1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_6.GTXE2_CHANNEL_RXCHARISK2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_4.GTXE2_CHANNEL_RXCHARISK3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_9.GTXE2_CHANNEL_RXCHARISK4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_7.GTXE2_CHANNEL_RXCHARISK5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_5.GTXE2_CHANNEL_RXCHARISK6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B12_3.GTXE2_CHANNEL_RXCHARISK7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_10.GTXE2_CHANNEL_RXCHBONDO0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_9.GTXE2_CHANNEL_RXCHBONDO1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_8.GTXE2_CHANNEL_RXCHBONDO2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_7.GTXE2_CHANNEL_RXCHBONDO3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_6.GTXE2_CHANNEL_RXCHBONDO4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_5.GTXE2_CHANNEL_RXCLKCORCNT0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_5.GTXE2_CHANNEL_RXCLKCORCNT1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_7.GTXE2_CHANNEL_RXCOMINITDET always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B19_7.GTXE2_CHANNEL_RXCOMMADET always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_7.GTXE2_CHANNEL_RXCOMSASDET always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B19_9.GTXE2_CHANNEL_RXCOMWAKEDET always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_10.GTXE2_CHANNEL_RXDATA0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_8.GTXE2_CHANNEL_RXDATA8 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_6.GTXE2_CHANNEL_RXDATA16 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_4.GTXE2_CHANNEL_RXDATA24 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_9.GTXE2_CHANNEL_RXDATA36 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_7.GTXE2_CHANNEL_RXDATA44 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_5.GTXE2_CHANNEL_RXDATA52 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_3.GTXE2_CHANNEL_RXDATA60 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_10.GTXE2_CHANNEL_RXDATA1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_8.GTXE2_CHANNEL_RXDATA9 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_6.GTXE2_CHANNEL_RXDATA17 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_4.GTXE2_CHANNEL_RXDATA25 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_9.GTXE2_CHANNEL_RXDATA37 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_7.GTXE2_CHANNEL_RXDATA45 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_5.GTXE2_CHANNEL_RXDATA53 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_3.GTXE2_CHANNEL_RXDATA61 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_10.GTXE2_CHANNEL_RXDATA2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_8.GTXE2_CHANNEL_RXDATA10 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_6.GTXE2_CHANNEL_RXDATA18 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_4.GTXE2_CHANNEL_RXDATA26 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_9.GTXE2_CHANNEL_RXDATA38 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_7.GTXE2_CHANNEL_RXDATA46 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_5.GTXE2_CHANNEL_RXDATA54 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_3.GTXE2_CHANNEL_RXDATA62 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_10.GTXE2_CHANNEL_RXDATA3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_8.GTXE2_CHANNEL_RXDATA11 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_6.GTXE2_CHANNEL_RXDATA19 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_4.GTXE2_CHANNEL_RXDATA27 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_9.GTXE2_CHANNEL_RXDATA39 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_7.GTXE2_CHANNEL_RXDATA47 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_5.GTXE2_CHANNEL_RXDATA55 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_3.GTXE2_CHANNEL_RXDATA63 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_9.GTXE2_CHANNEL_RXDATA4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_7.GTXE2_CHANNEL_RXDATA12 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_5.GTXE2_CHANNEL_RXDATA20 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_3.GTXE2_CHANNEL_RXDATA28 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_10.GTXE2_CHANNEL_RXDATA32 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_8.GTXE2_CHANNEL_RXDATA40 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_6.GTXE2_CHANNEL_RXDATA48 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_4.GTXE2_CHANNEL_RXDATA56 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_9.GTXE2_CHANNEL_RXDATA5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_7.GTXE2_CHANNEL_RXDATA13 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_5.GTXE2_CHANNEL_RXDATA21 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_3.GTXE2_CHANNEL_RXDATA29 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_10.GTXE2_CHANNEL_RXDATA33 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_8.GTXE2_CHANNEL_RXDATA41 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_6.GTXE2_CHANNEL_RXDATA49 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_4.GTXE2_CHANNEL_RXDATA57 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_9.GTXE2_CHANNEL_RXDATA6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_7.GTXE2_CHANNEL_RXDATA14 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_5.GTXE2_CHANNEL_RXDATA22 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_3.GTXE2_CHANNEL_RXDATA30 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_10.GTXE2_CHANNEL_RXDATA34 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_8.GTXE2_CHANNEL_RXDATA42 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_6.GTXE2_CHANNEL_RXDATA50 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_4.GTXE2_CHANNEL_RXDATA58 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_9.GTXE2_CHANNEL_RXDATA7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_7.GTXE2_CHANNEL_RXDATA15 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_5.GTXE2_CHANNEL_RXDATA23 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_3.GTXE2_CHANNEL_RXDATA31 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_10.GTXE2_CHANNEL_RXDATA35 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_8.GTXE2_CHANNEL_RXDATA43 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_6.GTXE2_CHANNEL_RXDATA51 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_4.GTXE2_CHANNEL_RXDATA59 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B19_5.GTXE2_CHANNEL_RXDATAVALID always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_10.GTXE2_CHANNEL_RXDISPERR0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_8.GTXE2_CHANNEL_RXDISPERR1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_6.GTXE2_CHANNEL_RXDISPERR2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_4.GTXE2_CHANNEL_RXDISPERR3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_9.GTXE2_CHANNEL_RXDISPERR4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_7.GTXE2_CHANNEL_RXDISPERR5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_5.GTXE2_CHANNEL_RXDISPERR6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_3.GTXE2_CHANNEL_RXDISPERR7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B22_1.GTXE2_CHANNEL_RXDLYSRESETDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B19_8.GTXE2_CHANNEL_RXELECIDLE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B19_6.GTXE2_CHANNEL_RXHEADER0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_6.GTXE2_CHANNEL_RXHEADER1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_6.GTXE2_CHANNEL_RXHEADER2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_7.GTXE2_CHANNEL_RXHEADERVALID always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_10.GTXE2_CHANNEL_RXMONITOROUT0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_9.GTXE2_CHANNEL_RXMONITOROUT1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_8.GTXE2_CHANNEL_RXMONITOROUT2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_7.GTXE2_CHANNEL_RXMONITOROUT3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_6.GTXE2_CHANNEL_RXMONITOROUT4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_5.GTXE2_CHANNEL_RXMONITOROUT5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_4.GTXE2_CHANNEL_RXMONITOROUT6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_10.GTXE2_CHANNEL_RXNOTINTABLE0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_8.GTXE2_CHANNEL_RXNOTINTABLE1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_6.GTXE2_CHANNEL_RXNOTINTABLE2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_4.GTXE2_CHANNEL_RXNOTINTABLE3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_9.GTXE2_CHANNEL_RXNOTINTABLE4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_7.GTXE2_CHANNEL_RXNOTINTABLE5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_5.GTXE2_CHANNEL_RXNOTINTABLE6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B14_3.GTXE2_CHANNEL_RXNOTINTABLE7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXN.GTXE2_CHANNEL_RXN_PAD always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_9.GTXE2_CHANNEL_RXOUTCLKFABRIC always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B21_9.GTXE2_CHANNEL_RXOUTCLKPCS always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_4.GTXE2_CHANNEL_RXPHALIGNDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B5_2.GTXE2_CHANNEL_RXPHMONITOR0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B1_2.GTXE2_CHANNEL_RXPHMONITOR1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B7_2.GTXE2_CHANNEL_RXPHMONITOR2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B3_2.GTXE2_CHANNEL_RXPHMONITOR3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B21_3.GTXE2_CHANNEL_RXPHMONITOR4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B0_2.GTXE2_CHANNEL_RXPHSLIPMONITOR0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B4_2.GTXE2_CHANNEL_RXPHSLIPMONITOR1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B2_2.GTXE2_CHANNEL_RXPHSLIPMONITOR2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B6_2.GTXE2_CHANNEL_RXPHSLIPMONITOR3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_3.GTXE2_CHANNEL_RXPHSLIPMONITOR4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_6.GTXE2_CHANNEL_RXPRBSERR always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXP.GTXE2_CHANNEL_RXP_PAD always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_1.GTXE2_CHANNEL_RXQPISENN always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B15_1.GTXE2_CHANNEL_RXQPISENP always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_5.GTXE2_CHANNEL_RXRATEDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_8.GTXE2_CHANNEL_RXRESETDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_8.GTXE2_CHANNEL_RXSTARTOFSEQ always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B21_8.GTXE2_CHANNEL_RXSTATUS0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_8.GTXE2_CHANNEL_RXSTATUS1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_8.GTXE2_CHANNEL_RXSTATUS2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_9.GTXE2_CHANNEL_RXVALID always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_0.GTXE2_CHANNEL_TSTOUT0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_1.GTXE2_CHANNEL_TSTOUT1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_2.GTXE2_CHANNEL_TSTOUT2 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_3.GTXE2_CHANNEL_TSTOUT3 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_4.GTXE2_CHANNEL_TSTOUT4 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_5.GTXE2_CHANNEL_TSTOUT5 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_6.GTXE2_CHANNEL_TSTOUT6 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_7.GTXE2_CHANNEL_TSTOUT7 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_8.GTXE2_CHANNEL_TSTOUT8 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B11_9.GTXE2_CHANNEL_TSTOUT9 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_2.GTXE2_CHANNEL_TXBUFSTATUS0 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B21_2.GTXE2_CHANNEL_TXBUFSTATUS1 always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_5.GTXE2_CHANNEL_TXCOMFINISH always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_3.GTXE2_CHANNEL_TXDLYSRESETDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_4.GTXE2_CHANNEL_TXGEARBOXREADY always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXN_PAD.GTXE2_CHANNEL_TXN always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B23_3.GTXE2_CHANNEL_TXOUTCLKFABRIC always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_4.GTXE2_CHANNEL_TXOUTCLKPCS always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXP_PAD.GTXE2_CHANNEL_TXP always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B18_3.GTXE2_CHANNEL_TXPHALIGNDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B17_0.GTXE2_CHANNEL_TXPHINITDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_3.GTXE2_CHANNEL_TXQPISENN always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B8_3.GTXE2_CHANNEL_TXQPISENP always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B20_4.GTXE2_CHANNEL_TXRATEDONE always
GTX_CHANNEL_0.GTXE2_LOGIC_OUTS_B16_4.GTXE2_CHANNEL_TXRESETDONE always
GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLLOCKDETCLK.GTXE2_CLK0_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXUSRCLK.GTXE2_CLK0_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXUSRCLK2.GTXE2_CLK0_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXUSRCLK.GTXE2_CLK0_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXUSRCLK2.GTXE2_CLK0_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPCLK.GTXE2_CLK1_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHDLYTSTCLK.GTXE2_CLK1_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CLKRSVD0.GTXE2_CLK1_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CLKRSVD1.GTXE2_CLK1_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CLKRSVD2.GTXE2_CLK1_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CLKRSVD3.GTXE2_CLK1_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTGREFCLK.GTXE2_CLK1_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLRESET.GTXE2_CTRL0_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTTXRESET.GTXE2_CTRL0_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDLYSRESET.GTXE2_CTRL0_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDRFREQRESET.GTXE2_CTRL0_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRXRESET.GTXE2_CTRL0_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFELPMRESET.GTXE2_CTRL0_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRESETSEL.GTXE2_CTRL0_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHDLYRESET.GTXE2_CTRL1_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPMARESET.GTXE2_CTRL1_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CFGRESET.GTXE2_CTRL1_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFRESET.GTXE2_CTRL1_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPMARESET.GTXE2_CTRL1_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDRRESETRSV.GTXE2_CTRL1_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDRRESET.GTXE2_CTRL1_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXOOBRESET.GTXE2_CTRL1_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BEN.GTXE2_IMUX0_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMAINCURSOR3.GTXE2_IMUX0_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSEQUENCE3.GTXE2_IMUX0_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN24.GTXE2_IMUX0_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN23.GTXE2_IMUX0_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN4.GTXE2_IMUX0_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN3.GTXE2_IMUX0_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXELECIDLEMODE0.GTXE2_IMUX0_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL7.GTXE2_IMUX10_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL6.GTXE2_IMUX10_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL5.GTXE2_IMUX10_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL4.GTXE2_IMUX10_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPDELECIDLEMODE.GTXE2_IMUX10_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXUSERRDY.GTXE2_IMUX10_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFDIFFCTRL2.GTXE2_IMUX10_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXQPIEN.GTXE2_IMUX10_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLREFCLKSEL2.GTXE2_IMUX11_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYHOLD.GTXE2_IMUX11_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXRATE2.GTXE2_IMUX11_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEVSEN.GTXE2_IMUX11_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXLPMLFHOLD.GTXE2_IMUX11_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCOMWAKE.GTXE2_IMUX12_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXHEADER1.GTXE2_IMUX12_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHOVRDEN.GTXE2_IMUX12_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYOVRDEN.GTXE2_IMUX12_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFDIFFCTRL0.GTXE2_IMUX12_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXSLIDE.GTXE2_IMUX12_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RX8B10BEN.GTXE2_IMUX12_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP3OVRDEN.GTXE2_IMUX12_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPISTRONGPDOWN.GTXE2_IMUX13_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXHEADER0.GTXE2_IMUX13_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFDIFFCTRL1.GTXE2_IMUX13_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXOSOVRDEN.GTXE2_IMUX13_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP5OVRDEN.GTXE2_IMUX13_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPRBSCNTRESET.GTXE2_IMUX13_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLREFCLKSEL1.GTXE2_IMUX14_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYEN.GTXE2_IMUX14_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXRATE1.GTXE2_IMUX14_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPCSRESET.GTXE2_IMUX14_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDROVRDEN.GTXE2_IMUX14_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHALIGN.GTXE2_IMUX14_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHOVRDEN.GTXE2_IMUX14_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS3.GTXE2_IMUX15_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS2.GTXE2_IMUX15_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS1.GTXE2_IMUX15_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS0.GTXE2_IMUX15_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLREFCLKSEL0.GTXE2_IMUX15_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRBSFORCEERR.GTXE2_IMUX15_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXRATE0.GTXE2_IMUX15_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA28.GTXE2_IMUX16_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA56.GTXE2_IMUX16_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA20.GTXE2_IMUX16_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA48.GTXE2_IMUX16_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA12.GTXE2_IMUX16_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA40.GTXE2_IMUX16_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA4.GTXE2_IMUX16_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA35.GTXE2_IMUX16_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFECM1EN.GTXE2_IMUX16_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA29.GTXE2_IMUX17_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA57.GTXE2_IMUX17_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA21.GTXE2_IMUX17_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA49.GTXE2_IMUX17_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA13.GTXE2_IMUX17_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA41.GTXE2_IMUX17_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA5.GTXE2_IMUX17_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA34.GTXE2_IMUX17_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDEN.GTXE2_IMUX17_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA60.GTXE2_IMUX18_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA24.GTXE2_IMUX18_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA52.GTXE2_IMUX18_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA16.GTXE2_IMUX18_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA44.GTXE2_IMUX18_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA8.GTXE2_IMUX18_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA36.GTXE2_IMUX18_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA0.GTXE2_IMUX18_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDI0.GTXE2_IMUX18_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDLEVEL0.GTXE2_IMUX18_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA61.GTXE2_IMUX19_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA25.GTXE2_IMUX19_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA53.GTXE2_IMUX19_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA17.GTXE2_IMUX19_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA45.GTXE2_IMUX19_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA9.GTXE2_IMUX19_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA37.GTXE2_IMUX19_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA1.GTXE2_IMUX19_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEVPHOLD.GTXE2_IMUX19_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDI1.GTXE2_IMUX19_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDLEVEL1.GTXE2_IMUX19_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITORSEL1.GTXE2_IMUX1_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMAINCURSOR2.GTXE2_IMUX1_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMAINCURSOR6.GTXE2_IMUX1_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSEQUENCE2.GTXE2_IMUX1_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSEQUENCE6.GTXE2_IMUX1_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN22.GTXE2_IMUX1_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN2.GTXE2_IMUX1_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKSEL2.GTXE2_IMUX1_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXELECIDLEMODE1.GTXE2_IMUX1_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA30.GTXE2_IMUX20_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA58.GTXE2_IMUX20_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA22.GTXE2_IMUX20_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA50.GTXE2_IMUX20_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA14.GTXE2_IMUX20_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA42.GTXE2_IMUX20_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA6.GTXE2_IMUX20_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA33.GTXE2_IMUX20_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA31.GTXE2_IMUX21_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA59.GTXE2_IMUX21_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA23.GTXE2_IMUX21_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA51.GTXE2_IMUX21_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA15.GTXE2_IMUX21_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA43.GTXE2_IMUX21_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA7.GTXE2_IMUX21_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA32.GTXE2_IMUX21_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEXYDOVRDEN.GTXE2_IMUX21_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP4OVRDEN.GTXE2_IMUX21_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEAGCOVRDEN.GTXE2_IMUX21_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA62.GTXE2_IMUX22_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA26.GTXE2_IMUX22_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA54.GTXE2_IMUX22_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA18.GTXE2_IMUX22_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA46.GTXE2_IMUX22_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA10.GTXE2_IMUX22_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA38.GTXE2_IMUX22_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA2.GTXE2_IMUX22_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPRBSSEL0.GTXE2_IMUX22_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDI2.GTXE2_IMUX22_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDLEVEL2.GTXE2_IMUX22_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA63.GTXE2_IMUX23_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA27.GTXE2_IMUX23_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA55.GTXE2_IMUX23_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA19.GTXE2_IMUX23_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA47.GTXE2_IMUX23_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA11.GTXE2_IMUX23_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA39.GTXE2_IMUX23_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDATA3.GTXE2_IMUX23_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPRBSSEL2.GTXE2_IMUX23_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDI3.GTXE2_IMUX23_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDI4.GTXE2_IMUX23_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN10.GTXE2_IMUX24_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN11.GTXE2_IMUX24_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN12.GTXE2_IMUX24_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN13.GTXE2_IMUX24_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN14.GTXE2_IMUX24_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN15.GTXE2_IMUX24_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN16.GTXE2_IMUX24_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN17.GTXE2_IMUX24_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN18.GTXE2_IMUX24_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN19.GTXE2_IMUX24_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHALIGN.GTXE2_IMUX25_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN0.GTXE2_IMUX25_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN1.GTXE2_IMUX25_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN2.GTXE2_IMUX25_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN3.GTXE2_IMUX25_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN4.GTXE2_IMUX25_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN5.GTXE2_IMUX25_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN6.GTXE2_IMUX25_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN7.GTXE2_IMUX25_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD8.GTXE2_IMUX26_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD9.GTXE2_IMUX26_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD10.GTXE2_IMUX26_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD11.GTXE2_IMUX26_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD12.GTXE2_IMUX26_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD13.GTXE2_IMUX26_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD14.GTXE2_IMUX26_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD15.GTXE2_IMUX26_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHINIT.GTXE2_IMUX27_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPOLARITY.GTXE2_IMUX27_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEVPOVRDEN.GTXE2_IMUX27_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFELFOVRDEN.GTXE2_IMUX27_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXLPMHFOVRDEN.GTXE2_IMUX27_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCOMSAS.GTXE2_IMUX28_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLLOCKEN.GTXE2_IMUX28_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPWE.GTXE2_IMUX28_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSYSCLKSEL1.GTXE2_IMUX28_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSYSCLKSEL0.GTXE2_IMUX28_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDLYEN.GTXE2_IMUX28_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPD1.GTXE2_IMUX28_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP2OVRDEN.GTXE2_IMUX28_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE3.GTXE2_IMUX29_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE2.GTXE2_IMUX29_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE1.GTXE2_IMUX29_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE0.GTXE2_IMUX29_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK7.GTXE2_IMUX29_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK6.GTXE2_IMUX29_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK5.GTXE2_IMUX29_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK4.GTXE2_IMUX29_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXOSHOLD.GTXE2_IMUX29_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP5HOLD.GTXE2_IMUX29_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEAGCHOLD.GTXE2_IMUX29_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR8.GTXE2_IMUX2_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPOSTCURSOR3.GTXE2_IMUX2_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDIFFCTRL3.GTXE2_IMUX2_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRECURSOR3.GTXE2_IMUX2_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXGEARBOXSLIP.GTXE2_IMUX2_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXMCOMMAALIGNEN.GTXE2_IMUX2_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKSEL2.GTXE2_IMUX2_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPOLARITY.GTXE2_IMUX30_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPCSRESET.GTXE2_IMUX30_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDRHOLD.GTXE2_IMUX30_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDMASTER.GTXE2_IMUX30_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDSLAVE.GTXE2_IMUX30_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE7.GTXE2_IMUX31_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE6.GTXE2_IMUX31_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE5.GTXE2_IMUX31_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPMODE4.GTXE2_IMUX31_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK3.GTXE2_IMUX31_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK2.GTXE2_IMUX31_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK1.GTXE2_IMUX31_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARISK0.GTXE2_IMUX31_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_EYESCANTRIGGER.GTXE2_IMUX31_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI11.GTXE2_IMUX32_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI15.GTXE2_IMUX32_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXINHIBIT.GTXE2_IMUX32_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDLYBYPASS.GTXE2_IMUX32_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI10.GTXE2_IMUX33_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI14.GTXE2_IMUX33_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHALIGNEN.GTXE2_IMUX33_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI3.GTXE2_IMUX34_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI7.GTXE2_IMUX34_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR3.GTXE2_IMUX34_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR7.GTXE2_IMUX34_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_SETERRSTATUS.GTXE2_IMUX34_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXLPMEN.GTXE2_IMUX34_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPCOMMAALIGNEN.GTXE2_IMUX34_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN20.GTXE2_IMUX34_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI2.GTXE2_IMUX35_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI6.GTXE2_IMUX35_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR2.GTXE2_IMUX35_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR6.GTXE2_IMUX35_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMARGIN2.GTXE2_IMUX35_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDEEMPH.GTXE2_IMUX35_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPD1.GTXE2_IMUX35_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEUTOVRDEN.GTXE2_IMUX35_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFELFHOLD.GTXE2_IMUX35_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN21.GTXE2_IMUX35_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI9.GTXE2_IMUX36_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI13.GTXE2_IMUX36_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLPD.GTXE2_IMUX36_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHDLYRESET.GTXE2_IMUX36_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP3HOLD.GTXE2_IMUX36_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI8.GTXE2_IMUX37_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI12.GTXE2_IMUX37_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHDLYPD.GTXE2_IMUX37_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDIFFPD.GTXE2_IMUX37_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEXYDHOLD.GTXE2_IMUX37_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP4HOLD.GTXE2_IMUX37_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI1.GTXE2_IMUX38_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI5.GTXE2_IMUX38_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR1.GTXE2_IMUX38_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR5.GTXE2_IMUX38_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMARGIN1.GTXE2_IMUX38_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSWING.GTXE2_IMUX38_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPD0.GTXE2_IMUX38_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDLYOVRDEN.GTXE2_IMUX38_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPRBSSEL1.GTXE2_IMUX38_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN22.GTXE2_IMUX38_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI0.GTXE2_IMUX39_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDI4.GTXE2_IMUX39_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR0.GTXE2_IMUX39_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPADDR4.GTXE2_IMUX39_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMARGIN0.GTXE2_IMUX39_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDETECTRX.GTXE2_IMUX39_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXELECIDLE.GTXE2_IMUX39_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN24.GTXE2_IMUX39_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN23.GTXE2_IMUX39_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSTARTSEQ.GTXE2_IMUX3_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPOSTCURSOR2.GTXE2_IMUX3_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDIFFCTRL2.GTXE2_IMUX3_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRECURSOR2.GTXE2_IMUX3_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPD0.GTXE2_IMUX3_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRBSSEL0.GTXE2_IMUX3_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEUTHOLD.GTXE2_IMUX3_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXLPMLFKLOVRDEN.GTXE2_IMUX3_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN0.GTXE2_IMUX40_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN1.GTXE2_IMUX40_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN2.GTXE2_IMUX40_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN3.GTXE2_IMUX40_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN4.GTXE2_IMUX40_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN5.GTXE2_IMUX40_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN6.GTXE2_IMUX40_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN7.GTXE2_IMUX40_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN8.GTXE2_IMUX40_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TSTIN9.GTXE2_IMUX40_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_EYESCANMODE.GTXE2_IMUX41_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPOSTCURSORINV.GTXE2_IMUX41_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RESETOVRD.GTXE2_IMUX41_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHALIGNEN.GTXE2_IMUX41_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXSYSCLKSEL1.GTXE2_IMUX42_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD0.GTXE2_IMUX42_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD1.GTXE2_IMUX42_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD2.GTXE2_IMUX42_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD3.GTXE2_IMUX42_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD4.GTXE2_IMUX42_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD5.GTXE2_IMUX42_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD6.GTXE2_IMUX42_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_GTRSVD7.GTXE2_IMUX42_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYUPDOWN.GTXE2_IMUX43_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXRATE2.GTXE2_IMUX43_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_LOOPBACK0.GTXE2_IMUX43_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXLPMHFHOLD.GTXE2_IMUX43_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCOMINIT.GTXE2_IMUX44_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_DRPEN.GTXE2_IMUX44_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYBYPASS.GTXE2_IMUX44_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXUSERRDY.GTXE2_IMUX44_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMMADETEN.GTXE2_IMUX44_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFETAP2HOLD.GTXE2_IMUX44_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPIWEAKPUP.GTXE2_IMUX45_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXSYSCLKSEL0.GTXE2_IMUX45_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYSRESET.GTXE2_IMUX45_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_EYESCANRESET.GTXE2_IMUX45_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDFEXYDEN.GTXE2_IMUX45_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITORSEL0.GTXE2_IMUX45_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXRATE1.GTXE2_IMUX46_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_LOOPBACK1.GTXE2_IMUX46_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXRATE0.GTXE2_IMUX47_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_LOOPBACK2.GTXE2_IMUX47_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRECURSORINV.GTXE2_IMUX4_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMAINCURSOR1.GTXE2_IMUX4_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMAINCURSOR5.GTXE2_IMUX4_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSEQUENCE1.GTXE2_IMUX4_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSEQUENCE5.GTXE2_IMUX4_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN21.GTXE2_IMUX4_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN1.GTXE2_IMUX4_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKSEL1.GTXE2_IMUX4_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKSEL0.GTXE2_IMUX4_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPIBIASEN.GTXE2_IMUX5_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMAINCURSOR0.GTXE2_IMUX5_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXMAINCURSOR4.GTXE2_IMUX5_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSEQUENCE0.GTXE2_IMUX5_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXSEQUENCE4.GTXE2_IMUX5_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN20.GTXE2_IMUX5_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PMARSVDIN0.GTXE2_IMUX5_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKSEL0.GTXE2_IMUX5_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKSEL1.GTXE2_IMUX5_10 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPOSTCURSOR1.GTXE2_IMUX6_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDIFFCTRL1.GTXE2_IMUX6_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRECURSOR1.GTXE2_IMUX6_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRBSSEL1.GTXE2_IMUX6_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPISOPD.GTXE2_IMUX7_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPOSTCURSOR4.GTXE2_IMUX7_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPOSTCURSOR0.GTXE2_IMUX7_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXDIFFCTRL0.GTXE2_IMUX7_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRECURSOR0.GTXE2_IMUX7_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRECURSOR4.GTXE2_IMUX7_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXPRBSSEL2.GTXE2_IMUX7_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL3.GTXE2_IMUX8_0 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL2.GTXE2_IMUX8_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL1.GTXE2_IMUX8_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXCHARDISPVAL0.GTXE2_IMUX8_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS7.GTXE2_IMUX8_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS6.GTXE2_IMUX8_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS5.GTXE2_IMUX8_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TX8B10BBYPASS4.GTXE2_IMUX8_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXDDIEN.GTXE2_IMUX8_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHDLYPD.GTXE2_IMUX9_1 always
GTX_CHANNEL_0.GTXE2_CHANNEL_TXHEADER2.GTXE2_IMUX9_2 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN8.GTXE2_IMUX9_3 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN9.GTXE2_IMUX9_4 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN10.GTXE2_IMUX9_5 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN11.GTXE2_IMUX9_6 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN12.GTXE2_IMUX9_7 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN13.GTXE2_IMUX9_8 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN14.GTXE2_IMUX9_9 always
GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDIN15.GTXE2_IMUX9_10 always

626
virtex7/ppips_gtx_channel_1.db Normal file
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@ -0,0 +1,626 @@
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_1.GTXE2_CHANNEL_CPLLFBCLKLOST always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_1.GTXE2_CHANNEL_CPLLLOCK always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_1.GTXE2_CHANNEL_CPLLREFCLKLOST always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_10.GTXE2_CHANNEL_DMONITOROUT0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_9.GTXE2_CHANNEL_DMONITOROUT1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_8.GTXE2_CHANNEL_DMONITOROUT2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_7.GTXE2_CHANNEL_DMONITOROUT3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_6.GTXE2_CHANNEL_DMONITOROUT4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_5.GTXE2_CHANNEL_DMONITOROUT5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_4.GTXE2_CHANNEL_DMONITOROUT6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_3.GTXE2_CHANNEL_DMONITOROUT7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_0.GTXE2_CHANNEL_DRPDO0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_1.GTXE2_CHANNEL_DRPDO8 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_0.GTXE2_CHANNEL_DRPDO1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_1.GTXE2_CHANNEL_DRPDO9 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_0.GTXE2_CHANNEL_DRPDO2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_1.GTXE2_CHANNEL_DRPDO10 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_0.GTXE2_CHANNEL_DRPDO3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_1.GTXE2_CHANNEL_DRPDO11 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_0.GTXE2_CHANNEL_DRPDO4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_1.GTXE2_CHANNEL_DRPDO12 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_0.GTXE2_CHANNEL_DRPDO5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_1.GTXE2_CHANNEL_DRPDO13 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_0.GTXE2_CHANNEL_DRPDO6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_1.GTXE2_CHANNEL_DRPDO14 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_0.GTXE2_CHANNEL_DRPDO7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_1.GTXE2_CHANNEL_DRPDO15 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_0.GTXE2_CHANNEL_DRPRDY always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_10.GTXE2_CHANNEL_EYESCANDATAERROR always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_2.GTXE2_CHANNEL_GTREFCLKMONITOR always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLK_1.GTXE2_CHANNEL_GTRXOUTCLK_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLK_1.GTXE2_CHANNEL_GTTXOUTCLK_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTNORTHREFCLK0.GTXE2_CHANNEL_NORTHREFCLK0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTNORTHREFCLK1.GTXE2_CHANNEL_NORTHREFCLK1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_0.GTXE2_CHANNEL_PCSRSVDOUT0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_1.GTXE2_CHANNEL_PCSRSVDOUT1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_2.GTXE2_CHANNEL_PCSRSVDOUT2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_3.GTXE2_CHANNEL_PCSRSVDOUT3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_4.GTXE2_CHANNEL_PCSRSVDOUT4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_5.GTXE2_CHANNEL_PCSRSVDOUT5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_6.GTXE2_CHANNEL_PCSRSVDOUT6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_7.GTXE2_CHANNEL_PCSRSVDOUT7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_8.GTXE2_CHANNEL_PCSRSVDOUT8 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_9.GTXE2_CHANNEL_PCSRSVDOUT9 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B13_10.GTXE2_CHANNEL_PCSRSVDOUT10 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_0.GTXE2_CHANNEL_PCSRSVDOUT11 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_1.GTXE2_CHANNEL_PCSRSVDOUT12 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B9_2.GTXE2_CHANNEL_PCSRSVDOUT13 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_0.GTXE2_CHANNEL_PCSRSVDOUT14 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_1.GTXE2_CHANNEL_PCSRSVDOUT15 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B10_9.GTXE2_CHANNEL_PHYSTATUS always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTQPLLCLK.GTXE2_CHANNEL_QPLLCLK always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTQPLLREFCLK.GTXE2_CHANNEL_QPLLREFCLK always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTREFCLK0.GTXE2_CHANNEL_REFCLK0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTREFCLK1.GTXE2_CHANNEL_REFCLK1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_10.GTXE2_CHANNEL_RXBUFSTATUS0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B19_10.GTXE2_CHANNEL_RXBUFSTATUS1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_10.GTXE2_CHANNEL_RXBUFSTATUS2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_10.GTXE2_CHANNEL_RXBYTEISALIGNED always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B10_10.GTXE2_CHANNEL_RXBYTEREALIGN always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_5.GTXE2_CHANNEL_RXCDRLOCK always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B10_8.GTXE2_CHANNEL_RXCHANBONDSEQ always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_9.GTXE2_CHANNEL_RXCHANISALIGNED always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_9.GTXE2_CHANNEL_RXCHANREALIGN always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_9.GTXE2_CHANNEL_RXCHARISCOMMA0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_7.GTXE2_CHANNEL_RXCHARISCOMMA1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_5.GTXE2_CHANNEL_RXCHARISCOMMA2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_3.GTXE2_CHANNEL_RXCHARISCOMMA3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_10.GTXE2_CHANNEL_RXCHARISCOMMA4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_8.GTXE2_CHANNEL_RXCHARISCOMMA5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_6.GTXE2_CHANNEL_RXCHARISCOMMA6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_4.GTXE2_CHANNEL_RXCHARISCOMMA7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_10.GTXE2_CHANNEL_RXCHARISK0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_8.GTXE2_CHANNEL_RXCHARISK1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_6.GTXE2_CHANNEL_RXCHARISK2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_4.GTXE2_CHANNEL_RXCHARISK3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_9.GTXE2_CHANNEL_RXCHARISK4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_7.GTXE2_CHANNEL_RXCHARISK5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_5.GTXE2_CHANNEL_RXCHARISK6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B12_3.GTXE2_CHANNEL_RXCHARISK7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_10.GTXE2_CHANNEL_RXCHBONDO0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_9.GTXE2_CHANNEL_RXCHBONDO1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_8.GTXE2_CHANNEL_RXCHBONDO2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_7.GTXE2_CHANNEL_RXCHBONDO3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_6.GTXE2_CHANNEL_RXCHBONDO4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_5.GTXE2_CHANNEL_RXCLKCORCNT0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_5.GTXE2_CHANNEL_RXCLKCORCNT1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_7.GTXE2_CHANNEL_RXCOMINITDET always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B19_7.GTXE2_CHANNEL_RXCOMMADET always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_7.GTXE2_CHANNEL_RXCOMSASDET always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B19_9.GTXE2_CHANNEL_RXCOMWAKEDET always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_10.GTXE2_CHANNEL_RXDATA0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_8.GTXE2_CHANNEL_RXDATA8 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_6.GTXE2_CHANNEL_RXDATA16 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_4.GTXE2_CHANNEL_RXDATA24 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_9.GTXE2_CHANNEL_RXDATA36 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_7.GTXE2_CHANNEL_RXDATA44 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_5.GTXE2_CHANNEL_RXDATA52 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_3.GTXE2_CHANNEL_RXDATA60 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_10.GTXE2_CHANNEL_RXDATA1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_8.GTXE2_CHANNEL_RXDATA9 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_6.GTXE2_CHANNEL_RXDATA17 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_4.GTXE2_CHANNEL_RXDATA25 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_9.GTXE2_CHANNEL_RXDATA37 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_7.GTXE2_CHANNEL_RXDATA45 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_5.GTXE2_CHANNEL_RXDATA53 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_3.GTXE2_CHANNEL_RXDATA61 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_10.GTXE2_CHANNEL_RXDATA2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_8.GTXE2_CHANNEL_RXDATA10 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_6.GTXE2_CHANNEL_RXDATA18 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_4.GTXE2_CHANNEL_RXDATA26 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_9.GTXE2_CHANNEL_RXDATA38 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_7.GTXE2_CHANNEL_RXDATA46 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_5.GTXE2_CHANNEL_RXDATA54 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_3.GTXE2_CHANNEL_RXDATA62 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_10.GTXE2_CHANNEL_RXDATA3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_8.GTXE2_CHANNEL_RXDATA11 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_6.GTXE2_CHANNEL_RXDATA19 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_4.GTXE2_CHANNEL_RXDATA27 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_9.GTXE2_CHANNEL_RXDATA39 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_7.GTXE2_CHANNEL_RXDATA47 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_5.GTXE2_CHANNEL_RXDATA55 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_3.GTXE2_CHANNEL_RXDATA63 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_9.GTXE2_CHANNEL_RXDATA4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_7.GTXE2_CHANNEL_RXDATA12 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_5.GTXE2_CHANNEL_RXDATA20 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_3.GTXE2_CHANNEL_RXDATA28 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_10.GTXE2_CHANNEL_RXDATA32 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_8.GTXE2_CHANNEL_RXDATA40 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_6.GTXE2_CHANNEL_RXDATA48 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_4.GTXE2_CHANNEL_RXDATA56 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_9.GTXE2_CHANNEL_RXDATA5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_7.GTXE2_CHANNEL_RXDATA13 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_5.GTXE2_CHANNEL_RXDATA21 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_3.GTXE2_CHANNEL_RXDATA29 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_10.GTXE2_CHANNEL_RXDATA33 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_8.GTXE2_CHANNEL_RXDATA41 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_6.GTXE2_CHANNEL_RXDATA49 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_4.GTXE2_CHANNEL_RXDATA57 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_9.GTXE2_CHANNEL_RXDATA6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_7.GTXE2_CHANNEL_RXDATA14 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_5.GTXE2_CHANNEL_RXDATA22 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_3.GTXE2_CHANNEL_RXDATA30 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_10.GTXE2_CHANNEL_RXDATA34 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_8.GTXE2_CHANNEL_RXDATA42 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_6.GTXE2_CHANNEL_RXDATA50 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_4.GTXE2_CHANNEL_RXDATA58 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_9.GTXE2_CHANNEL_RXDATA7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_7.GTXE2_CHANNEL_RXDATA15 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_5.GTXE2_CHANNEL_RXDATA23 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_3.GTXE2_CHANNEL_RXDATA31 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_10.GTXE2_CHANNEL_RXDATA35 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_8.GTXE2_CHANNEL_RXDATA43 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_6.GTXE2_CHANNEL_RXDATA51 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_4.GTXE2_CHANNEL_RXDATA59 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B19_5.GTXE2_CHANNEL_RXDATAVALID always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_10.GTXE2_CHANNEL_RXDISPERR0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_8.GTXE2_CHANNEL_RXDISPERR1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_6.GTXE2_CHANNEL_RXDISPERR2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_4.GTXE2_CHANNEL_RXDISPERR3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_9.GTXE2_CHANNEL_RXDISPERR4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_7.GTXE2_CHANNEL_RXDISPERR5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_5.GTXE2_CHANNEL_RXDISPERR6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_3.GTXE2_CHANNEL_RXDISPERR7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B22_1.GTXE2_CHANNEL_RXDLYSRESETDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B19_8.GTXE2_CHANNEL_RXELECIDLE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B19_6.GTXE2_CHANNEL_RXHEADER0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_6.GTXE2_CHANNEL_RXHEADER1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_6.GTXE2_CHANNEL_RXHEADER2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_7.GTXE2_CHANNEL_RXHEADERVALID always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_10.GTXE2_CHANNEL_RXMONITOROUT0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_9.GTXE2_CHANNEL_RXMONITOROUT1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_8.GTXE2_CHANNEL_RXMONITOROUT2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_7.GTXE2_CHANNEL_RXMONITOROUT3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_6.GTXE2_CHANNEL_RXMONITOROUT4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_5.GTXE2_CHANNEL_RXMONITOROUT5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_4.GTXE2_CHANNEL_RXMONITOROUT6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_10.GTXE2_CHANNEL_RXNOTINTABLE0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_8.GTXE2_CHANNEL_RXNOTINTABLE1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_6.GTXE2_CHANNEL_RXNOTINTABLE2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_4.GTXE2_CHANNEL_RXNOTINTABLE3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_9.GTXE2_CHANNEL_RXNOTINTABLE4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_7.GTXE2_CHANNEL_RXNOTINTABLE5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_5.GTXE2_CHANNEL_RXNOTINTABLE6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B14_3.GTXE2_CHANNEL_RXNOTINTABLE7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXN.GTXE2_CHANNEL_RXN_PAD always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_9.GTXE2_CHANNEL_RXOUTCLKFABRIC always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B21_9.GTXE2_CHANNEL_RXOUTCLKPCS always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_4.GTXE2_CHANNEL_RXPHALIGNDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B5_2.GTXE2_CHANNEL_RXPHMONITOR0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B1_2.GTXE2_CHANNEL_RXPHMONITOR1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B7_2.GTXE2_CHANNEL_RXPHMONITOR2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B3_2.GTXE2_CHANNEL_RXPHMONITOR3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B21_3.GTXE2_CHANNEL_RXPHMONITOR4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B0_2.GTXE2_CHANNEL_RXPHSLIPMONITOR0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B4_2.GTXE2_CHANNEL_RXPHSLIPMONITOR1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B2_2.GTXE2_CHANNEL_RXPHSLIPMONITOR2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B6_2.GTXE2_CHANNEL_RXPHSLIPMONITOR3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_3.GTXE2_CHANNEL_RXPHSLIPMONITOR4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_6.GTXE2_CHANNEL_RXPRBSERR always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXP.GTXE2_CHANNEL_RXP_PAD always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_1.GTXE2_CHANNEL_RXQPISENN always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B15_1.GTXE2_CHANNEL_RXQPISENP always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_5.GTXE2_CHANNEL_RXRATEDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_8.GTXE2_CHANNEL_RXRESETDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_8.GTXE2_CHANNEL_RXSTARTOFSEQ always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B21_8.GTXE2_CHANNEL_RXSTATUS0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_8.GTXE2_CHANNEL_RXSTATUS1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_8.GTXE2_CHANNEL_RXSTATUS2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_9.GTXE2_CHANNEL_RXVALID always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_0.GTXE2_CHANNEL_TSTOUT0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_1.GTXE2_CHANNEL_TSTOUT1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_2.GTXE2_CHANNEL_TSTOUT2 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_3.GTXE2_CHANNEL_TSTOUT3 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_4.GTXE2_CHANNEL_TSTOUT4 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_5.GTXE2_CHANNEL_TSTOUT5 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_6.GTXE2_CHANNEL_TSTOUT6 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_7.GTXE2_CHANNEL_TSTOUT7 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_8.GTXE2_CHANNEL_TSTOUT8 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B11_9.GTXE2_CHANNEL_TSTOUT9 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_2.GTXE2_CHANNEL_TXBUFSTATUS0 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B21_2.GTXE2_CHANNEL_TXBUFSTATUS1 always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_5.GTXE2_CHANNEL_TXCOMFINISH always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_3.GTXE2_CHANNEL_TXDLYSRESETDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_4.GTXE2_CHANNEL_TXGEARBOXREADY always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXN_PAD.GTXE2_CHANNEL_TXN always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B23_3.GTXE2_CHANNEL_TXOUTCLKFABRIC always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_4.GTXE2_CHANNEL_TXOUTCLKPCS always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXP_PAD.GTXE2_CHANNEL_TXP always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B18_3.GTXE2_CHANNEL_TXPHALIGNDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B17_0.GTXE2_CHANNEL_TXPHINITDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_3.GTXE2_CHANNEL_TXQPISENN always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B8_3.GTXE2_CHANNEL_TXQPISENP always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B20_4.GTXE2_CHANNEL_TXRATEDONE always
GTX_CHANNEL_1.GTXE2_LOGIC_OUTS_B16_4.GTXE2_CHANNEL_TXRESETDONE always
GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLLOCKDETCLK.GTXE2_CLK0_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXUSRCLK.GTXE2_CLK0_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXUSRCLK2.GTXE2_CLK0_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXUSRCLK.GTXE2_CLK0_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXUSRCLK2.GTXE2_CLK0_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPCLK.GTXE2_CLK1_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHDLYTSTCLK.GTXE2_CLK1_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CLKRSVD0.GTXE2_CLK1_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CLKRSVD1.GTXE2_CLK1_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CLKRSVD2.GTXE2_CLK1_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CLKRSVD3.GTXE2_CLK1_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTGREFCLK.GTXE2_CLK1_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLRESET.GTXE2_CTRL0_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTTXRESET.GTXE2_CTRL0_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDLYSRESET.GTXE2_CTRL0_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCDRFREQRESET.GTXE2_CTRL0_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRXRESET.GTXE2_CTRL0_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFELPMRESET.GTXE2_CTRL0_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRESETSEL.GTXE2_CTRL0_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHDLYRESET.GTXE2_CTRL1_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPMARESET.GTXE2_CTRL1_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CFGRESET.GTXE2_CTRL1_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXBUFRESET.GTXE2_CTRL1_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPMARESET.GTXE2_CTRL1_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCDRRESETRSV.GTXE2_CTRL1_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCDRRESET.GTXE2_CTRL1_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXOOBRESET.GTXE2_CTRL1_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BEN.GTXE2_IMUX0_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMAINCURSOR3.GTXE2_IMUX0_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSEQUENCE3.GTXE2_IMUX0_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN24.GTXE2_IMUX0_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN23.GTXE2_IMUX0_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN4.GTXE2_IMUX0_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN3.GTXE2_IMUX0_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXELECIDLEMODE0.GTXE2_IMUX0_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL7.GTXE2_IMUX10_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL6.GTXE2_IMUX10_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL5.GTXE2_IMUX10_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL4.GTXE2_IMUX10_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPDELECIDLEMODE.GTXE2_IMUX10_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXUSERRDY.GTXE2_IMUX10_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXBUFDIFFCTRL2.GTXE2_IMUX10_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXQPIEN.GTXE2_IMUX10_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLREFCLKSEL2.GTXE2_IMUX11_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYHOLD.GTXE2_IMUX11_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXRATE2.GTXE2_IMUX11_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEVSEN.GTXE2_IMUX11_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXLPMLFHOLD.GTXE2_IMUX11_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCOMWAKE.GTXE2_IMUX12_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXHEADER1.GTXE2_IMUX12_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHOVRDEN.GTXE2_IMUX12_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYOVRDEN.GTXE2_IMUX12_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXBUFDIFFCTRL0.GTXE2_IMUX12_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXSLIDE.GTXE2_IMUX12_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RX8B10BEN.GTXE2_IMUX12_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP3OVRDEN.GTXE2_IMUX12_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXQPISTRONGPDOWN.GTXE2_IMUX13_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXHEADER0.GTXE2_IMUX13_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXBUFDIFFCTRL1.GTXE2_IMUX13_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXOSOVRDEN.GTXE2_IMUX13_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP5OVRDEN.GTXE2_IMUX13_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPRBSCNTRESET.GTXE2_IMUX13_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLREFCLKSEL1.GTXE2_IMUX14_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYEN.GTXE2_IMUX14_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXRATE1.GTXE2_IMUX14_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPCSRESET.GTXE2_IMUX14_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCDROVRDEN.GTXE2_IMUX14_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHALIGN.GTXE2_IMUX14_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHOVRDEN.GTXE2_IMUX14_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS3.GTXE2_IMUX15_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS2.GTXE2_IMUX15_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS1.GTXE2_IMUX15_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS0.GTXE2_IMUX15_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLREFCLKSEL0.GTXE2_IMUX15_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRBSFORCEERR.GTXE2_IMUX15_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXRATE0.GTXE2_IMUX15_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA28.GTXE2_IMUX16_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA56.GTXE2_IMUX16_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA20.GTXE2_IMUX16_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA48.GTXE2_IMUX16_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA12.GTXE2_IMUX16_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA40.GTXE2_IMUX16_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA4.GTXE2_IMUX16_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA35.GTXE2_IMUX16_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFECM1EN.GTXE2_IMUX16_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA29.GTXE2_IMUX17_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA57.GTXE2_IMUX17_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA21.GTXE2_IMUX17_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA49.GTXE2_IMUX17_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA13.GTXE2_IMUX17_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA41.GTXE2_IMUX17_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA5.GTXE2_IMUX17_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA34.GTXE2_IMUX17_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDEN.GTXE2_IMUX17_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA60.GTXE2_IMUX18_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA24.GTXE2_IMUX18_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA52.GTXE2_IMUX18_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA16.GTXE2_IMUX18_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA44.GTXE2_IMUX18_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA8.GTXE2_IMUX18_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA36.GTXE2_IMUX18_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA0.GTXE2_IMUX18_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDI0.GTXE2_IMUX18_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDLEVEL0.GTXE2_IMUX18_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA61.GTXE2_IMUX19_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA25.GTXE2_IMUX19_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA53.GTXE2_IMUX19_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA17.GTXE2_IMUX19_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA45.GTXE2_IMUX19_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA9.GTXE2_IMUX19_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA37.GTXE2_IMUX19_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA1.GTXE2_IMUX19_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEVPHOLD.GTXE2_IMUX19_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDI1.GTXE2_IMUX19_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDLEVEL1.GTXE2_IMUX19_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITORSEL1.GTXE2_IMUX1_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMAINCURSOR2.GTXE2_IMUX1_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMAINCURSOR6.GTXE2_IMUX1_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSEQUENCE2.GTXE2_IMUX1_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSEQUENCE6.GTXE2_IMUX1_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN22.GTXE2_IMUX1_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN2.GTXE2_IMUX1_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLKSEL2.GTXE2_IMUX1_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXELECIDLEMODE1.GTXE2_IMUX1_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA30.GTXE2_IMUX20_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA58.GTXE2_IMUX20_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA22.GTXE2_IMUX20_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA50.GTXE2_IMUX20_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA14.GTXE2_IMUX20_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA42.GTXE2_IMUX20_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA6.GTXE2_IMUX20_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA33.GTXE2_IMUX20_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA31.GTXE2_IMUX21_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA59.GTXE2_IMUX21_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA23.GTXE2_IMUX21_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA51.GTXE2_IMUX21_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA15.GTXE2_IMUX21_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA43.GTXE2_IMUX21_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA7.GTXE2_IMUX21_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA32.GTXE2_IMUX21_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEXYDOVRDEN.GTXE2_IMUX21_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP4OVRDEN.GTXE2_IMUX21_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEAGCOVRDEN.GTXE2_IMUX21_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA62.GTXE2_IMUX22_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA26.GTXE2_IMUX22_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA54.GTXE2_IMUX22_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA18.GTXE2_IMUX22_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA46.GTXE2_IMUX22_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA10.GTXE2_IMUX22_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA38.GTXE2_IMUX22_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA2.GTXE2_IMUX22_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPRBSSEL0.GTXE2_IMUX22_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDI2.GTXE2_IMUX22_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDLEVEL2.GTXE2_IMUX22_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA63.GTXE2_IMUX23_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA27.GTXE2_IMUX23_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA55.GTXE2_IMUX23_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA19.GTXE2_IMUX23_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA47.GTXE2_IMUX23_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA11.GTXE2_IMUX23_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA39.GTXE2_IMUX23_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDATA3.GTXE2_IMUX23_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPRBSSEL2.GTXE2_IMUX23_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDI3.GTXE2_IMUX23_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDI4.GTXE2_IMUX23_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN10.GTXE2_IMUX24_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN11.GTXE2_IMUX24_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN12.GTXE2_IMUX24_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN13.GTXE2_IMUX24_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN14.GTXE2_IMUX24_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN15.GTXE2_IMUX24_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN16.GTXE2_IMUX24_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN17.GTXE2_IMUX24_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN18.GTXE2_IMUX24_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN19.GTXE2_IMUX24_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHALIGN.GTXE2_IMUX25_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN0.GTXE2_IMUX25_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN1.GTXE2_IMUX25_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN2.GTXE2_IMUX25_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN3.GTXE2_IMUX25_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN4.GTXE2_IMUX25_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN5.GTXE2_IMUX25_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN6.GTXE2_IMUX25_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN7.GTXE2_IMUX25_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD8.GTXE2_IMUX26_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD9.GTXE2_IMUX26_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD10.GTXE2_IMUX26_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD11.GTXE2_IMUX26_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD12.GTXE2_IMUX26_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD13.GTXE2_IMUX26_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD14.GTXE2_IMUX26_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD15.GTXE2_IMUX26_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHINIT.GTXE2_IMUX27_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPOLARITY.GTXE2_IMUX27_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEVPOVRDEN.GTXE2_IMUX27_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFELFOVRDEN.GTXE2_IMUX27_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXLPMHFOVRDEN.GTXE2_IMUX27_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCOMSAS.GTXE2_IMUX28_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLLOCKEN.GTXE2_IMUX28_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPWE.GTXE2_IMUX28_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSYSCLKSEL1.GTXE2_IMUX28_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSYSCLKSEL0.GTXE2_IMUX28_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDLYEN.GTXE2_IMUX28_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPD1.GTXE2_IMUX28_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP2OVRDEN.GTXE2_IMUX28_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE3.GTXE2_IMUX29_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE2.GTXE2_IMUX29_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE1.GTXE2_IMUX29_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE0.GTXE2_IMUX29_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK7.GTXE2_IMUX29_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK6.GTXE2_IMUX29_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK5.GTXE2_IMUX29_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK4.GTXE2_IMUX29_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXOSHOLD.GTXE2_IMUX29_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP5HOLD.GTXE2_IMUX29_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEAGCHOLD.GTXE2_IMUX29_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR8.GTXE2_IMUX2_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPOSTCURSOR3.GTXE2_IMUX2_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDIFFCTRL3.GTXE2_IMUX2_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRECURSOR3.GTXE2_IMUX2_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXGEARBOXSLIP.GTXE2_IMUX2_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXMCOMMAALIGNEN.GTXE2_IMUX2_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLKSEL2.GTXE2_IMUX2_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPOLARITY.GTXE2_IMUX30_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPCSRESET.GTXE2_IMUX30_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCDRHOLD.GTXE2_IMUX30_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDMASTER.GTXE2_IMUX30_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDSLAVE.GTXE2_IMUX30_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE7.GTXE2_IMUX31_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE6.GTXE2_IMUX31_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE5.GTXE2_IMUX31_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPMODE4.GTXE2_IMUX31_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK3.GTXE2_IMUX31_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK2.GTXE2_IMUX31_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK1.GTXE2_IMUX31_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARISK0.GTXE2_IMUX31_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_EYESCANTRIGGER.GTXE2_IMUX31_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI11.GTXE2_IMUX32_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI15.GTXE2_IMUX32_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXINHIBIT.GTXE2_IMUX32_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDLYBYPASS.GTXE2_IMUX32_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI10.GTXE2_IMUX33_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI14.GTXE2_IMUX33_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHALIGNEN.GTXE2_IMUX33_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI3.GTXE2_IMUX34_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI7.GTXE2_IMUX34_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR3.GTXE2_IMUX34_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR7.GTXE2_IMUX34_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_SETERRSTATUS.GTXE2_IMUX34_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXLPMEN.GTXE2_IMUX34_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPCOMMAALIGNEN.GTXE2_IMUX34_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN20.GTXE2_IMUX34_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI2.GTXE2_IMUX35_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI6.GTXE2_IMUX35_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR2.GTXE2_IMUX35_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR6.GTXE2_IMUX35_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMARGIN2.GTXE2_IMUX35_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDEEMPH.GTXE2_IMUX35_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPD1.GTXE2_IMUX35_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEUTOVRDEN.GTXE2_IMUX35_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFELFHOLD.GTXE2_IMUX35_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN21.GTXE2_IMUX35_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI9.GTXE2_IMUX36_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI13.GTXE2_IMUX36_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLPD.GTXE2_IMUX36_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHDLYRESET.GTXE2_IMUX36_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP3HOLD.GTXE2_IMUX36_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI8.GTXE2_IMUX37_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI12.GTXE2_IMUX37_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHDLYPD.GTXE2_IMUX37_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDIFFPD.GTXE2_IMUX37_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEXYDHOLD.GTXE2_IMUX37_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP4HOLD.GTXE2_IMUX37_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI1.GTXE2_IMUX38_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI5.GTXE2_IMUX38_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR1.GTXE2_IMUX38_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR5.GTXE2_IMUX38_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMARGIN1.GTXE2_IMUX38_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSWING.GTXE2_IMUX38_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPD0.GTXE2_IMUX38_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDLYOVRDEN.GTXE2_IMUX38_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPRBSSEL1.GTXE2_IMUX38_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN22.GTXE2_IMUX38_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI0.GTXE2_IMUX39_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDI4.GTXE2_IMUX39_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR0.GTXE2_IMUX39_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPADDR4.GTXE2_IMUX39_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMARGIN0.GTXE2_IMUX39_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDETECTRX.GTXE2_IMUX39_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXELECIDLE.GTXE2_IMUX39_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN24.GTXE2_IMUX39_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN23.GTXE2_IMUX39_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSTARTSEQ.GTXE2_IMUX3_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPOSTCURSOR2.GTXE2_IMUX3_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDIFFCTRL2.GTXE2_IMUX3_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRECURSOR2.GTXE2_IMUX3_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPD0.GTXE2_IMUX3_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRBSSEL0.GTXE2_IMUX3_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEUTHOLD.GTXE2_IMUX3_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXLPMLFKLOVRDEN.GTXE2_IMUX3_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN0.GTXE2_IMUX40_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN1.GTXE2_IMUX40_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN2.GTXE2_IMUX40_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN3.GTXE2_IMUX40_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN4.GTXE2_IMUX40_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN5.GTXE2_IMUX40_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN6.GTXE2_IMUX40_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN7.GTXE2_IMUX40_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN8.GTXE2_IMUX40_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TSTIN9.GTXE2_IMUX40_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_EYESCANMODE.GTXE2_IMUX41_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPOSTCURSORINV.GTXE2_IMUX41_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RESETOVRD.GTXE2_IMUX41_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHALIGNEN.GTXE2_IMUX41_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXSYSCLKSEL1.GTXE2_IMUX42_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD0.GTXE2_IMUX42_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD1.GTXE2_IMUX42_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD2.GTXE2_IMUX42_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD3.GTXE2_IMUX42_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD4.GTXE2_IMUX42_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD5.GTXE2_IMUX42_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD6.GTXE2_IMUX42_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_GTRSVD7.GTXE2_IMUX42_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYUPDOWN.GTXE2_IMUX43_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXRATE2.GTXE2_IMUX43_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_LOOPBACK0.GTXE2_IMUX43_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXLPMHFHOLD.GTXE2_IMUX43_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCOMINIT.GTXE2_IMUX44_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_DRPEN.GTXE2_IMUX44_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYBYPASS.GTXE2_IMUX44_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXUSERRDY.GTXE2_IMUX44_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMMADETEN.GTXE2_IMUX44_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFETAP2HOLD.GTXE2_IMUX44_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXQPIWEAKPUP.GTXE2_IMUX45_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXSYSCLKSEL0.GTXE2_IMUX45_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYSRESET.GTXE2_IMUX45_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_EYESCANRESET.GTXE2_IMUX45_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDFEXYDEN.GTXE2_IMUX45_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITORSEL0.GTXE2_IMUX45_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXRATE1.GTXE2_IMUX46_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_LOOPBACK1.GTXE2_IMUX46_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXRATE0.GTXE2_IMUX47_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_LOOPBACK2.GTXE2_IMUX47_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRECURSORINV.GTXE2_IMUX4_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMAINCURSOR1.GTXE2_IMUX4_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMAINCURSOR5.GTXE2_IMUX4_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSEQUENCE1.GTXE2_IMUX4_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSEQUENCE5.GTXE2_IMUX4_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN21.GTXE2_IMUX4_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN1.GTXE2_IMUX4_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLKSEL1.GTXE2_IMUX4_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLKSEL0.GTXE2_IMUX4_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXQPIBIASEN.GTXE2_IMUX5_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMAINCURSOR0.GTXE2_IMUX5_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXMAINCURSOR4.GTXE2_IMUX5_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSEQUENCE0.GTXE2_IMUX5_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXSEQUENCE4.GTXE2_IMUX5_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN20.GTXE2_IMUX5_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PMARSVDIN0.GTXE2_IMUX5_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLKSEL0.GTXE2_IMUX5_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLKSEL1.GTXE2_IMUX5_10 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPOSTCURSOR1.GTXE2_IMUX6_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDIFFCTRL1.GTXE2_IMUX6_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRECURSOR1.GTXE2_IMUX6_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRBSSEL1.GTXE2_IMUX6_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPISOPD.GTXE2_IMUX7_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPOSTCURSOR4.GTXE2_IMUX7_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPOSTCURSOR0.GTXE2_IMUX7_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXDIFFCTRL0.GTXE2_IMUX7_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRECURSOR0.GTXE2_IMUX7_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRECURSOR4.GTXE2_IMUX7_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXPRBSSEL2.GTXE2_IMUX7_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL3.GTXE2_IMUX8_0 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL2.GTXE2_IMUX8_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL1.GTXE2_IMUX8_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXCHARDISPVAL0.GTXE2_IMUX8_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS7.GTXE2_IMUX8_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS6.GTXE2_IMUX8_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS5.GTXE2_IMUX8_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TX8B10BBYPASS4.GTXE2_IMUX8_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXDDIEN.GTXE2_IMUX8_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHDLYPD.GTXE2_IMUX9_1 always
GTX_CHANNEL_1.GTXE2_CHANNEL_TXHEADER2.GTXE2_IMUX9_2 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN8.GTXE2_IMUX9_3 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN9.GTXE2_IMUX9_4 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN10.GTXE2_IMUX9_5 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN11.GTXE2_IMUX9_6 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN12.GTXE2_IMUX9_7 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN13.GTXE2_IMUX9_8 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN14.GTXE2_IMUX9_9 always
GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDIN15.GTXE2_IMUX9_10 always

626
virtex7/ppips_gtx_channel_2.db Normal file
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@ -0,0 +1,626 @@
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_1.GTXE2_CHANNEL_CPLLFBCLKLOST always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_1.GTXE2_CHANNEL_CPLLLOCK always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_1.GTXE2_CHANNEL_CPLLREFCLKLOST always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_10.GTXE2_CHANNEL_DMONITOROUT0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_9.GTXE2_CHANNEL_DMONITOROUT1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_8.GTXE2_CHANNEL_DMONITOROUT2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_7.GTXE2_CHANNEL_DMONITOROUT3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_6.GTXE2_CHANNEL_DMONITOROUT4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_5.GTXE2_CHANNEL_DMONITOROUT5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_4.GTXE2_CHANNEL_DMONITOROUT6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_3.GTXE2_CHANNEL_DMONITOROUT7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_0.GTXE2_CHANNEL_DRPDO0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_1.GTXE2_CHANNEL_DRPDO8 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_0.GTXE2_CHANNEL_DRPDO1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_1.GTXE2_CHANNEL_DRPDO9 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_0.GTXE2_CHANNEL_DRPDO2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_1.GTXE2_CHANNEL_DRPDO10 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_0.GTXE2_CHANNEL_DRPDO3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_1.GTXE2_CHANNEL_DRPDO11 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_0.GTXE2_CHANNEL_DRPDO4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_1.GTXE2_CHANNEL_DRPDO12 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_0.GTXE2_CHANNEL_DRPDO5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_1.GTXE2_CHANNEL_DRPDO13 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_0.GTXE2_CHANNEL_DRPDO6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_1.GTXE2_CHANNEL_DRPDO14 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_0.GTXE2_CHANNEL_DRPDO7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_1.GTXE2_CHANNEL_DRPDO15 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_0.GTXE2_CHANNEL_DRPRDY always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_10.GTXE2_CHANNEL_EYESCANDATAERROR always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_2.GTXE2_CHANNEL_GTREFCLKMONITOR always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLK_2.GTXE2_CHANNEL_GTRXOUTCLK_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLK_2.GTXE2_CHANNEL_GTTXOUTCLK_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTNORTHREFCLK0.GTXE2_CHANNEL_NORTHREFCLK0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTNORTHREFCLK1.GTXE2_CHANNEL_NORTHREFCLK1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_0.GTXE2_CHANNEL_PCSRSVDOUT0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_1.GTXE2_CHANNEL_PCSRSVDOUT1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_2.GTXE2_CHANNEL_PCSRSVDOUT2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_3.GTXE2_CHANNEL_PCSRSVDOUT3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_4.GTXE2_CHANNEL_PCSRSVDOUT4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_5.GTXE2_CHANNEL_PCSRSVDOUT5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_6.GTXE2_CHANNEL_PCSRSVDOUT6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_7.GTXE2_CHANNEL_PCSRSVDOUT7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_8.GTXE2_CHANNEL_PCSRSVDOUT8 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_9.GTXE2_CHANNEL_PCSRSVDOUT9 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B13_10.GTXE2_CHANNEL_PCSRSVDOUT10 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_0.GTXE2_CHANNEL_PCSRSVDOUT11 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_1.GTXE2_CHANNEL_PCSRSVDOUT12 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B9_2.GTXE2_CHANNEL_PCSRSVDOUT13 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_0.GTXE2_CHANNEL_PCSRSVDOUT14 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_1.GTXE2_CHANNEL_PCSRSVDOUT15 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B10_9.GTXE2_CHANNEL_PHYSTATUS always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTQPLLCLK.GTXE2_CHANNEL_QPLLCLK always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTQPLLREFCLK.GTXE2_CHANNEL_QPLLREFCLK always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTREFCLK0.GTXE2_CHANNEL_REFCLK0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTREFCLK1.GTXE2_CHANNEL_REFCLK1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_10.GTXE2_CHANNEL_RXBUFSTATUS0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B19_10.GTXE2_CHANNEL_RXBUFSTATUS1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_10.GTXE2_CHANNEL_RXBUFSTATUS2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_10.GTXE2_CHANNEL_RXBYTEISALIGNED always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B10_10.GTXE2_CHANNEL_RXBYTEREALIGN always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_5.GTXE2_CHANNEL_RXCDRLOCK always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B10_8.GTXE2_CHANNEL_RXCHANBONDSEQ always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_9.GTXE2_CHANNEL_RXCHANISALIGNED always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_9.GTXE2_CHANNEL_RXCHANREALIGN always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_9.GTXE2_CHANNEL_RXCHARISCOMMA0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_7.GTXE2_CHANNEL_RXCHARISCOMMA1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_5.GTXE2_CHANNEL_RXCHARISCOMMA2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_3.GTXE2_CHANNEL_RXCHARISCOMMA3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_10.GTXE2_CHANNEL_RXCHARISCOMMA4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_8.GTXE2_CHANNEL_RXCHARISCOMMA5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_6.GTXE2_CHANNEL_RXCHARISCOMMA6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_4.GTXE2_CHANNEL_RXCHARISCOMMA7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_10.GTXE2_CHANNEL_RXCHARISK0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_8.GTXE2_CHANNEL_RXCHARISK1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_6.GTXE2_CHANNEL_RXCHARISK2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_4.GTXE2_CHANNEL_RXCHARISK3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_9.GTXE2_CHANNEL_RXCHARISK4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_7.GTXE2_CHANNEL_RXCHARISK5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_5.GTXE2_CHANNEL_RXCHARISK6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B12_3.GTXE2_CHANNEL_RXCHARISK7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_10.GTXE2_CHANNEL_RXCHBONDO0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_9.GTXE2_CHANNEL_RXCHBONDO1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_8.GTXE2_CHANNEL_RXCHBONDO2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_7.GTXE2_CHANNEL_RXCHBONDO3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_6.GTXE2_CHANNEL_RXCHBONDO4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_5.GTXE2_CHANNEL_RXCLKCORCNT0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_5.GTXE2_CHANNEL_RXCLKCORCNT1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_7.GTXE2_CHANNEL_RXCOMINITDET always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B19_7.GTXE2_CHANNEL_RXCOMMADET always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_7.GTXE2_CHANNEL_RXCOMSASDET always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B19_9.GTXE2_CHANNEL_RXCOMWAKEDET always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_10.GTXE2_CHANNEL_RXDATA0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_8.GTXE2_CHANNEL_RXDATA8 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_6.GTXE2_CHANNEL_RXDATA16 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_4.GTXE2_CHANNEL_RXDATA24 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_9.GTXE2_CHANNEL_RXDATA36 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_7.GTXE2_CHANNEL_RXDATA44 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_5.GTXE2_CHANNEL_RXDATA52 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_3.GTXE2_CHANNEL_RXDATA60 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_10.GTXE2_CHANNEL_RXDATA1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_8.GTXE2_CHANNEL_RXDATA9 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_6.GTXE2_CHANNEL_RXDATA17 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_4.GTXE2_CHANNEL_RXDATA25 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_9.GTXE2_CHANNEL_RXDATA37 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_7.GTXE2_CHANNEL_RXDATA45 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_5.GTXE2_CHANNEL_RXDATA53 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_3.GTXE2_CHANNEL_RXDATA61 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_10.GTXE2_CHANNEL_RXDATA2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_8.GTXE2_CHANNEL_RXDATA10 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_6.GTXE2_CHANNEL_RXDATA18 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_4.GTXE2_CHANNEL_RXDATA26 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_9.GTXE2_CHANNEL_RXDATA38 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_7.GTXE2_CHANNEL_RXDATA46 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_5.GTXE2_CHANNEL_RXDATA54 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_3.GTXE2_CHANNEL_RXDATA62 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_10.GTXE2_CHANNEL_RXDATA3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_8.GTXE2_CHANNEL_RXDATA11 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_6.GTXE2_CHANNEL_RXDATA19 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_4.GTXE2_CHANNEL_RXDATA27 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_9.GTXE2_CHANNEL_RXDATA39 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_7.GTXE2_CHANNEL_RXDATA47 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_5.GTXE2_CHANNEL_RXDATA55 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_3.GTXE2_CHANNEL_RXDATA63 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_9.GTXE2_CHANNEL_RXDATA4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_7.GTXE2_CHANNEL_RXDATA12 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_5.GTXE2_CHANNEL_RXDATA20 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_3.GTXE2_CHANNEL_RXDATA28 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_10.GTXE2_CHANNEL_RXDATA32 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_8.GTXE2_CHANNEL_RXDATA40 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_6.GTXE2_CHANNEL_RXDATA48 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_4.GTXE2_CHANNEL_RXDATA56 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_9.GTXE2_CHANNEL_RXDATA5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_7.GTXE2_CHANNEL_RXDATA13 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_5.GTXE2_CHANNEL_RXDATA21 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_3.GTXE2_CHANNEL_RXDATA29 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_10.GTXE2_CHANNEL_RXDATA33 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_8.GTXE2_CHANNEL_RXDATA41 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_6.GTXE2_CHANNEL_RXDATA49 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_4.GTXE2_CHANNEL_RXDATA57 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_9.GTXE2_CHANNEL_RXDATA6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_7.GTXE2_CHANNEL_RXDATA14 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_5.GTXE2_CHANNEL_RXDATA22 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_3.GTXE2_CHANNEL_RXDATA30 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_10.GTXE2_CHANNEL_RXDATA34 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_8.GTXE2_CHANNEL_RXDATA42 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_6.GTXE2_CHANNEL_RXDATA50 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_4.GTXE2_CHANNEL_RXDATA58 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_9.GTXE2_CHANNEL_RXDATA7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_7.GTXE2_CHANNEL_RXDATA15 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_5.GTXE2_CHANNEL_RXDATA23 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_3.GTXE2_CHANNEL_RXDATA31 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_10.GTXE2_CHANNEL_RXDATA35 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_8.GTXE2_CHANNEL_RXDATA43 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_6.GTXE2_CHANNEL_RXDATA51 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_4.GTXE2_CHANNEL_RXDATA59 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B19_5.GTXE2_CHANNEL_RXDATAVALID always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_10.GTXE2_CHANNEL_RXDISPERR0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_8.GTXE2_CHANNEL_RXDISPERR1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_6.GTXE2_CHANNEL_RXDISPERR2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_4.GTXE2_CHANNEL_RXDISPERR3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_9.GTXE2_CHANNEL_RXDISPERR4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_7.GTXE2_CHANNEL_RXDISPERR5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_5.GTXE2_CHANNEL_RXDISPERR6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_3.GTXE2_CHANNEL_RXDISPERR7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B22_1.GTXE2_CHANNEL_RXDLYSRESETDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B19_8.GTXE2_CHANNEL_RXELECIDLE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B19_6.GTXE2_CHANNEL_RXHEADER0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_6.GTXE2_CHANNEL_RXHEADER1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_6.GTXE2_CHANNEL_RXHEADER2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_7.GTXE2_CHANNEL_RXHEADERVALID always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_10.GTXE2_CHANNEL_RXMONITOROUT0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_9.GTXE2_CHANNEL_RXMONITOROUT1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_8.GTXE2_CHANNEL_RXMONITOROUT2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_7.GTXE2_CHANNEL_RXMONITOROUT3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_6.GTXE2_CHANNEL_RXMONITOROUT4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_5.GTXE2_CHANNEL_RXMONITOROUT5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_4.GTXE2_CHANNEL_RXMONITOROUT6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_10.GTXE2_CHANNEL_RXNOTINTABLE0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_8.GTXE2_CHANNEL_RXNOTINTABLE1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_6.GTXE2_CHANNEL_RXNOTINTABLE2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_4.GTXE2_CHANNEL_RXNOTINTABLE3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_9.GTXE2_CHANNEL_RXNOTINTABLE4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_7.GTXE2_CHANNEL_RXNOTINTABLE5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_5.GTXE2_CHANNEL_RXNOTINTABLE6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B14_3.GTXE2_CHANNEL_RXNOTINTABLE7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXN.GTXE2_CHANNEL_RXN_PAD always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_9.GTXE2_CHANNEL_RXOUTCLKFABRIC always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B21_9.GTXE2_CHANNEL_RXOUTCLKPCS always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_4.GTXE2_CHANNEL_RXPHALIGNDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B5_2.GTXE2_CHANNEL_RXPHMONITOR0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B1_2.GTXE2_CHANNEL_RXPHMONITOR1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B7_2.GTXE2_CHANNEL_RXPHMONITOR2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B3_2.GTXE2_CHANNEL_RXPHMONITOR3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B21_3.GTXE2_CHANNEL_RXPHMONITOR4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B0_2.GTXE2_CHANNEL_RXPHSLIPMONITOR0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B4_2.GTXE2_CHANNEL_RXPHSLIPMONITOR1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B2_2.GTXE2_CHANNEL_RXPHSLIPMONITOR2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B6_2.GTXE2_CHANNEL_RXPHSLIPMONITOR3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_3.GTXE2_CHANNEL_RXPHSLIPMONITOR4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_6.GTXE2_CHANNEL_RXPRBSERR always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXP.GTXE2_CHANNEL_RXP_PAD always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_1.GTXE2_CHANNEL_RXQPISENN always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B15_1.GTXE2_CHANNEL_RXQPISENP always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_5.GTXE2_CHANNEL_RXRATEDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_8.GTXE2_CHANNEL_RXRESETDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_8.GTXE2_CHANNEL_RXSTARTOFSEQ always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B21_8.GTXE2_CHANNEL_RXSTATUS0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_8.GTXE2_CHANNEL_RXSTATUS1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_8.GTXE2_CHANNEL_RXSTATUS2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_9.GTXE2_CHANNEL_RXVALID always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_0.GTXE2_CHANNEL_TSTOUT0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_1.GTXE2_CHANNEL_TSTOUT1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_2.GTXE2_CHANNEL_TSTOUT2 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_3.GTXE2_CHANNEL_TSTOUT3 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_4.GTXE2_CHANNEL_TSTOUT4 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_5.GTXE2_CHANNEL_TSTOUT5 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_6.GTXE2_CHANNEL_TSTOUT6 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_7.GTXE2_CHANNEL_TSTOUT7 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_8.GTXE2_CHANNEL_TSTOUT8 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B11_9.GTXE2_CHANNEL_TSTOUT9 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_2.GTXE2_CHANNEL_TXBUFSTATUS0 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B21_2.GTXE2_CHANNEL_TXBUFSTATUS1 always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_5.GTXE2_CHANNEL_TXCOMFINISH always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_3.GTXE2_CHANNEL_TXDLYSRESETDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_4.GTXE2_CHANNEL_TXGEARBOXREADY always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXN_PAD.GTXE2_CHANNEL_TXN always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B23_3.GTXE2_CHANNEL_TXOUTCLKFABRIC always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_4.GTXE2_CHANNEL_TXOUTCLKPCS always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXP_PAD.GTXE2_CHANNEL_TXP always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B18_3.GTXE2_CHANNEL_TXPHALIGNDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B17_0.GTXE2_CHANNEL_TXPHINITDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_3.GTXE2_CHANNEL_TXQPISENN always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B8_3.GTXE2_CHANNEL_TXQPISENP always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B20_4.GTXE2_CHANNEL_TXRATEDONE always
GTX_CHANNEL_2.GTXE2_LOGIC_OUTS_B16_4.GTXE2_CHANNEL_TXRESETDONE always
GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLLOCKDETCLK.GTXE2_CLK0_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXUSRCLK.GTXE2_CLK0_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXUSRCLK2.GTXE2_CLK0_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXUSRCLK.GTXE2_CLK0_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXUSRCLK2.GTXE2_CLK0_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPCLK.GTXE2_CLK1_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHDLYTSTCLK.GTXE2_CLK1_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CLKRSVD0.GTXE2_CLK1_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CLKRSVD1.GTXE2_CLK1_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CLKRSVD2.GTXE2_CLK1_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CLKRSVD3.GTXE2_CLK1_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTGREFCLK.GTXE2_CLK1_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLRESET.GTXE2_CTRL0_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTTXRESET.GTXE2_CTRL0_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDLYSRESET.GTXE2_CTRL0_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCDRFREQRESET.GTXE2_CTRL0_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRXRESET.GTXE2_CTRL0_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFELPMRESET.GTXE2_CTRL0_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRESETSEL.GTXE2_CTRL0_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHDLYRESET.GTXE2_CTRL1_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPMARESET.GTXE2_CTRL1_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CFGRESET.GTXE2_CTRL1_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXBUFRESET.GTXE2_CTRL1_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPMARESET.GTXE2_CTRL1_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCDRRESETRSV.GTXE2_CTRL1_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCDRRESET.GTXE2_CTRL1_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXOOBRESET.GTXE2_CTRL1_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BEN.GTXE2_IMUX0_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMAINCURSOR3.GTXE2_IMUX0_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSEQUENCE3.GTXE2_IMUX0_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN24.GTXE2_IMUX0_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN23.GTXE2_IMUX0_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN4.GTXE2_IMUX0_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN3.GTXE2_IMUX0_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXELECIDLEMODE0.GTXE2_IMUX0_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL7.GTXE2_IMUX10_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL6.GTXE2_IMUX10_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL5.GTXE2_IMUX10_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL4.GTXE2_IMUX10_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPDELECIDLEMODE.GTXE2_IMUX10_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXUSERRDY.GTXE2_IMUX10_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXBUFDIFFCTRL2.GTXE2_IMUX10_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXQPIEN.GTXE2_IMUX10_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLREFCLKSEL2.GTXE2_IMUX11_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYHOLD.GTXE2_IMUX11_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXRATE2.GTXE2_IMUX11_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEVSEN.GTXE2_IMUX11_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXLPMLFHOLD.GTXE2_IMUX11_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCOMWAKE.GTXE2_IMUX12_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXHEADER1.GTXE2_IMUX12_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHOVRDEN.GTXE2_IMUX12_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYOVRDEN.GTXE2_IMUX12_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXBUFDIFFCTRL0.GTXE2_IMUX12_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXSLIDE.GTXE2_IMUX12_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RX8B10BEN.GTXE2_IMUX12_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP3OVRDEN.GTXE2_IMUX12_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXQPISTRONGPDOWN.GTXE2_IMUX13_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXHEADER0.GTXE2_IMUX13_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXBUFDIFFCTRL1.GTXE2_IMUX13_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXOSOVRDEN.GTXE2_IMUX13_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP5OVRDEN.GTXE2_IMUX13_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPRBSCNTRESET.GTXE2_IMUX13_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLREFCLKSEL1.GTXE2_IMUX14_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYEN.GTXE2_IMUX14_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXRATE1.GTXE2_IMUX14_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPCSRESET.GTXE2_IMUX14_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCDROVRDEN.GTXE2_IMUX14_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHALIGN.GTXE2_IMUX14_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHOVRDEN.GTXE2_IMUX14_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS3.GTXE2_IMUX15_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS2.GTXE2_IMUX15_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS1.GTXE2_IMUX15_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS0.GTXE2_IMUX15_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLREFCLKSEL0.GTXE2_IMUX15_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRBSFORCEERR.GTXE2_IMUX15_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXRATE0.GTXE2_IMUX15_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA28.GTXE2_IMUX16_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA56.GTXE2_IMUX16_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA20.GTXE2_IMUX16_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA48.GTXE2_IMUX16_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA12.GTXE2_IMUX16_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA40.GTXE2_IMUX16_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA4.GTXE2_IMUX16_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA35.GTXE2_IMUX16_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFECM1EN.GTXE2_IMUX16_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA29.GTXE2_IMUX17_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA57.GTXE2_IMUX17_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA21.GTXE2_IMUX17_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA49.GTXE2_IMUX17_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA13.GTXE2_IMUX17_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA41.GTXE2_IMUX17_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA5.GTXE2_IMUX17_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA34.GTXE2_IMUX17_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDEN.GTXE2_IMUX17_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA60.GTXE2_IMUX18_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA24.GTXE2_IMUX18_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA52.GTXE2_IMUX18_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA16.GTXE2_IMUX18_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA44.GTXE2_IMUX18_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA8.GTXE2_IMUX18_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA36.GTXE2_IMUX18_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA0.GTXE2_IMUX18_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDI0.GTXE2_IMUX18_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDLEVEL0.GTXE2_IMUX18_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA61.GTXE2_IMUX19_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA25.GTXE2_IMUX19_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA53.GTXE2_IMUX19_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA17.GTXE2_IMUX19_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA45.GTXE2_IMUX19_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA9.GTXE2_IMUX19_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA37.GTXE2_IMUX19_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA1.GTXE2_IMUX19_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEVPHOLD.GTXE2_IMUX19_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDI1.GTXE2_IMUX19_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDLEVEL1.GTXE2_IMUX19_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITORSEL1.GTXE2_IMUX1_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMAINCURSOR2.GTXE2_IMUX1_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMAINCURSOR6.GTXE2_IMUX1_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSEQUENCE2.GTXE2_IMUX1_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSEQUENCE6.GTXE2_IMUX1_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN22.GTXE2_IMUX1_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN2.GTXE2_IMUX1_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLKSEL2.GTXE2_IMUX1_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXELECIDLEMODE1.GTXE2_IMUX1_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA30.GTXE2_IMUX20_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA58.GTXE2_IMUX20_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA22.GTXE2_IMUX20_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA50.GTXE2_IMUX20_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA14.GTXE2_IMUX20_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA42.GTXE2_IMUX20_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA6.GTXE2_IMUX20_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA33.GTXE2_IMUX20_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA31.GTXE2_IMUX21_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA59.GTXE2_IMUX21_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA23.GTXE2_IMUX21_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA51.GTXE2_IMUX21_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA15.GTXE2_IMUX21_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA43.GTXE2_IMUX21_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA7.GTXE2_IMUX21_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA32.GTXE2_IMUX21_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEXYDOVRDEN.GTXE2_IMUX21_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP4OVRDEN.GTXE2_IMUX21_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEAGCOVRDEN.GTXE2_IMUX21_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA62.GTXE2_IMUX22_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA26.GTXE2_IMUX22_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA54.GTXE2_IMUX22_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA18.GTXE2_IMUX22_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA46.GTXE2_IMUX22_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA10.GTXE2_IMUX22_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA38.GTXE2_IMUX22_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA2.GTXE2_IMUX22_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPRBSSEL0.GTXE2_IMUX22_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDI2.GTXE2_IMUX22_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDLEVEL2.GTXE2_IMUX22_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA63.GTXE2_IMUX23_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA27.GTXE2_IMUX23_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA55.GTXE2_IMUX23_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA19.GTXE2_IMUX23_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA47.GTXE2_IMUX23_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA11.GTXE2_IMUX23_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA39.GTXE2_IMUX23_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDATA3.GTXE2_IMUX23_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPRBSSEL2.GTXE2_IMUX23_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDI3.GTXE2_IMUX23_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDI4.GTXE2_IMUX23_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN10.GTXE2_IMUX24_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN11.GTXE2_IMUX24_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN12.GTXE2_IMUX24_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN13.GTXE2_IMUX24_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN14.GTXE2_IMUX24_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN15.GTXE2_IMUX24_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN16.GTXE2_IMUX24_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN17.GTXE2_IMUX24_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN18.GTXE2_IMUX24_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN19.GTXE2_IMUX24_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHALIGN.GTXE2_IMUX25_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN0.GTXE2_IMUX25_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN1.GTXE2_IMUX25_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN2.GTXE2_IMUX25_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN3.GTXE2_IMUX25_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN4.GTXE2_IMUX25_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN5.GTXE2_IMUX25_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN6.GTXE2_IMUX25_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN7.GTXE2_IMUX25_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD8.GTXE2_IMUX26_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD9.GTXE2_IMUX26_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD10.GTXE2_IMUX26_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD11.GTXE2_IMUX26_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD12.GTXE2_IMUX26_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD13.GTXE2_IMUX26_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD14.GTXE2_IMUX26_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD15.GTXE2_IMUX26_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHINIT.GTXE2_IMUX27_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPOLARITY.GTXE2_IMUX27_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEVPOVRDEN.GTXE2_IMUX27_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFELFOVRDEN.GTXE2_IMUX27_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXLPMHFOVRDEN.GTXE2_IMUX27_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCOMSAS.GTXE2_IMUX28_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLLOCKEN.GTXE2_IMUX28_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPWE.GTXE2_IMUX28_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSYSCLKSEL1.GTXE2_IMUX28_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSYSCLKSEL0.GTXE2_IMUX28_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDLYEN.GTXE2_IMUX28_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPD1.GTXE2_IMUX28_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP2OVRDEN.GTXE2_IMUX28_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE3.GTXE2_IMUX29_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE2.GTXE2_IMUX29_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE1.GTXE2_IMUX29_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE0.GTXE2_IMUX29_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK7.GTXE2_IMUX29_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK6.GTXE2_IMUX29_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK5.GTXE2_IMUX29_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK4.GTXE2_IMUX29_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXOSHOLD.GTXE2_IMUX29_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP5HOLD.GTXE2_IMUX29_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEAGCHOLD.GTXE2_IMUX29_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR8.GTXE2_IMUX2_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPOSTCURSOR3.GTXE2_IMUX2_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDIFFCTRL3.GTXE2_IMUX2_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRECURSOR3.GTXE2_IMUX2_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXGEARBOXSLIP.GTXE2_IMUX2_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXMCOMMAALIGNEN.GTXE2_IMUX2_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLKSEL2.GTXE2_IMUX2_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPOLARITY.GTXE2_IMUX30_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPCSRESET.GTXE2_IMUX30_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCDRHOLD.GTXE2_IMUX30_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDMASTER.GTXE2_IMUX30_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDSLAVE.GTXE2_IMUX30_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE7.GTXE2_IMUX31_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE6.GTXE2_IMUX31_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE5.GTXE2_IMUX31_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPMODE4.GTXE2_IMUX31_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK3.GTXE2_IMUX31_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK2.GTXE2_IMUX31_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK1.GTXE2_IMUX31_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARISK0.GTXE2_IMUX31_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_EYESCANTRIGGER.GTXE2_IMUX31_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI11.GTXE2_IMUX32_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI15.GTXE2_IMUX32_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXINHIBIT.GTXE2_IMUX32_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDLYBYPASS.GTXE2_IMUX32_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI10.GTXE2_IMUX33_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI14.GTXE2_IMUX33_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHALIGNEN.GTXE2_IMUX33_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI3.GTXE2_IMUX34_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI7.GTXE2_IMUX34_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR3.GTXE2_IMUX34_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR7.GTXE2_IMUX34_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_SETERRSTATUS.GTXE2_IMUX34_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXLPMEN.GTXE2_IMUX34_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPCOMMAALIGNEN.GTXE2_IMUX34_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN20.GTXE2_IMUX34_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI2.GTXE2_IMUX35_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI6.GTXE2_IMUX35_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR2.GTXE2_IMUX35_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR6.GTXE2_IMUX35_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMARGIN2.GTXE2_IMUX35_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDEEMPH.GTXE2_IMUX35_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPD1.GTXE2_IMUX35_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEUTOVRDEN.GTXE2_IMUX35_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFELFHOLD.GTXE2_IMUX35_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN21.GTXE2_IMUX35_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI9.GTXE2_IMUX36_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI13.GTXE2_IMUX36_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLPD.GTXE2_IMUX36_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHDLYRESET.GTXE2_IMUX36_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP3HOLD.GTXE2_IMUX36_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI8.GTXE2_IMUX37_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI12.GTXE2_IMUX37_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHDLYPD.GTXE2_IMUX37_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDIFFPD.GTXE2_IMUX37_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEXYDHOLD.GTXE2_IMUX37_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP4HOLD.GTXE2_IMUX37_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI1.GTXE2_IMUX38_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI5.GTXE2_IMUX38_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR1.GTXE2_IMUX38_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR5.GTXE2_IMUX38_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMARGIN1.GTXE2_IMUX38_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSWING.GTXE2_IMUX38_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPD0.GTXE2_IMUX38_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDLYOVRDEN.GTXE2_IMUX38_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPRBSSEL1.GTXE2_IMUX38_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN22.GTXE2_IMUX38_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI0.GTXE2_IMUX39_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDI4.GTXE2_IMUX39_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR0.GTXE2_IMUX39_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPADDR4.GTXE2_IMUX39_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMARGIN0.GTXE2_IMUX39_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDETECTRX.GTXE2_IMUX39_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXELECIDLE.GTXE2_IMUX39_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN24.GTXE2_IMUX39_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN23.GTXE2_IMUX39_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSTARTSEQ.GTXE2_IMUX3_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPOSTCURSOR2.GTXE2_IMUX3_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDIFFCTRL2.GTXE2_IMUX3_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRECURSOR2.GTXE2_IMUX3_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPD0.GTXE2_IMUX3_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRBSSEL0.GTXE2_IMUX3_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEUTHOLD.GTXE2_IMUX3_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXLPMLFKLOVRDEN.GTXE2_IMUX3_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN0.GTXE2_IMUX40_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN1.GTXE2_IMUX40_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN2.GTXE2_IMUX40_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN3.GTXE2_IMUX40_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN4.GTXE2_IMUX40_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN5.GTXE2_IMUX40_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN6.GTXE2_IMUX40_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN7.GTXE2_IMUX40_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN8.GTXE2_IMUX40_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TSTIN9.GTXE2_IMUX40_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_EYESCANMODE.GTXE2_IMUX41_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPOSTCURSORINV.GTXE2_IMUX41_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RESETOVRD.GTXE2_IMUX41_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHALIGNEN.GTXE2_IMUX41_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXSYSCLKSEL1.GTXE2_IMUX42_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD0.GTXE2_IMUX42_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD1.GTXE2_IMUX42_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD2.GTXE2_IMUX42_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD3.GTXE2_IMUX42_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD4.GTXE2_IMUX42_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD5.GTXE2_IMUX42_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD6.GTXE2_IMUX42_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_GTRSVD7.GTXE2_IMUX42_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYUPDOWN.GTXE2_IMUX43_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXRATE2.GTXE2_IMUX43_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_LOOPBACK0.GTXE2_IMUX43_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXLPMHFHOLD.GTXE2_IMUX43_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCOMINIT.GTXE2_IMUX44_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_DRPEN.GTXE2_IMUX44_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYBYPASS.GTXE2_IMUX44_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXUSERRDY.GTXE2_IMUX44_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMMADETEN.GTXE2_IMUX44_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFETAP2HOLD.GTXE2_IMUX44_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXQPIWEAKPUP.GTXE2_IMUX45_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXSYSCLKSEL0.GTXE2_IMUX45_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYSRESET.GTXE2_IMUX45_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_EYESCANRESET.GTXE2_IMUX45_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDFEXYDEN.GTXE2_IMUX45_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITORSEL0.GTXE2_IMUX45_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXRATE1.GTXE2_IMUX46_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_LOOPBACK1.GTXE2_IMUX46_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXRATE0.GTXE2_IMUX47_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_LOOPBACK2.GTXE2_IMUX47_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRECURSORINV.GTXE2_IMUX4_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMAINCURSOR1.GTXE2_IMUX4_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMAINCURSOR5.GTXE2_IMUX4_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSEQUENCE1.GTXE2_IMUX4_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSEQUENCE5.GTXE2_IMUX4_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN21.GTXE2_IMUX4_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN1.GTXE2_IMUX4_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLKSEL1.GTXE2_IMUX4_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLKSEL0.GTXE2_IMUX4_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXQPIBIASEN.GTXE2_IMUX5_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMAINCURSOR0.GTXE2_IMUX5_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXMAINCURSOR4.GTXE2_IMUX5_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSEQUENCE0.GTXE2_IMUX5_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXSEQUENCE4.GTXE2_IMUX5_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN20.GTXE2_IMUX5_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PMARSVDIN0.GTXE2_IMUX5_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLKSEL0.GTXE2_IMUX5_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLKSEL1.GTXE2_IMUX5_10 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPOSTCURSOR1.GTXE2_IMUX6_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDIFFCTRL1.GTXE2_IMUX6_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRECURSOR1.GTXE2_IMUX6_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRBSSEL1.GTXE2_IMUX6_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPISOPD.GTXE2_IMUX7_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPOSTCURSOR4.GTXE2_IMUX7_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPOSTCURSOR0.GTXE2_IMUX7_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXDIFFCTRL0.GTXE2_IMUX7_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRECURSOR0.GTXE2_IMUX7_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRECURSOR4.GTXE2_IMUX7_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXPRBSSEL2.GTXE2_IMUX7_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL3.GTXE2_IMUX8_0 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL2.GTXE2_IMUX8_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL1.GTXE2_IMUX8_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXCHARDISPVAL0.GTXE2_IMUX8_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS7.GTXE2_IMUX8_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS6.GTXE2_IMUX8_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS5.GTXE2_IMUX8_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TX8B10BBYPASS4.GTXE2_IMUX8_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXDDIEN.GTXE2_IMUX8_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHDLYPD.GTXE2_IMUX9_1 always
GTX_CHANNEL_2.GTXE2_CHANNEL_TXHEADER2.GTXE2_IMUX9_2 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN8.GTXE2_IMUX9_3 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN9.GTXE2_IMUX9_4 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN10.GTXE2_IMUX9_5 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN11.GTXE2_IMUX9_6 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN12.GTXE2_IMUX9_7 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN13.GTXE2_IMUX9_8 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN14.GTXE2_IMUX9_9 always
GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDIN15.GTXE2_IMUX9_10 always

626
virtex7/ppips_gtx_channel_3.db Normal file
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@ -0,0 +1,626 @@
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_1.GTXE2_CHANNEL_CPLLFBCLKLOST always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_1.GTXE2_CHANNEL_CPLLLOCK always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_1.GTXE2_CHANNEL_CPLLREFCLKLOST always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_10.GTXE2_CHANNEL_DMONITOROUT0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_9.GTXE2_CHANNEL_DMONITOROUT1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_8.GTXE2_CHANNEL_DMONITOROUT2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_7.GTXE2_CHANNEL_DMONITOROUT3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_6.GTXE2_CHANNEL_DMONITOROUT4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_5.GTXE2_CHANNEL_DMONITOROUT5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_4.GTXE2_CHANNEL_DMONITOROUT6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_3.GTXE2_CHANNEL_DMONITOROUT7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_0.GTXE2_CHANNEL_DRPDO0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_1.GTXE2_CHANNEL_DRPDO8 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_0.GTXE2_CHANNEL_DRPDO1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_1.GTXE2_CHANNEL_DRPDO9 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_0.GTXE2_CHANNEL_DRPDO2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_1.GTXE2_CHANNEL_DRPDO10 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_0.GTXE2_CHANNEL_DRPDO3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_1.GTXE2_CHANNEL_DRPDO11 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_0.GTXE2_CHANNEL_DRPDO4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_1.GTXE2_CHANNEL_DRPDO12 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_0.GTXE2_CHANNEL_DRPDO5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_1.GTXE2_CHANNEL_DRPDO13 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_0.GTXE2_CHANNEL_DRPDO6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_1.GTXE2_CHANNEL_DRPDO14 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_0.GTXE2_CHANNEL_DRPDO7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_1.GTXE2_CHANNEL_DRPDO15 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_0.GTXE2_CHANNEL_DRPRDY always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_10.GTXE2_CHANNEL_EYESCANDATAERROR always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_2.GTXE2_CHANNEL_GTREFCLKMONITOR always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLK_3.GTXE2_CHANNEL_GTRXOUTCLK_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLK_3.GTXE2_CHANNEL_GTTXOUTCLK_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTNORTHREFCLK0.GTXE2_CHANNEL_NORTHREFCLK0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTNORTHREFCLK1.GTXE2_CHANNEL_NORTHREFCLK1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_0.GTXE2_CHANNEL_PCSRSVDOUT0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_1.GTXE2_CHANNEL_PCSRSVDOUT1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_2.GTXE2_CHANNEL_PCSRSVDOUT2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_3.GTXE2_CHANNEL_PCSRSVDOUT3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_4.GTXE2_CHANNEL_PCSRSVDOUT4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_5.GTXE2_CHANNEL_PCSRSVDOUT5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_6.GTXE2_CHANNEL_PCSRSVDOUT6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_7.GTXE2_CHANNEL_PCSRSVDOUT7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_8.GTXE2_CHANNEL_PCSRSVDOUT8 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_9.GTXE2_CHANNEL_PCSRSVDOUT9 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B13_10.GTXE2_CHANNEL_PCSRSVDOUT10 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_0.GTXE2_CHANNEL_PCSRSVDOUT11 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_1.GTXE2_CHANNEL_PCSRSVDOUT12 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B9_2.GTXE2_CHANNEL_PCSRSVDOUT13 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_0.GTXE2_CHANNEL_PCSRSVDOUT14 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_1.GTXE2_CHANNEL_PCSRSVDOUT15 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B10_9.GTXE2_CHANNEL_PHYSTATUS always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTQPLLCLK.GTXE2_CHANNEL_QPLLCLK always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTQPLLREFCLK.GTXE2_CHANNEL_QPLLREFCLK always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTREFCLK0.GTXE2_CHANNEL_REFCLK0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTREFCLK1.GTXE2_CHANNEL_REFCLK1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_10.GTXE2_CHANNEL_RXBUFSTATUS0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B19_10.GTXE2_CHANNEL_RXBUFSTATUS1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_10.GTXE2_CHANNEL_RXBUFSTATUS2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_10.GTXE2_CHANNEL_RXBYTEISALIGNED always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B10_10.GTXE2_CHANNEL_RXBYTEREALIGN always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_5.GTXE2_CHANNEL_RXCDRLOCK always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B10_8.GTXE2_CHANNEL_RXCHANBONDSEQ always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_9.GTXE2_CHANNEL_RXCHANISALIGNED always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_9.GTXE2_CHANNEL_RXCHANREALIGN always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_9.GTXE2_CHANNEL_RXCHARISCOMMA0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_7.GTXE2_CHANNEL_RXCHARISCOMMA1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_5.GTXE2_CHANNEL_RXCHARISCOMMA2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_3.GTXE2_CHANNEL_RXCHARISCOMMA3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_10.GTXE2_CHANNEL_RXCHARISCOMMA4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_8.GTXE2_CHANNEL_RXCHARISCOMMA5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_6.GTXE2_CHANNEL_RXCHARISCOMMA6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_4.GTXE2_CHANNEL_RXCHARISCOMMA7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_10.GTXE2_CHANNEL_RXCHARISK0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_8.GTXE2_CHANNEL_RXCHARISK1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_6.GTXE2_CHANNEL_RXCHARISK2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_4.GTXE2_CHANNEL_RXCHARISK3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_9.GTXE2_CHANNEL_RXCHARISK4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_7.GTXE2_CHANNEL_RXCHARISK5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_5.GTXE2_CHANNEL_RXCHARISK6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B12_3.GTXE2_CHANNEL_RXCHARISK7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_10.GTXE2_CHANNEL_RXCHBONDO0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_9.GTXE2_CHANNEL_RXCHBONDO1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_8.GTXE2_CHANNEL_RXCHBONDO2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_7.GTXE2_CHANNEL_RXCHBONDO3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_6.GTXE2_CHANNEL_RXCHBONDO4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_5.GTXE2_CHANNEL_RXCLKCORCNT0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_5.GTXE2_CHANNEL_RXCLKCORCNT1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_7.GTXE2_CHANNEL_RXCOMINITDET always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B19_7.GTXE2_CHANNEL_RXCOMMADET always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_7.GTXE2_CHANNEL_RXCOMSASDET always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B19_9.GTXE2_CHANNEL_RXCOMWAKEDET always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_10.GTXE2_CHANNEL_RXDATA0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_8.GTXE2_CHANNEL_RXDATA8 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_6.GTXE2_CHANNEL_RXDATA16 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_4.GTXE2_CHANNEL_RXDATA24 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_9.GTXE2_CHANNEL_RXDATA36 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_7.GTXE2_CHANNEL_RXDATA44 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_5.GTXE2_CHANNEL_RXDATA52 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_3.GTXE2_CHANNEL_RXDATA60 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_10.GTXE2_CHANNEL_RXDATA1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_8.GTXE2_CHANNEL_RXDATA9 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_6.GTXE2_CHANNEL_RXDATA17 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_4.GTXE2_CHANNEL_RXDATA25 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_9.GTXE2_CHANNEL_RXDATA37 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_7.GTXE2_CHANNEL_RXDATA45 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_5.GTXE2_CHANNEL_RXDATA53 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_3.GTXE2_CHANNEL_RXDATA61 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_10.GTXE2_CHANNEL_RXDATA2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_8.GTXE2_CHANNEL_RXDATA10 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_6.GTXE2_CHANNEL_RXDATA18 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_4.GTXE2_CHANNEL_RXDATA26 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_9.GTXE2_CHANNEL_RXDATA38 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_7.GTXE2_CHANNEL_RXDATA46 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_5.GTXE2_CHANNEL_RXDATA54 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_3.GTXE2_CHANNEL_RXDATA62 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_10.GTXE2_CHANNEL_RXDATA3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_8.GTXE2_CHANNEL_RXDATA11 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_6.GTXE2_CHANNEL_RXDATA19 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_4.GTXE2_CHANNEL_RXDATA27 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_9.GTXE2_CHANNEL_RXDATA39 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_7.GTXE2_CHANNEL_RXDATA47 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_5.GTXE2_CHANNEL_RXDATA55 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_3.GTXE2_CHANNEL_RXDATA63 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_9.GTXE2_CHANNEL_RXDATA4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_7.GTXE2_CHANNEL_RXDATA12 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_5.GTXE2_CHANNEL_RXDATA20 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_3.GTXE2_CHANNEL_RXDATA28 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_10.GTXE2_CHANNEL_RXDATA32 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_8.GTXE2_CHANNEL_RXDATA40 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_6.GTXE2_CHANNEL_RXDATA48 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_4.GTXE2_CHANNEL_RXDATA56 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_9.GTXE2_CHANNEL_RXDATA5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_7.GTXE2_CHANNEL_RXDATA13 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_5.GTXE2_CHANNEL_RXDATA21 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_3.GTXE2_CHANNEL_RXDATA29 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_10.GTXE2_CHANNEL_RXDATA33 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_8.GTXE2_CHANNEL_RXDATA41 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_6.GTXE2_CHANNEL_RXDATA49 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_4.GTXE2_CHANNEL_RXDATA57 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_9.GTXE2_CHANNEL_RXDATA6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_7.GTXE2_CHANNEL_RXDATA14 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_5.GTXE2_CHANNEL_RXDATA22 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_3.GTXE2_CHANNEL_RXDATA30 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_10.GTXE2_CHANNEL_RXDATA34 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_8.GTXE2_CHANNEL_RXDATA42 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_6.GTXE2_CHANNEL_RXDATA50 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_4.GTXE2_CHANNEL_RXDATA58 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_9.GTXE2_CHANNEL_RXDATA7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_7.GTXE2_CHANNEL_RXDATA15 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_5.GTXE2_CHANNEL_RXDATA23 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_3.GTXE2_CHANNEL_RXDATA31 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_10.GTXE2_CHANNEL_RXDATA35 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_8.GTXE2_CHANNEL_RXDATA43 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_6.GTXE2_CHANNEL_RXDATA51 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_4.GTXE2_CHANNEL_RXDATA59 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B19_5.GTXE2_CHANNEL_RXDATAVALID always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_10.GTXE2_CHANNEL_RXDISPERR0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_8.GTXE2_CHANNEL_RXDISPERR1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_6.GTXE2_CHANNEL_RXDISPERR2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_4.GTXE2_CHANNEL_RXDISPERR3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_9.GTXE2_CHANNEL_RXDISPERR4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_7.GTXE2_CHANNEL_RXDISPERR5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_5.GTXE2_CHANNEL_RXDISPERR6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_3.GTXE2_CHANNEL_RXDISPERR7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B22_1.GTXE2_CHANNEL_RXDLYSRESETDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B19_8.GTXE2_CHANNEL_RXELECIDLE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B19_6.GTXE2_CHANNEL_RXHEADER0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_6.GTXE2_CHANNEL_RXHEADER1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_6.GTXE2_CHANNEL_RXHEADER2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_7.GTXE2_CHANNEL_RXHEADERVALID always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_10.GTXE2_CHANNEL_RXMONITOROUT0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_9.GTXE2_CHANNEL_RXMONITOROUT1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_8.GTXE2_CHANNEL_RXMONITOROUT2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_7.GTXE2_CHANNEL_RXMONITOROUT3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_6.GTXE2_CHANNEL_RXMONITOROUT4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_5.GTXE2_CHANNEL_RXMONITOROUT5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_4.GTXE2_CHANNEL_RXMONITOROUT6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_10.GTXE2_CHANNEL_RXNOTINTABLE0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_8.GTXE2_CHANNEL_RXNOTINTABLE1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_6.GTXE2_CHANNEL_RXNOTINTABLE2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_4.GTXE2_CHANNEL_RXNOTINTABLE3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_9.GTXE2_CHANNEL_RXNOTINTABLE4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_7.GTXE2_CHANNEL_RXNOTINTABLE5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_5.GTXE2_CHANNEL_RXNOTINTABLE6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B14_3.GTXE2_CHANNEL_RXNOTINTABLE7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXN.GTXE2_CHANNEL_RXN_PAD always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_9.GTXE2_CHANNEL_RXOUTCLKFABRIC always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B21_9.GTXE2_CHANNEL_RXOUTCLKPCS always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_4.GTXE2_CHANNEL_RXPHALIGNDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B5_2.GTXE2_CHANNEL_RXPHMONITOR0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B1_2.GTXE2_CHANNEL_RXPHMONITOR1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B7_2.GTXE2_CHANNEL_RXPHMONITOR2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B3_2.GTXE2_CHANNEL_RXPHMONITOR3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B21_3.GTXE2_CHANNEL_RXPHMONITOR4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B0_2.GTXE2_CHANNEL_RXPHSLIPMONITOR0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B4_2.GTXE2_CHANNEL_RXPHSLIPMONITOR1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B2_2.GTXE2_CHANNEL_RXPHSLIPMONITOR2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B6_2.GTXE2_CHANNEL_RXPHSLIPMONITOR3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_3.GTXE2_CHANNEL_RXPHSLIPMONITOR4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_6.GTXE2_CHANNEL_RXPRBSERR always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXP.GTXE2_CHANNEL_RXP_PAD always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_1.GTXE2_CHANNEL_RXQPISENN always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B15_1.GTXE2_CHANNEL_RXQPISENP always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_5.GTXE2_CHANNEL_RXRATEDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_8.GTXE2_CHANNEL_RXRESETDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_8.GTXE2_CHANNEL_RXSTARTOFSEQ always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B21_8.GTXE2_CHANNEL_RXSTATUS0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_8.GTXE2_CHANNEL_RXSTATUS1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_8.GTXE2_CHANNEL_RXSTATUS2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_9.GTXE2_CHANNEL_RXVALID always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_0.GTXE2_CHANNEL_TSTOUT0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_1.GTXE2_CHANNEL_TSTOUT1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_2.GTXE2_CHANNEL_TSTOUT2 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_3.GTXE2_CHANNEL_TSTOUT3 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_4.GTXE2_CHANNEL_TSTOUT4 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_5.GTXE2_CHANNEL_TSTOUT5 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_6.GTXE2_CHANNEL_TSTOUT6 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_7.GTXE2_CHANNEL_TSTOUT7 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_8.GTXE2_CHANNEL_TSTOUT8 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B11_9.GTXE2_CHANNEL_TSTOUT9 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_2.GTXE2_CHANNEL_TXBUFSTATUS0 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B21_2.GTXE2_CHANNEL_TXBUFSTATUS1 always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_5.GTXE2_CHANNEL_TXCOMFINISH always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_3.GTXE2_CHANNEL_TXDLYSRESETDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_4.GTXE2_CHANNEL_TXGEARBOXREADY always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXN_PAD.GTXE2_CHANNEL_TXN always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B23_3.GTXE2_CHANNEL_TXOUTCLKFABRIC always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_4.GTXE2_CHANNEL_TXOUTCLKPCS always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXP_PAD.GTXE2_CHANNEL_TXP always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B18_3.GTXE2_CHANNEL_TXPHALIGNDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B17_0.GTXE2_CHANNEL_TXPHINITDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_3.GTXE2_CHANNEL_TXQPISENN always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B8_3.GTXE2_CHANNEL_TXQPISENP always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B20_4.GTXE2_CHANNEL_TXRATEDONE always
GTX_CHANNEL_3.GTXE2_LOGIC_OUTS_B16_4.GTXE2_CHANNEL_TXRESETDONE always
GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLLOCKDETCLK.GTXE2_CLK0_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXUSRCLK.GTXE2_CLK0_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXUSRCLK2.GTXE2_CLK0_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXUSRCLK.GTXE2_CLK0_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXUSRCLK2.GTXE2_CLK0_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPCLK.GTXE2_CLK1_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHDLYTSTCLK.GTXE2_CLK1_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CLKRSVD0.GTXE2_CLK1_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CLKRSVD1.GTXE2_CLK1_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CLKRSVD2.GTXE2_CLK1_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CLKRSVD3.GTXE2_CLK1_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTGREFCLK.GTXE2_CLK1_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLRESET.GTXE2_CTRL0_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTTXRESET.GTXE2_CTRL0_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDLYSRESET.GTXE2_CTRL0_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCDRFREQRESET.GTXE2_CTRL0_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRXRESET.GTXE2_CTRL0_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFELPMRESET.GTXE2_CTRL0_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRESETSEL.GTXE2_CTRL0_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHDLYRESET.GTXE2_CTRL1_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPMARESET.GTXE2_CTRL1_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CFGRESET.GTXE2_CTRL1_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXBUFRESET.GTXE2_CTRL1_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPMARESET.GTXE2_CTRL1_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCDRRESETRSV.GTXE2_CTRL1_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCDRRESET.GTXE2_CTRL1_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXOOBRESET.GTXE2_CTRL1_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BEN.GTXE2_IMUX0_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMAINCURSOR3.GTXE2_IMUX0_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSEQUENCE3.GTXE2_IMUX0_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN24.GTXE2_IMUX0_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN23.GTXE2_IMUX0_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN4.GTXE2_IMUX0_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN3.GTXE2_IMUX0_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXELECIDLEMODE0.GTXE2_IMUX0_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL7.GTXE2_IMUX10_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL6.GTXE2_IMUX10_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL5.GTXE2_IMUX10_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL4.GTXE2_IMUX10_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPDELECIDLEMODE.GTXE2_IMUX10_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXUSERRDY.GTXE2_IMUX10_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXBUFDIFFCTRL2.GTXE2_IMUX10_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXQPIEN.GTXE2_IMUX10_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLREFCLKSEL2.GTXE2_IMUX11_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYHOLD.GTXE2_IMUX11_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXRATE2.GTXE2_IMUX11_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEVSEN.GTXE2_IMUX11_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXLPMLFHOLD.GTXE2_IMUX11_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCOMWAKE.GTXE2_IMUX12_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXHEADER1.GTXE2_IMUX12_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHOVRDEN.GTXE2_IMUX12_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYOVRDEN.GTXE2_IMUX12_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXBUFDIFFCTRL0.GTXE2_IMUX12_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXSLIDE.GTXE2_IMUX12_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RX8B10BEN.GTXE2_IMUX12_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP3OVRDEN.GTXE2_IMUX12_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXQPISTRONGPDOWN.GTXE2_IMUX13_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXHEADER0.GTXE2_IMUX13_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXBUFDIFFCTRL1.GTXE2_IMUX13_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXOSOVRDEN.GTXE2_IMUX13_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP5OVRDEN.GTXE2_IMUX13_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPRBSCNTRESET.GTXE2_IMUX13_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLREFCLKSEL1.GTXE2_IMUX14_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYEN.GTXE2_IMUX14_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXRATE1.GTXE2_IMUX14_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPCSRESET.GTXE2_IMUX14_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCDROVRDEN.GTXE2_IMUX14_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHALIGN.GTXE2_IMUX14_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHOVRDEN.GTXE2_IMUX14_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS3.GTXE2_IMUX15_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS2.GTXE2_IMUX15_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS1.GTXE2_IMUX15_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS0.GTXE2_IMUX15_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLREFCLKSEL0.GTXE2_IMUX15_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRBSFORCEERR.GTXE2_IMUX15_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXRATE0.GTXE2_IMUX15_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA28.GTXE2_IMUX16_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA56.GTXE2_IMUX16_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA20.GTXE2_IMUX16_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA48.GTXE2_IMUX16_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA12.GTXE2_IMUX16_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA40.GTXE2_IMUX16_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA4.GTXE2_IMUX16_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA35.GTXE2_IMUX16_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFECM1EN.GTXE2_IMUX16_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA29.GTXE2_IMUX17_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA57.GTXE2_IMUX17_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA21.GTXE2_IMUX17_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA49.GTXE2_IMUX17_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA13.GTXE2_IMUX17_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA41.GTXE2_IMUX17_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA5.GTXE2_IMUX17_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA34.GTXE2_IMUX17_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDEN.GTXE2_IMUX17_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA60.GTXE2_IMUX18_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA24.GTXE2_IMUX18_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA52.GTXE2_IMUX18_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA16.GTXE2_IMUX18_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA44.GTXE2_IMUX18_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA8.GTXE2_IMUX18_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA36.GTXE2_IMUX18_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA0.GTXE2_IMUX18_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDI0.GTXE2_IMUX18_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDLEVEL0.GTXE2_IMUX18_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA61.GTXE2_IMUX19_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA25.GTXE2_IMUX19_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA53.GTXE2_IMUX19_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA17.GTXE2_IMUX19_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA45.GTXE2_IMUX19_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA9.GTXE2_IMUX19_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA37.GTXE2_IMUX19_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA1.GTXE2_IMUX19_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEVPHOLD.GTXE2_IMUX19_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDI1.GTXE2_IMUX19_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDLEVEL1.GTXE2_IMUX19_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITORSEL1.GTXE2_IMUX1_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMAINCURSOR2.GTXE2_IMUX1_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMAINCURSOR6.GTXE2_IMUX1_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSEQUENCE2.GTXE2_IMUX1_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSEQUENCE6.GTXE2_IMUX1_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN22.GTXE2_IMUX1_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN2.GTXE2_IMUX1_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLKSEL2.GTXE2_IMUX1_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXELECIDLEMODE1.GTXE2_IMUX1_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA30.GTXE2_IMUX20_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA58.GTXE2_IMUX20_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA22.GTXE2_IMUX20_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA50.GTXE2_IMUX20_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA14.GTXE2_IMUX20_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA42.GTXE2_IMUX20_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA6.GTXE2_IMUX20_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA33.GTXE2_IMUX20_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA31.GTXE2_IMUX21_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA59.GTXE2_IMUX21_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA23.GTXE2_IMUX21_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA51.GTXE2_IMUX21_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA15.GTXE2_IMUX21_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA43.GTXE2_IMUX21_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA7.GTXE2_IMUX21_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA32.GTXE2_IMUX21_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEXYDOVRDEN.GTXE2_IMUX21_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP4OVRDEN.GTXE2_IMUX21_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEAGCOVRDEN.GTXE2_IMUX21_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA62.GTXE2_IMUX22_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA26.GTXE2_IMUX22_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA54.GTXE2_IMUX22_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA18.GTXE2_IMUX22_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA46.GTXE2_IMUX22_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA10.GTXE2_IMUX22_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA38.GTXE2_IMUX22_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA2.GTXE2_IMUX22_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPRBSSEL0.GTXE2_IMUX22_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDI2.GTXE2_IMUX22_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDLEVEL2.GTXE2_IMUX22_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA63.GTXE2_IMUX23_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA27.GTXE2_IMUX23_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA55.GTXE2_IMUX23_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA19.GTXE2_IMUX23_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA47.GTXE2_IMUX23_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA11.GTXE2_IMUX23_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA39.GTXE2_IMUX23_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDATA3.GTXE2_IMUX23_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPRBSSEL2.GTXE2_IMUX23_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDI3.GTXE2_IMUX23_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDI4.GTXE2_IMUX23_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN10.GTXE2_IMUX24_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN11.GTXE2_IMUX24_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN12.GTXE2_IMUX24_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN13.GTXE2_IMUX24_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN14.GTXE2_IMUX24_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN15.GTXE2_IMUX24_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN16.GTXE2_IMUX24_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN17.GTXE2_IMUX24_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN18.GTXE2_IMUX24_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN19.GTXE2_IMUX24_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHALIGN.GTXE2_IMUX25_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN0.GTXE2_IMUX25_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN1.GTXE2_IMUX25_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN2.GTXE2_IMUX25_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN3.GTXE2_IMUX25_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN4.GTXE2_IMUX25_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN5.GTXE2_IMUX25_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN6.GTXE2_IMUX25_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN7.GTXE2_IMUX25_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD8.GTXE2_IMUX26_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD9.GTXE2_IMUX26_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD10.GTXE2_IMUX26_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD11.GTXE2_IMUX26_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD12.GTXE2_IMUX26_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD13.GTXE2_IMUX26_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD14.GTXE2_IMUX26_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD15.GTXE2_IMUX26_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHINIT.GTXE2_IMUX27_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPOLARITY.GTXE2_IMUX27_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEVPOVRDEN.GTXE2_IMUX27_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFELFOVRDEN.GTXE2_IMUX27_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXLPMHFOVRDEN.GTXE2_IMUX27_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCOMSAS.GTXE2_IMUX28_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLLOCKEN.GTXE2_IMUX28_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPWE.GTXE2_IMUX28_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSYSCLKSEL1.GTXE2_IMUX28_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSYSCLKSEL0.GTXE2_IMUX28_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDLYEN.GTXE2_IMUX28_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPD1.GTXE2_IMUX28_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP2OVRDEN.GTXE2_IMUX28_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE3.GTXE2_IMUX29_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE2.GTXE2_IMUX29_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE1.GTXE2_IMUX29_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE0.GTXE2_IMUX29_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK7.GTXE2_IMUX29_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK6.GTXE2_IMUX29_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK5.GTXE2_IMUX29_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK4.GTXE2_IMUX29_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXOSHOLD.GTXE2_IMUX29_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP5HOLD.GTXE2_IMUX29_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEAGCHOLD.GTXE2_IMUX29_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR8.GTXE2_IMUX2_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPOSTCURSOR3.GTXE2_IMUX2_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDIFFCTRL3.GTXE2_IMUX2_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRECURSOR3.GTXE2_IMUX2_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXGEARBOXSLIP.GTXE2_IMUX2_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXMCOMMAALIGNEN.GTXE2_IMUX2_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLKSEL2.GTXE2_IMUX2_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPOLARITY.GTXE2_IMUX30_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPCSRESET.GTXE2_IMUX30_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCDRHOLD.GTXE2_IMUX30_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDMASTER.GTXE2_IMUX30_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDSLAVE.GTXE2_IMUX30_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE7.GTXE2_IMUX31_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE6.GTXE2_IMUX31_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE5.GTXE2_IMUX31_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPMODE4.GTXE2_IMUX31_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK3.GTXE2_IMUX31_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK2.GTXE2_IMUX31_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK1.GTXE2_IMUX31_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARISK0.GTXE2_IMUX31_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_EYESCANTRIGGER.GTXE2_IMUX31_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI11.GTXE2_IMUX32_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI15.GTXE2_IMUX32_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXINHIBIT.GTXE2_IMUX32_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDLYBYPASS.GTXE2_IMUX32_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI10.GTXE2_IMUX33_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI14.GTXE2_IMUX33_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHALIGNEN.GTXE2_IMUX33_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI3.GTXE2_IMUX34_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI7.GTXE2_IMUX34_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR3.GTXE2_IMUX34_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR7.GTXE2_IMUX34_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_SETERRSTATUS.GTXE2_IMUX34_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXLPMEN.GTXE2_IMUX34_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPCOMMAALIGNEN.GTXE2_IMUX34_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN20.GTXE2_IMUX34_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI2.GTXE2_IMUX35_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI6.GTXE2_IMUX35_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR2.GTXE2_IMUX35_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR6.GTXE2_IMUX35_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMARGIN2.GTXE2_IMUX35_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDEEMPH.GTXE2_IMUX35_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPD1.GTXE2_IMUX35_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEUTOVRDEN.GTXE2_IMUX35_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFELFHOLD.GTXE2_IMUX35_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN21.GTXE2_IMUX35_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI9.GTXE2_IMUX36_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI13.GTXE2_IMUX36_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLPD.GTXE2_IMUX36_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHDLYRESET.GTXE2_IMUX36_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP3HOLD.GTXE2_IMUX36_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI8.GTXE2_IMUX37_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI12.GTXE2_IMUX37_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHDLYPD.GTXE2_IMUX37_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDIFFPD.GTXE2_IMUX37_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEXYDHOLD.GTXE2_IMUX37_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP4HOLD.GTXE2_IMUX37_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI1.GTXE2_IMUX38_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI5.GTXE2_IMUX38_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR1.GTXE2_IMUX38_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR5.GTXE2_IMUX38_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMARGIN1.GTXE2_IMUX38_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSWING.GTXE2_IMUX38_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPD0.GTXE2_IMUX38_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDLYOVRDEN.GTXE2_IMUX38_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPRBSSEL1.GTXE2_IMUX38_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN22.GTXE2_IMUX38_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI0.GTXE2_IMUX39_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDI4.GTXE2_IMUX39_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR0.GTXE2_IMUX39_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPADDR4.GTXE2_IMUX39_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMARGIN0.GTXE2_IMUX39_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDETECTRX.GTXE2_IMUX39_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXELECIDLE.GTXE2_IMUX39_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN24.GTXE2_IMUX39_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN23.GTXE2_IMUX39_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSTARTSEQ.GTXE2_IMUX3_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPOSTCURSOR2.GTXE2_IMUX3_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDIFFCTRL2.GTXE2_IMUX3_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRECURSOR2.GTXE2_IMUX3_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPD0.GTXE2_IMUX3_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRBSSEL0.GTXE2_IMUX3_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEUTHOLD.GTXE2_IMUX3_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXLPMLFKLOVRDEN.GTXE2_IMUX3_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN0.GTXE2_IMUX40_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN1.GTXE2_IMUX40_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN2.GTXE2_IMUX40_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN3.GTXE2_IMUX40_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN4.GTXE2_IMUX40_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN5.GTXE2_IMUX40_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN6.GTXE2_IMUX40_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN7.GTXE2_IMUX40_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN8.GTXE2_IMUX40_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TSTIN9.GTXE2_IMUX40_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_EYESCANMODE.GTXE2_IMUX41_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPOSTCURSORINV.GTXE2_IMUX41_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RESETOVRD.GTXE2_IMUX41_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHALIGNEN.GTXE2_IMUX41_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXSYSCLKSEL1.GTXE2_IMUX42_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD0.GTXE2_IMUX42_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD1.GTXE2_IMUX42_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD2.GTXE2_IMUX42_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD3.GTXE2_IMUX42_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD4.GTXE2_IMUX42_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD5.GTXE2_IMUX42_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD6.GTXE2_IMUX42_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_GTRSVD7.GTXE2_IMUX42_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYUPDOWN.GTXE2_IMUX43_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXRATE2.GTXE2_IMUX43_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_LOOPBACK0.GTXE2_IMUX43_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXLPMHFHOLD.GTXE2_IMUX43_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCOMINIT.GTXE2_IMUX44_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_DRPEN.GTXE2_IMUX44_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYBYPASS.GTXE2_IMUX44_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXUSERRDY.GTXE2_IMUX44_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMMADETEN.GTXE2_IMUX44_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFETAP2HOLD.GTXE2_IMUX44_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXQPIWEAKPUP.GTXE2_IMUX45_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXSYSCLKSEL0.GTXE2_IMUX45_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYSRESET.GTXE2_IMUX45_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_EYESCANRESET.GTXE2_IMUX45_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDFEXYDEN.GTXE2_IMUX45_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITORSEL0.GTXE2_IMUX45_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXRATE1.GTXE2_IMUX46_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_LOOPBACK1.GTXE2_IMUX46_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXRATE0.GTXE2_IMUX47_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_LOOPBACK2.GTXE2_IMUX47_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRECURSORINV.GTXE2_IMUX4_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMAINCURSOR1.GTXE2_IMUX4_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMAINCURSOR5.GTXE2_IMUX4_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSEQUENCE1.GTXE2_IMUX4_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSEQUENCE5.GTXE2_IMUX4_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN21.GTXE2_IMUX4_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN1.GTXE2_IMUX4_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLKSEL1.GTXE2_IMUX4_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLKSEL0.GTXE2_IMUX4_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXQPIBIASEN.GTXE2_IMUX5_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMAINCURSOR0.GTXE2_IMUX5_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXMAINCURSOR4.GTXE2_IMUX5_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSEQUENCE0.GTXE2_IMUX5_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXSEQUENCE4.GTXE2_IMUX5_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN20.GTXE2_IMUX5_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PMARSVDIN0.GTXE2_IMUX5_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLKSEL0.GTXE2_IMUX5_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLKSEL1.GTXE2_IMUX5_10 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPOSTCURSOR1.GTXE2_IMUX6_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDIFFCTRL1.GTXE2_IMUX6_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRECURSOR1.GTXE2_IMUX6_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRBSSEL1.GTXE2_IMUX6_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPISOPD.GTXE2_IMUX7_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPOSTCURSOR4.GTXE2_IMUX7_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPOSTCURSOR0.GTXE2_IMUX7_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXDIFFCTRL0.GTXE2_IMUX7_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRECURSOR0.GTXE2_IMUX7_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRECURSOR4.GTXE2_IMUX7_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXPRBSSEL2.GTXE2_IMUX7_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL3.GTXE2_IMUX8_0 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL2.GTXE2_IMUX8_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL1.GTXE2_IMUX8_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXCHARDISPVAL0.GTXE2_IMUX8_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS7.GTXE2_IMUX8_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS6.GTXE2_IMUX8_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS5.GTXE2_IMUX8_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TX8B10BBYPASS4.GTXE2_IMUX8_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXDDIEN.GTXE2_IMUX8_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHDLYPD.GTXE2_IMUX9_1 always
GTX_CHANNEL_3.GTXE2_CHANNEL_TXHEADER2.GTXE2_IMUX9_2 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN8.GTXE2_IMUX9_3 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN9.GTXE2_IMUX9_4 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN10.GTXE2_IMUX9_5 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN11.GTXE2_IMUX9_6 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN12.GTXE2_IMUX9_7 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN13.GTXE2_IMUX9_8 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN14.GTXE2_IMUX9_9 always
GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDIN15.GTXE2_IMUX9_10 always

134
virtex7/ppips_gtx_common.db Normal file
View File

@ -0,0 +1,134 @@
GTX_COMMON.GTXE2_COMMON_DRPCLK.GTXE2_CLK1_1 always
GTX_COMMON.GTXE2_COMMON_QPLLLOCKDETCLK.GTXE2_CLK1_3 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B15_0.GTXE2_COMMON_DRPDO0 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B15_1.GTXE2_COMMON_DRPDO8 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B11_0.GTXE2_COMMON_DRPDO1 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B11_1.GTXE2_COMMON_DRPDO9 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B13_0.GTXE2_COMMON_DRPDO2 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B13_1.GTXE2_COMMON_DRPDO10 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B9_0.GTXE2_COMMON_DRPDO3 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B9_1.GTXE2_COMMON_DRPDO11 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B10_0.GTXE2_COMMON_DRPDO4 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B10_1.GTXE2_COMMON_DRPDO12 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B14_0.GTXE2_COMMON_DRPDO5 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B14_1.GTXE2_COMMON_DRPDO13 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B8_0.GTXE2_COMMON_DRPDO6 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B8_1.GTXE2_COMMON_DRPDO14 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B12_0.GTXE2_COMMON_DRPDO7 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B12_1.GTXE2_COMMON_DRPDO15 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B21_0.GTXE2_COMMON_DRPRDY always
GTX_COMMON.GTXE2_COMMON_QPLLOUTCLK.GTXE2_COMMON_GTQPLLOUTCLK always
GTX_COMMON.GTXE2_COMMON_QPLLOUTREFCLK.GTXE2_COMMON_GTQPLLOUTREFCLK always
GTX_COMMON.GTXE2_COMMON_GTNORTHREFCLK0.GTXE2_COMMON_NORTHREFCLK0 always
GTX_COMMON.GTXE2_COMMON_GTNORTHREFCLK1.GTXE2_COMMON_NORTHREFCLK1 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B19_3.GTXE2_COMMON_QPLLDMONITOR0 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B23_3.GTXE2_COMMON_QPLLDMONITOR1 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B17_3.GTXE2_COMMON_QPLLDMONITOR2 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B21_3.GTXE2_COMMON_QPLLDMONITOR3 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B22_4.GTXE2_COMMON_QPLLDMONITOR4 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B18_4.GTXE2_COMMON_QPLLDMONITOR5 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B20_4.GTXE2_COMMON_QPLLDMONITOR6 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B16_4.GTXE2_COMMON_QPLLDMONITOR7 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B19_2.GTXE2_COMMON_QPLLFBCLKLOST always
GTX_COMMON.GTXE2_LOGIC_OUTS_B14_2.GTXE2_COMMON_QPLLLOCK always
GTX_COMMON.GTXE2_LOGIC_OUTS_B10_2.GTXE2_COMMON_QPLLREFCLKLOST always
GTX_COMMON.GTXE2_COMMON_GTREFCLK0.GTXE2_COMMON_REFCLK0 always
GTX_COMMON.GTXE2_COMMON_GTREFCLK1.GTXE2_COMMON_REFCLK1 always
GTX_COMMON.GTXE2_LOGIC_OUTS_B2_3.GTXE2_COMMON_REFCLKOUTMONITOR always
GTX_COMMON.GTXE2_COMMON_MGT_CLK0.GTXE2_COMMON_RXOUTCLK_0 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK1.GTXE2_COMMON_RXOUTCLK_1 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK6.GTXE2_COMMON_RXOUTCLK_2 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK7.GTXE2_COMMON_RXOUTCLK_3 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK2.GTXE2_COMMON_TXOUTCLK_0 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK3.GTXE2_COMMON_TXOUTCLK_1 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK8.GTXE2_COMMON_TXOUTCLK_2 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK9.GTXE2_COMMON_TXOUTCLK_3 always
GTX_COMMON.GTXE2_COMMON_QPLLRESET.GTXE2_CTRL0_3 always
GTX_COMMON.GTXE2_COMMON_QPLLOUTRESET.GTXE2_CTRL1_2 always
GTX_COMMON.GTXE2_COMMON_DRPDI7.GTXE2_IMUX16_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI15.GTXE2_IMUX16_1 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD20.GTXE2_IMUX16_2 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD21.GTXE2_IMUX16_3 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD22.GTXE2_IMUX16_4 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD23.GTXE2_IMUX16_5 always
GTX_COMMON.GTXE2_COMMON_DRPDI6.GTXE2_IMUX17_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI14.GTXE2_IMUX17_1 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD24.GTXE2_IMUX17_5 always
GTX_COMMON.GTXE2_COMMON_DRPDI3.GTXE2_IMUX18_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI11.GTXE2_IMUX18_1 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD13.GTXE2_IMUX18_2 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD17.GTXE2_IMUX18_3 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD111.GTXE2_IMUX18_4 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD115.GTXE2_IMUX18_5 always
GTX_COMMON.GTXE2_COMMON_DRPDI2.GTXE2_IMUX19_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI10.GTXE2_IMUX19_1 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD12.GTXE2_IMUX19_2 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD16.GTXE2_IMUX19_3 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD110.GTXE2_IMUX19_4 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD114.GTXE2_IMUX19_5 always
GTX_COMMON.GTXE2_COMMON_DRPDI5.GTXE2_IMUX20_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI13.GTXE2_IMUX20_1 always
GTX_COMMON.GTXE2_COMMON_PMARSVD4.GTXE2_IMUX20_2 always
GTX_COMMON.GTXE2_COMMON_PMARSVD5.GTXE2_IMUX20_3 always
GTX_COMMON.GTXE2_COMMON_PMARSVD6.GTXE2_IMUX20_4 always
GTX_COMMON.GTXE2_COMMON_PMARSVD7.GTXE2_IMUX20_5 always
GTX_COMMON.GTXE2_COMMON_DRPDI4.GTXE2_IMUX21_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI12.GTXE2_IMUX21_1 always
GTX_COMMON.GTXE2_COMMON_PMARSVD0.GTXE2_IMUX21_2 always
GTX_COMMON.GTXE2_COMMON_PMARSVD1.GTXE2_IMUX21_3 always
GTX_COMMON.GTXE2_COMMON_PMARSVD2.GTXE2_IMUX21_4 always
GTX_COMMON.GTXE2_COMMON_PMARSVD3.GTXE2_IMUX21_5 always
GTX_COMMON.GTXE2_COMMON_DRPDI1.GTXE2_IMUX22_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI9.GTXE2_IMUX22_1 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD11.GTXE2_IMUX22_2 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD15.GTXE2_IMUX22_3 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD19.GTXE2_IMUX22_4 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD113.GTXE2_IMUX22_5 always
GTX_COMMON.GTXE2_COMMON_DRPDI0.GTXE2_IMUX23_0 always
GTX_COMMON.GTXE2_COMMON_DRPDI8.GTXE2_IMUX23_1 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD10.GTXE2_IMUX23_2 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD14.GTXE2_IMUX23_3 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD18.GTXE2_IMUX23_4 always
GTX_COMMON.GTXE2_COMMON_QPLLRSVD112.GTXE2_IMUX23_5 always
GTX_COMMON.GTXE2_COMMON_DRPADDR0.GTXE2_IMUX24_2 always
GTX_COMMON.GTXE2_COMMON_QPLLLOCKEN.GTXE2_IMUX24_3 always
GTX_COMMON.GTXE2_COMMON_DRPADDR1.GTXE2_IMUX25_2 always
GTX_COMMON.GTXE2_COMMON_DRPADDR4.GTXE2_IMUX26_2 always
GTX_COMMON.IBUFDS_GTE2_0_CEB.GTXE2_IMUX26_3 always
GTX_COMMON.GTXE2_COMMON_BGRCALOVRD3.GTXE2_IMUX26_4 always
GTX_COMMON.GTXE2_COMMON_BGPDB.GTXE2_IMUX26_5 always
GTX_COMMON.GTXE2_COMMON_DRPADDR5.GTXE2_IMUX27_2 always
GTX_COMMON.GTXE2_COMMON_QPLLREFCLKSEL2.GTXE2_IMUX27_3 always
GTX_COMMON.GTXE2_COMMON_BGRCALOVRD2.GTXE2_IMUX27_4 always
GTX_COMMON.GTXE2_COMMON_BGMONITORENB.GTXE2_IMUX27_5 always
GTX_COMMON.GTXE2_COMMON_DRPADDR2.GTXE2_IMUX28_2 always
GTX_COMMON.GTXE2_COMMON_QPLLPD.GTXE2_IMUX28_3 always
GTX_COMMON.GTXE2_COMMON_RCALENB.GTXE2_IMUX28_4 always
GTX_COMMON.GTXE2_COMMON_DRPWE.GTXE2_IMUX29_0 always
GTX_COMMON.GTXE2_COMMON_DRPEN.GTXE2_IMUX29_1 always
GTX_COMMON.GTXE2_COMMON_DRPADDR3.GTXE2_IMUX29_2 always
GTX_COMMON.IBUFDS_GTE2_1_CEB.GTXE2_IMUX29_3 always
GTX_COMMON.GTXE2_COMMON_BGRCALOVRD4.GTXE2_IMUX29_4 always
GTX_COMMON.GTXE2_COMMON_DRPADDR6.GTXE2_IMUX30_2 always
GTX_COMMON.GTXE2_COMMON_QPLLREFCLKSEL1.GTXE2_IMUX30_3 always
GTX_COMMON.GTXE2_COMMON_BGRCALOVRD1.GTXE2_IMUX30_4 always
GTX_COMMON.GTXE2_COMMON_BGBYPASSB.GTXE2_IMUX30_5 always
GTX_COMMON.GTXE2_COMMON_DRPADDR7.GTXE2_IMUX31_2 always
GTX_COMMON.GTXE2_COMMON_QPLLREFCLKSEL0.GTXE2_IMUX31_3 always
GTX_COMMON.GTXE2_COMMON_BGRCALOVRD0.GTXE2_IMUX31_4 always
GTX_COMMON.IBUFDS_GTE2_0_I_SEG.IBUFDS_GTE2_0_I always
GTX_COMMON.IBUFDS_GTE2_0_IB_SEG.IBUFDS_GTE2_0_IB always
GTX_COMMON.GTXE2_COMMON_MGT_CLK4.IBUFDS_GTE2_0_MGTCLKOUT always
GTX_COMMON.IBUFDS_GTE2_0_MGTCLKOUT.IBUFDS_GTE2_0_O always
GTX_COMMON.GTXE2_COMMON_REFCLK0.IBUFDS_GTE2_0_O always
GTX_COMMON.IBUFDS_GTE2_0_MGTCLKOUT.IBUFDS_GTE2_0_ODIV2 always
GTX_COMMON.IBUFDS_GTE2_1_I_SEG.IBUFDS_GTE2_1_I always
GTX_COMMON.IBUFDS_GTE2_1_IB_SEG.IBUFDS_GTE2_1_IB always
GTX_COMMON.GTXE2_COMMON_MGT_CLK5.IBUFDS_GTE2_1_MGTCLKOUT always
GTX_COMMON.IBUFDS_GTE2_1_MGTCLKOUT.IBUFDS_GTE2_1_O always
GTX_COMMON.GTXE2_COMMON_REFCLK1.IBUFDS_GTE2_1_O always
GTX_COMMON.IBUFDS_GTE2_1_MGTCLKOUT.IBUFDS_GTE2_1_ODIV2 always
GTX_COMMON.GTXE2_COMMON_MGT_CLK4.IBUFDS_GTE2_0_MGTCLKOUT always
GTX_COMMON.IBUFDS_GTE2_0_CEB.GTXE2_IMUX26_3 always
GTX_COMMON.IBUFDS_GTE2_0_MGTCLKOUT.IBUFDS_GTE2_0_O always
GTX_COMMON.IBUFDS_GTE2_Y0.IN_USE always

120
virtex7/ppips_gtx_int_interface.db Normal file
View File

@ -0,0 +1,120 @@
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY0.GTXE2_INT_INTERFACE_IMUX0 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY1.GTXE2_INT_INTERFACE_IMUX1 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY2.GTXE2_INT_INTERFACE_IMUX2 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY3.GTXE2_INT_INTERFACE_IMUX3 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY4.GTXE2_INT_INTERFACE_IMUX4 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY5.GTXE2_INT_INTERFACE_IMUX5 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY6.GTXE2_INT_INTERFACE_IMUX6 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY7.GTXE2_INT_INTERFACE_IMUX7 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY8.GTXE2_INT_INTERFACE_IMUX8 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY9.GTXE2_INT_INTERFACE_IMUX9 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY10.GTXE2_INT_INTERFACE_IMUX10 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY11.GTXE2_INT_INTERFACE_IMUX11 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY12.GTXE2_INT_INTERFACE_IMUX12 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY13.GTXE2_INT_INTERFACE_IMUX13 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY14.GTXE2_INT_INTERFACE_IMUX14 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY15.GTXE2_INT_INTERFACE_IMUX15 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY16.GTXE2_INT_INTERFACE_IMUX16 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY17.GTXE2_INT_INTERFACE_IMUX17 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY18.GTXE2_INT_INTERFACE_IMUX18 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY19.GTXE2_INT_INTERFACE_IMUX19 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY20.GTXE2_INT_INTERFACE_IMUX20 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY21.GTXE2_INT_INTERFACE_IMUX21 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY22.GTXE2_INT_INTERFACE_IMUX22 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY23.GTXE2_INT_INTERFACE_IMUX23 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY24.GTXE2_INT_INTERFACE_IMUX24 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY25.GTXE2_INT_INTERFACE_IMUX25 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY26.GTXE2_INT_INTERFACE_IMUX26 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY27.GTXE2_INT_INTERFACE_IMUX27 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY28.GTXE2_INT_INTERFACE_IMUX28 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY29.GTXE2_INT_INTERFACE_IMUX29 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY30.GTXE2_INT_INTERFACE_IMUX30 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY31.GTXE2_INT_INTERFACE_IMUX31 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY32.GTXE2_INT_INTERFACE_IMUX32 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY33.GTXE2_INT_INTERFACE_IMUX33 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY34.GTXE2_INT_INTERFACE_IMUX34 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY35.GTXE2_INT_INTERFACE_IMUX35 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY36.GTXE2_INT_INTERFACE_IMUX36 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY37.GTXE2_INT_INTERFACE_IMUX37 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY38.GTXE2_INT_INTERFACE_IMUX38 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY39.GTXE2_INT_INTERFACE_IMUX39 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY40.GTXE2_INT_INTERFACE_IMUX40 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY41.GTXE2_INT_INTERFACE_IMUX41 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY42.GTXE2_INT_INTERFACE_IMUX42 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY43.GTXE2_INT_INTERFACE_IMUX43 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY44.GTXE2_INT_INTERFACE_IMUX44 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY45.GTXE2_INT_INTERFACE_IMUX45 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY46.GTXE2_INT_INTERFACE_IMUX46 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY47.GTXE2_INT_INTERFACE_IMUX47 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT0.GTXE2_INT_INTERFACE_IMUX0 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT1.GTXE2_INT_INTERFACE_IMUX1 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT2.GTXE2_INT_INTERFACE_IMUX2 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT3.GTXE2_INT_INTERFACE_IMUX3 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT4.GTXE2_INT_INTERFACE_IMUX4 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT5.GTXE2_INT_INTERFACE_IMUX5 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT6.GTXE2_INT_INTERFACE_IMUX6 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT7.GTXE2_INT_INTERFACE_IMUX7 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT8.GTXE2_INT_INTERFACE_IMUX8 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT9.GTXE2_INT_INTERFACE_IMUX9 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT10.GTXE2_INT_INTERFACE_IMUX10 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT11.GTXE2_INT_INTERFACE_IMUX11 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT12.GTXE2_INT_INTERFACE_IMUX12 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT13.GTXE2_INT_INTERFACE_IMUX13 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT14.GTXE2_INT_INTERFACE_IMUX14 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT15.GTXE2_INT_INTERFACE_IMUX15 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT16.GTXE2_INT_INTERFACE_IMUX16 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT17.GTXE2_INT_INTERFACE_IMUX17 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT18.GTXE2_INT_INTERFACE_IMUX18 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT19.GTXE2_INT_INTERFACE_IMUX19 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT20.GTXE2_INT_INTERFACE_IMUX20 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT21.GTXE2_INT_INTERFACE_IMUX21 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT22.GTXE2_INT_INTERFACE_IMUX22 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT23.GTXE2_INT_INTERFACE_IMUX23 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT24.GTXE2_INT_INTERFACE_IMUX24 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT25.GTXE2_INT_INTERFACE_IMUX25 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT26.GTXE2_INT_INTERFACE_IMUX26 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT27.GTXE2_INT_INTERFACE_IMUX27 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT28.GTXE2_INT_INTERFACE_IMUX28 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT29.GTXE2_INT_INTERFACE_IMUX29 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT30.GTXE2_INT_INTERFACE_IMUX30 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT31.GTXE2_INT_INTERFACE_IMUX31 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT32.GTXE2_INT_INTERFACE_IMUX32 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT33.GTXE2_INT_INTERFACE_IMUX33 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT34.GTXE2_INT_INTERFACE_IMUX34 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT35.GTXE2_INT_INTERFACE_IMUX35 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT36.GTXE2_INT_INTERFACE_IMUX36 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT37.GTXE2_INT_INTERFACE_IMUX37 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT38.GTXE2_INT_INTERFACE_IMUX38 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT39.GTXE2_INT_INTERFACE_IMUX39 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT40.GTXE2_INT_INTERFACE_IMUX40 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT41.GTXE2_INT_INTERFACE_IMUX41 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT42.GTXE2_INT_INTERFACE_IMUX42 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT43.GTXE2_INT_INTERFACE_IMUX43 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT44.GTXE2_INT_INTERFACE_IMUX44 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT45.GTXE2_INT_INTERFACE_IMUX45 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT46.GTXE2_INT_INTERFACE_IMUX46 always
GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_OUT47.GTXE2_INT_INTERFACE_IMUX47 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

1
virtex7/ppips_gtx_int_interface_l.db Normal file
View File

@ -0,0 +1 @@
GTX_INT_INTERFACE_L.GTXE2_LEFT_INT_INTERFACE_IMUX_OUT26.GTXE2_LEFT_INT_INTERFACE_IMUX26 always

5
virtex7/ppips_hclk_cmt.db Normal file
View File

@ -0,0 +1,5 @@
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF0.HCLK_CMT_BUFMRCE_O0 always
HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF1.HCLK_CMT_BUFMRCE_O1 always
HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP0.HCLK_CMT_BUFMR_CE0 always
HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP1.HCLK_CMT_BUFMR_CE1 always
HCLK_CMT.HCLK_CMT_MUX_CLK_10.HCLK_CMT_CK_IN8 always

8
virtex7/ppips_hclk_l.db Normal file
View File

@ -0,0 +1,8 @@
HCLK_L.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always
HCLK_L.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always
HCLK_L.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always
HCLK_L.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always
HCLK_L.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always
HCLK_L.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always
HCLK_L.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always
HCLK_L.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always

0
virtex7/ppips_hclk_l.origin_info.db Normal file
View File

8
virtex7/ppips_hclk_r.db Normal file
View File

@ -0,0 +1,8 @@
HCLK_R.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always
HCLK_R.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always
HCLK_R.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always
HCLK_R.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always
HCLK_R.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always
HCLK_R.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always
HCLK_R.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always
HCLK_R.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always

0
virtex7/ppips_hclk_r.origin_info.db Normal file
View File

24
virtex7/ppips_int_interface_l.db Normal file
View File

@ -0,0 +1,24 @@
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

24
virtex7/ppips_int_interface_r.db Normal file
View File

@ -0,0 +1,24 @@
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

108
virtex7/ppips_int_l.db Normal file
View File

@ -0,0 +1,108 @@
INT_L.FAN_ALT0.VCC_WIRE default
INT_L.FAN_ALT1.VCC_WIRE default
INT_L.FAN_ALT2.VCC_WIRE default
INT_L.FAN_ALT3.VCC_WIRE default
INT_L.FAN_ALT4.VCC_WIRE default
INT_L.FAN_ALT5.VCC_WIRE default
INT_L.FAN_ALT6.VCC_WIRE default
INT_L.FAN_ALT7.VCC_WIRE default
INT_L.BYP_ALT0.VCC_WIRE default
INT_L.BYP_ALT1.VCC_WIRE default
INT_L.BYP_ALT2.VCC_WIRE default
INT_L.BYP_ALT3.VCC_WIRE default
INT_L.BYP_ALT4.VCC_WIRE default
INT_L.BYP_ALT5.VCC_WIRE default
INT_L.BYP_ALT6.VCC_WIRE default
INT_L.BYP_ALT7.VCC_WIRE default
INT_L.IMUX_L0.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default
INT_L.IMUX_L10.VCC_WIRE default
INT_L.IMUX_L11.VCC_WIRE default
INT_L.IMUX_L12.VCC_WIRE default
INT_L.IMUX_L13.VCC_WIRE default
INT_L.IMUX_L14.VCC_WIRE default
INT_L.IMUX_L15.VCC_WIRE default
INT_L.IMUX_L16.VCC_WIRE default
INT_L.IMUX_L17.VCC_WIRE default
INT_L.IMUX_L18.VCC_WIRE default
INT_L.IMUX_L19.VCC_WIRE default
INT_L.IMUX_L20.VCC_WIRE default
INT_L.IMUX_L21.VCC_WIRE default
INT_L.IMUX_L22.VCC_WIRE default
INT_L.IMUX_L23.VCC_WIRE default
INT_L.IMUX_L24.VCC_WIRE default
INT_L.IMUX_L25.VCC_WIRE default
INT_L.IMUX_L26.VCC_WIRE default
INT_L.IMUX_L27.VCC_WIRE default
INT_L.IMUX_L28.VCC_WIRE default
INT_L.IMUX_L29.VCC_WIRE default
INT_L.IMUX_L30.VCC_WIRE default
INT_L.IMUX_L31.VCC_WIRE default
INT_L.IMUX_L32.VCC_WIRE default
INT_L.IMUX_L33.VCC_WIRE default
INT_L.IMUX_L34.VCC_WIRE default
INT_L.IMUX_L35.VCC_WIRE default
INT_L.IMUX_L36.VCC_WIRE default
INT_L.IMUX_L37.VCC_WIRE default
INT_L.IMUX_L38.VCC_WIRE default
INT_L.IMUX_L39.VCC_WIRE default
INT_L.IMUX_L40.VCC_WIRE default
INT_L.IMUX_L41.VCC_WIRE default
INT_L.IMUX_L42.VCC_WIRE default
INT_L.IMUX_L43.VCC_WIRE default
INT_L.IMUX_L44.VCC_WIRE default
INT_L.IMUX_L45.VCC_WIRE default
INT_L.IMUX_L46.VCC_WIRE default
INT_L.IMUX_L47.VCC_WIRE default
INT_L.BYP_BOUNCE0.BYP_ALT0 always
INT_L.BYP_BOUNCE1.BYP_ALT1 always
INT_L.BYP_BOUNCE2.BYP_ALT2 always
INT_L.BYP_BOUNCE3.BYP_ALT3 always
INT_L.BYP_BOUNCE4.BYP_ALT4 always
INT_L.BYP_BOUNCE5.BYP_ALT5 always
INT_L.BYP_BOUNCE6.BYP_ALT6 always
INT_L.BYP_BOUNCE7.BYP_ALT7 always
INT_L.BYP_L0.BYP_ALT0 always
INT_L.BYP_L1.BYP_ALT1 always
INT_L.BYP_L2.BYP_ALT2 always
INT_L.BYP_L3.BYP_ALT3 always
INT_L.BYP_L4.BYP_ALT4 always
INT_L.BYP_L5.BYP_ALT5 always
INT_L.BYP_L6.BYP_ALT6 always
INT_L.BYP_L7.BYP_ALT7 always
INT_L.FAN_BOUNCE0.FAN_ALT0 always
INT_L.FAN_BOUNCE1.FAN_ALT1 always
INT_L.FAN_BOUNCE2.FAN_ALT2 always
INT_L.FAN_BOUNCE3.FAN_ALT3 always
INT_L.FAN_BOUNCE4.FAN_ALT4 always
INT_L.FAN_BOUNCE5.FAN_ALT5 always
INT_L.FAN_BOUNCE6.FAN_ALT6 always
INT_L.FAN_BOUNCE7.FAN_ALT7 always
INT_L.FAN_L0.FAN_ALT0 always
INT_L.FAN_L1.FAN_ALT1 always
INT_L.FAN_L2.FAN_ALT2 always
INT_L.FAN_L3.FAN_ALT3 always
INT_L.FAN_L4.FAN_ALT4 always
INT_L.FAN_L5.FAN_ALT5 always
INT_L.FAN_L6.FAN_ALT6 always
INT_L.FAN_L7.FAN_ALT7 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always
INT_L.GCLK_L_B6_EAST.GCLK_L_B6 always
INT_L.GCLK_L_B7_WEST.GCLK_L_B7 always
INT_L.GCLK_L_B7_EAST.GCLK_L_B7 always
INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always
INT_L.GCLK_L_B8_EAST.GCLK_L_B8 always
INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always
INT_L.GCLK_L_B9_EAST.GCLK_L_B9 always

0
virtex7/ppips_int_l.origin_info.db Normal file
View File

108
virtex7/ppips_int_r.db Normal file
View File

@ -0,0 +1,108 @@
INT_R.FAN_ALT0.VCC_WIRE default
INT_R.FAN_ALT1.VCC_WIRE default
INT_R.FAN_ALT2.VCC_WIRE default
INT_R.FAN_ALT3.VCC_WIRE default
INT_R.FAN_ALT4.VCC_WIRE default
INT_R.FAN_ALT5.VCC_WIRE default
INT_R.FAN_ALT6.VCC_WIRE default
INT_R.FAN_ALT7.VCC_WIRE default
INT_R.BYP_ALT0.VCC_WIRE default
INT_R.BYP_ALT1.VCC_WIRE default
INT_R.BYP_ALT2.VCC_WIRE default
INT_R.BYP_ALT3.VCC_WIRE default
INT_R.BYP_ALT4.VCC_WIRE default
INT_R.BYP_ALT5.VCC_WIRE default
INT_R.BYP_ALT6.VCC_WIRE default
INT_R.BYP_ALT7.VCC_WIRE default
INT_R.IMUX0.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default
INT_R.IMUX10.VCC_WIRE default
INT_R.IMUX11.VCC_WIRE default
INT_R.IMUX12.VCC_WIRE default
INT_R.IMUX13.VCC_WIRE default
INT_R.IMUX14.VCC_WIRE default
INT_R.IMUX15.VCC_WIRE default
INT_R.IMUX16.VCC_WIRE default
INT_R.IMUX17.VCC_WIRE default
INT_R.IMUX18.VCC_WIRE default
INT_R.IMUX19.VCC_WIRE default
INT_R.IMUX20.VCC_WIRE default
INT_R.IMUX21.VCC_WIRE default
INT_R.IMUX22.VCC_WIRE default
INT_R.IMUX23.VCC_WIRE default
INT_R.IMUX24.VCC_WIRE default
INT_R.IMUX25.VCC_WIRE default
INT_R.IMUX26.VCC_WIRE default
INT_R.IMUX27.VCC_WIRE default
INT_R.IMUX28.VCC_WIRE default
INT_R.IMUX29.VCC_WIRE default
INT_R.IMUX30.VCC_WIRE default
INT_R.IMUX31.VCC_WIRE default
INT_R.IMUX32.VCC_WIRE default
INT_R.IMUX33.VCC_WIRE default
INT_R.IMUX34.VCC_WIRE default
INT_R.IMUX35.VCC_WIRE default
INT_R.IMUX36.VCC_WIRE default
INT_R.IMUX37.VCC_WIRE default
INT_R.IMUX38.VCC_WIRE default
INT_R.IMUX39.VCC_WIRE default
INT_R.IMUX40.VCC_WIRE default
INT_R.IMUX41.VCC_WIRE default
INT_R.IMUX42.VCC_WIRE default
INT_R.IMUX43.VCC_WIRE default
INT_R.IMUX44.VCC_WIRE default
INT_R.IMUX45.VCC_WIRE default
INT_R.IMUX46.VCC_WIRE default
INT_R.IMUX47.VCC_WIRE default
INT_R.BYP_BOUNCE0.BYP_ALT0 always
INT_R.BYP_BOUNCE1.BYP_ALT1 always
INT_R.BYP_BOUNCE2.BYP_ALT2 always
INT_R.BYP_BOUNCE3.BYP_ALT3 always
INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.FAN_BOUNCE0.FAN_ALT0 always
INT_R.FAN_BOUNCE1.FAN_ALT1 always
INT_R.FAN_BOUNCE2.FAN_ALT2 always
INT_R.FAN_BOUNCE3.FAN_ALT3 always
INT_R.FAN_BOUNCE4.FAN_ALT4 always
INT_R.FAN_BOUNCE5.FAN_ALT5 always
INT_R.FAN_BOUNCE6.FAN_ALT6 always
INT_R.FAN_BOUNCE7.FAN_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.GCLK_B0_EAST.GCLK_B0 always
INT_R.GCLK_B0_WEST.GCLK_B0 always
INT_R.GCLK_B1_EAST.GCLK_B1 always
INT_R.GCLK_B1_WEST.GCLK_B1 always
INT_R.GCLK_B2_EAST.GCLK_B2 always
INT_R.GCLK_B2_WEST.GCLK_B2 always
INT_R.GCLK_B3_EAST.GCLK_B3 always
INT_R.GCLK_B3_WEST.GCLK_B3 always
INT_R.GCLK_B4_EAST.GCLK_B4 always
INT_R.GCLK_B4_WEST.GCLK_B4 always
INT_R.GCLK_B5_EAST.GCLK_B5 always
INT_R.GCLK_B5_WEST.GCLK_B5 always

0
virtex7/ppips_int_r.origin_info.db Normal file
View File

24
virtex7/ppips_io_int_interface_l.db Normal file
View File

@ -0,0 +1,24 @@
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

24
virtex7/ppips_io_int_interface_r.db Normal file
View File

@ -0,0 +1,24 @@
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

0
virtex7/ppips_liob33_sing.db Normal file
View File

165
virtex7/ppips_lioi.db Normal file
View File

@ -0,0 +1,165 @@
LIOI.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI.IOI_IDELAYCTRL_RST.IOI_IMUX24_0 always
LIOI.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI.IOI_ILOGIC0_O.LIOI_ILOGIC0_D always
LIOI.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI.IOI_ILOGIC1_O.LIOI_ILOGIC1_D always
LIOI.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI.IOI_IMUX_RC2.IOI_BYP4_1 always
LIOI.IOI_IMUX_RC3.IOI_BYP3_1 always
LIOI.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
LIOI.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
LIOI.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
LIOI.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
LIOI.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
LIOI.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI.IOI_LOGIC_OUTS13_0.IOI_IDELAYCTRL_DNPULSEOUT always
LIOI.IOI_LOGIC_OUTS13_1.IOI_IDELAYCTRL_OUTN1 always
LIOI.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
LIOI.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
LIOI.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
LIOI.IOI_LOGIC_OUTS15_1.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI.IOI_LOGIC_OUTS16_0.IOI_IDELAYCTRL_UPPULSEOUT always
LIOI.IOI_LOGIC_OUTS16_1.IOI_IDELAYCTRL_OUTN65 always
LIOI.IOI_LOGIC_OUTS18_0.IOI_ILOGIC1_O always
LIOI.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O always
LIOI.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
LIOI.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
LIOI.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI.IOI_LOGIC_OUTS22_1.IOI_IDELAYCTRL_RDY always
LIOI.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
LIOI.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
LIOI.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
LIOI.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
LIOI.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
LIOI.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
LIOI.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always
LIOI.LIOI_DCI_T_TERM0.IOI_IMUX6_1 always
LIOI.LIOI_DCI_T_TERM1.IOI_IMUX6_0 always
LIOI.LIOI_I0.LIOI_IBUF0 always
LIOI.LIOI_I1.LIOI_IBUF1 always
LIOI.LIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
LIOI.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
LIOI.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI.LIOI_ILOGIC1_DDLY.LIOI_IDELAY1_DATAOUT always
LIOI.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI.LIOI_ILOGIC1_OFB.LIOI_OLOGIC1_OFB always
LIOI.LIOI_ILOGIC1_TFB.LIOI_OLOGIC1_TFB_LOCAL always
LIOI.LIOI_ISIN11.LIOI_ISOUT10 always
LIOI.LIOI_ISIN21.LIOI_ISOUT20 always
LIOI.LIOI_O0.LIOI_OLOGIC0_OQ always
LIOI.LIOI_O1.LIOI_OLOGIC1_OQ always
LIOI.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI.LIOI_OLOGIC1_OQ.IOI_OLOGIC1_D1 always
LIOI.LIOI_OLOGIC1_TFB_LOCAL.LIOI_OLOGIC1_TFB always
LIOI.LIOI_OLOGIC1_TQ.IOI_OLOGIC1_T1 always
LIOI.LIOI_OSIN10.LIOI_OSOUT11 always
LIOI.LIOI_OSIN20.LIOI_OSOUT21 always
LIOI.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI.LIOI_T1.LIOI_OLOGIC1_TQ always

71
virtex7/ppips_lioi3_sing.db Normal file
View File

@ -0,0 +1,71 @@
LIOI3_SING.IOI_IDELAY0_CE.IOI_IMUX32_0 always
LIOI3_SING.IOI_IDELAY0_CINVCTRL.IOI_BYP6_0 always
LIOI3_SING.IOI_IDELAY0_C.IOI_CLK1_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_SING.IOI_IDELAY0_DATAIN.IOI_IMUX25_0 always
LIOI3_SING.IOI_IDELAY0_INC.IOI_IMUX26_0 always
LIOI3_SING.IOI_IDELAY0_LD.IOI_IMUX30_0 always
LIOI3_SING.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_SING.IOI_IDELAY0_REGRST.IOI_IMUX12_0 always
LIOI3_SING.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_0 always
LIOI3_SING.IOI_ILOGIC0_CE1.IOI_IMUX5_0 always
LIOI3_SING.IOI_ILOGIC0_CE2.IOI_IMUX14_0 always
LIOI3_SING.IOI_ILOGIC0_CLKDIV.IOI_CLK0_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_SING.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_SING.IOI_ILOGIC0_SR.IOI_CTRL1_0 always
LIOI3_SING.IOI_LOGIC_OUTS0_0.IOI_ILOGIC0_Q1 always
LIOI3_SING.IOI_LOGIC_OUTS10_0.IOI_ILOGIC0_Q4 always
LIOI3_SING.IOI_LOGIC_OUTS1_0.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_SING.IOI_LOGIC_OUTS11_0.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3_SING.IOI_LOGIC_OUTS14_0.IOI_ILOGIC0_Q5 always
LIOI3_SING.IOI_LOGIC_OUTS15_0.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI3_SING.IOI_LOGIC_OUTS18_0.IOI_ILOGIC0_O always
LIOI3_SING.IOI_LOGIC_OUTS19_0.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3_SING.IOI_LOGIC_OUTS20_0.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3_SING.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_SING.IOI_LOGIC_OUTS23_0.IOI_ILOGIC0_Q2 always
LIOI3_SING.IOI_LOGIC_OUTS3_0.IOI_ILOGIC0_Q6 always
LIOI3_SING.IOI_LOGIC_OUTS5_0.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_SING.IOI_LOGIC_OUTS7_0.IOI_ILOGIC0_Q7 always
LIOI3_SING.IOI_LOGIC_OUTS8_0.IOI_ILOGIC0_Q8 always
LIOI3_SING.IOI_LOGIC_OUTS9_0.IOI_ILOGIC0_Q3 always
LIOI3_SING.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3_SING.IOI_OLOGIC0_D1.IOI_IMUX34_0 always
LIOI3_SING.IOI_OLOGIC0_D2.IOI_IMUX40_0 always
LIOI3_SING.IOI_OLOGIC0_D3.IOI_IMUX44_0 always
LIOI3_SING.IOI_OLOGIC0_D4.IOI_IMUX42_0 always
LIOI3_SING.IOI_OLOGIC0_D5.IOI_IMUX43_0 always
LIOI3_SING.IOI_OLOGIC0_D6.IOI_IMUX45_0 always
LIOI3_SING.IOI_OLOGIC0_D7.IOI_IMUX46_0 always
LIOI3_SING.IOI_OLOGIC0_D8.IOI_IMUX47_0 always
LIOI3_SING.IOI_OLOGIC0_OCE.IOI_IMUX29_0 always
LIOI3_SING.IOI_OLOGIC0_SR.IOI_CTRL0_0 always
LIOI3_SING.IOI_OLOGIC0_T1.IOI_IMUX15_0 always
LIOI3_SING.IOI_OLOGIC0_T2.IOI_IMUX7_0 always
LIOI3_SING.IOI_OLOGIC0_T3.IOI_IMUX13_0 always
LIOI3_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
LIOI3_SING.IOI_OLOGIC0_TBYTEIN.IOI_SING_TBYTEIN always
LIOI3_SING.IOI_OLOGIC0_TCE.IOI_IMUX1_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_0 always
LIOI3_SING.LIOI_DCI_T_TERM0.IOI_IMUX6_0 always
LIOI3_SING.LIOI_I0.LIOI_IBUF0 always
LIOI3_SING.LIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
LIOI3_SING.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3_SING.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3_SING.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_SING.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3_SING.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_SING.LIOI_O0.LIOI_OLOGIC0_OQ always
LIOI3_SING.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI3_SING.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI3_SING.LIOI_T0.LIOI_OLOGIC0_TQ always

77
virtex7/ppips_lioi_sing.db Normal file
View File

@ -0,0 +1,77 @@
LIOI_SING.IOI_IDELAY0_CE.IOI_IMUX32_0 always
LIOI_SING.IOI_IDELAY0_CINVCTRL.IOI_BYP6_0 always
LIOI_SING.IOI_IDELAY0_C.IOI_CLK1_0 always
LIOI_SING.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI_SING.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI_SING.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI_SING.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI_SING.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI_SING.IOI_IDELAY0_DATAIN.IOI_IMUX25_0 always
LIOI_SING.IOI_IDELAY0_INC.IOI_IMUX26_0 always
LIOI_SING.IOI_IDELAY0_LD.IOI_IMUX30_0 always
LIOI_SING.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_0 always
LIOI_SING.IOI_IDELAY0_REGRST.IOI_IMUX12_0 always
LIOI_SING.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_0 always
LIOI_SING.IOI_ILOGIC0_CE1.IOI_IMUX5_0 always
LIOI_SING.IOI_ILOGIC0_CE2.IOI_IMUX14_0 always
LIOI_SING.IOI_ILOGIC0_CLKDIV.IOI_CLK0_0 always
LIOI_SING.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI_SING.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI_SING.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_0 always
LIOI_SING.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI_SING.IOI_ILOGIC0_SR.IOI_CTRL1_0 always
LIOI_SING.IOI_LOGIC_OUTS0_0.IOI_ILOGIC0_Q1 always
LIOI_SING.IOI_LOGIC_OUTS10_0.IOI_ILOGIC0_Q4 always
LIOI_SING.IOI_LOGIC_OUTS1_0.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI_SING.IOI_LOGIC_OUTS11_0.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI_SING.IOI_LOGIC_OUTS14_0.IOI_ILOGIC0_Q5 always
LIOI_SING.IOI_LOGIC_OUTS15_0.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI_SING.IOI_LOGIC_OUTS18_0.IOI_ILOGIC0_O always
LIOI_SING.IOI_LOGIC_OUTS19_0.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI_SING.IOI_LOGIC_OUTS20_0.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI_SING.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC0_TFB_LOCAL always
LIOI_SING.IOI_LOGIC_OUTS23_0.IOI_ILOGIC0_Q2 always
LIOI_SING.IOI_LOGIC_OUTS3_0.IOI_ILOGIC0_Q6 always
LIOI_SING.IOI_LOGIC_OUTS5_0.IOI_OLOGIC0_IOCLKGLITCH always
LIOI_SING.IOI_LOGIC_OUTS7_0.IOI_ILOGIC0_Q7 always
LIOI_SING.IOI_LOGIC_OUTS8_0.IOI_ILOGIC0_Q8 always
LIOI_SING.IOI_LOGIC_OUTS9_0.IOI_ILOGIC0_Q3 always
LIOI_SING.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI_SING.IOI_OLOGIC0_D1.IOI_IMUX34_0 always
LIOI_SING.IOI_OLOGIC0_D2.IOI_IMUX40_0 always
LIOI_SING.IOI_OLOGIC0_D3.IOI_IMUX44_0 always
LIOI_SING.IOI_OLOGIC0_D4.IOI_IMUX42_0 always
LIOI_SING.IOI_OLOGIC0_D5.IOI_IMUX43_0 always
LIOI_SING.IOI_OLOGIC0_D6.IOI_IMUX45_0 always
LIOI_SING.IOI_OLOGIC0_D7.IOI_IMUX46_0 always
LIOI_SING.IOI_OLOGIC0_D8.IOI_IMUX47_0 always
LIOI_SING.IOI_OLOGIC0_OCE.IOI_IMUX29_0 always
LIOI_SING.IOI_OLOGIC0_SR.IOI_CTRL0_0 always
LIOI_SING.IOI_OLOGIC0_T1.IOI_IMUX15_0 always
LIOI_SING.IOI_OLOGIC0_T2.IOI_IMUX7_0 always
LIOI_SING.IOI_OLOGIC0_T3.IOI_IMUX13_0 always
LIOI_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
LIOI_SING.IOI_OLOGIC0_TBYTEIN.IOI_SING_TBYTEIN always
LIOI_SING.IOI_OLOGIC0_TCE.IOI_IMUX1_0 always
LIOI_SING.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_0 always
LIOI_SING.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_0 always
LIOI_SING.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_0 always
LIOI_SING.LIOI_DCI_T_TERM0.IOI_IMUX6_0 always
LIOI_SING.LIOI_I0.LIOI_IBUF0 always
LIOI_SING.LIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
LIOI_SING.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI_SING.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI_SING.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI_SING.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI_SING.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI_SING.LIOI_O0.LIOI_OLOGIC0_OQ always
LIOI_SING.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI_SING.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI_SING.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI_SING.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI_SING.OLOGIC_Y0.OMUX.D1 always
LIOI_SING.OLOGIC_Y0.OQUSED always
LIOI_SING.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF always
LIOI_SING.OLOGIC_Y1.OMUX.D1 always
LIOI_SING.OLOGIC_Y1.OQUSED always
LIOI_SING.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF always

158
virtex7/ppips_lioi_tbytesrc.db Normal file
View File

@ -0,0 +1,158 @@
LIOI_TBYTESRC.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI_TBYTESRC.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI_TBYTESRC.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI_TBYTESRC.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI_TBYTESRC.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI_TBYTESRC.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI_TBYTESRC.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI_TBYTESRC.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI_TBYTESRC.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI_TBYTESRC.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI_TBYTESRC.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI_TBYTESRC.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI_TBYTESRC.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI_TBYTESRC.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI_TBYTESRC.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI_TBYTESRC.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI_TBYTESRC.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI_TBYTESRC.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI_TBYTESRC.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI_TBYTESRC.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI_TBYTESRC.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI_TBYTESRC.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI_TBYTESRC.IOI_ILOGIC0_O.LIOI_ILOGIC0_D always
LIOI_TBYTESRC.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI_TBYTESRC.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI_TBYTESRC.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI_TBYTESRC.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI_TBYTESRC.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI_TBYTESRC.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI_TBYTESRC.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI_TBYTESRC.IOI_ILOGIC1_O.LIOI_ILOGIC1_D always
LIOI_TBYTESRC.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS15_1.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS18_0.IOI_ILOGIC1_O always
LIOI_TBYTESRC.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O always
LIOI_TBYTESRC.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI_TBYTESRC.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI_TBYTESRC.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI_TBYTESRC.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI_TBYTESRC.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI_TBYTESRC.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI_TBYTESRC.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI_TBYTESRC.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI_TBYTESRC.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI_TBYTESRC.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI_TBYTESRC.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI_TBYTESRC.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI_TBYTESRC.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI_TBYTESRC.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI_TBYTESRC.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI_TBYTESRC.IOI_TBYTEIN.IOI_OLOGIC1_TBYTEOUT always
LIOI_TBYTESRC.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI_TBYTESRC.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI_TBYTESRC.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI_TBYTESRC.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI_TBYTESRC.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI_TBYTESRC.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always
LIOI_TBYTESRC.LIOI_DCI_T_TERM0.IOI_IMUX6_1 always
LIOI_TBYTESRC.LIOI_DCI_T_TERM1.IOI_IMUX6_0 always
LIOI_TBYTESRC.LIOI_I0.LIOI_IBUF0 always
LIOI_TBYTESRC.LIOI_I1.LIOI_IBUF1 always
LIOI_TBYTESRC.LIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
LIOI_TBYTESRC.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI_TBYTESRC.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI_TBYTESRC.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI_TBYTESRC.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
LIOI_TBYTESRC.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI_TBYTESRC.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI_TBYTESRC.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI_TBYTESRC.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI_TBYTESRC.LIOI_ILOGIC1_DDLY.LIOI_IDELAY1_DATAOUT always
LIOI_TBYTESRC.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI_TBYTESRC.LIOI_ILOGIC1_OFB.LIOI_OLOGIC1_OFB always
LIOI_TBYTESRC.LIOI_ILOGIC1_TFB.LIOI_OLOGIC1_TFB_LOCAL always
LIOI_TBYTESRC.LIOI_ISIN11.LIOI_ISOUT10 always
LIOI_TBYTESRC.LIOI_ISIN21.LIOI_ISOUT20 always
LIOI_TBYTESRC.LIOI_O0.LIOI_OLOGIC0_OQ always
LIOI_TBYTESRC.LIOI_O1.LIOI_OLOGIC1_OQ always
LIOI_TBYTESRC.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI_TBYTESRC.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI_TBYTESRC.LIOI_OLOGIC1_OQ.IOI_OLOGIC1_D1 always
LIOI_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL.LIOI_OLOGIC1_TFB always
LIOI_TBYTESRC.LIOI_OLOGIC1_TQ.IOI_OLOGIC1_T1 always
LIOI_TBYTESRC.LIOI_OSIN10.LIOI_OSOUT11 always
LIOI_TBYTESRC.LIOI_OSIN20.LIOI_OSOUT21 always
LIOI_TBYTESRC.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI_TBYTESRC.LIOI_T1.LIOI_OLOGIC1_TQ always

Some files were not shown because too many files have changed in this diff Show More