luke
/
prjxray-db
mirror of https://github.com/openXC7/prjxray-db.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Updating all based on "Merge pull request #1614 from antmicro/add-gtp-ports-attrs-file" 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2021-03-11 11:30:09 -08:00
parent a7f9fd99e4
commit 2e51ad3ff7
110 changed files with 62011 additions and 49562 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

224
Info.md
View File

@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Thu 25 Feb 2021 06:48:02 PM UTC (2021-02-25T18:48:02+00:00).
Last updated on Thu 11 Mar 2021 07:29:56 PM UTC (2021-03-11T19:29:56+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [6867429c](https://github.com/SymbiFlow/prjxray/commit/6867429cc3a4ce422b06ceda100b868a0a7f8b23).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [0d9418a9](https://github.com/SymbiFlow/prjxray/commit/0d9418a908dafecae1d38418d3a0e2d2b2416ea0).
Latest commit was;
```
commit 6867429cc3a4ce422b06ceda100b868a0a7f8b23
Merge: 45abab75 9b4f4551
commit 0d9418a908dafecae1d38418d3a0e2d2b2416ea0
Merge: 0ddf03b8 2ccada20
Author: litghost <537074+litghost@users.noreply.github.com>
Date: Wed Feb 24 08:23:12 2021 -0800
Date: Wed Mar 10 09:07:49 2021 -0800
Merge pull request #1592 from antmicro/fix-iob-lvds-tmds
Merge pull request #1614 from antmicro/add-gtp-ports-attrs-file
030-iob: improve rdb processing for LVDS and TMDS
gtp: generate attributes and ports files to add to the db
```
@ -59,7 +59,7 @@ Date: Wed Feb 24 08:23:12 2021 -0800
### Settings
Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/artix7.sh)
Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/artix7.sh)
```shell
#!/bin/bash
# Copyright (C) 2017-2020 The Project X-Ray Authors.
@ -104,24 +104,28 @@ eval $(python3 ${XRAY_UTILS_DIR}/create_environment.py)
Results have checksums;
* [`efcb8d5580edebfd8a6aa1d742c65cfd96f5544a855e4956e790fcee2568d30a ./artix7/cells_data/gtpe2_channel_attrs.json`](./artix7/cells_data/gtpe2_channel_attrs.json)
* [`962b9db76b9e6333b72880fc196a492756f4f5d37dae2fe727c7f6fb6db8e834 ./artix7/cells_data/gtpe2_channel_ports.json`](./artix7/cells_data/gtpe2_channel_ports.json)
* [`0928d105dc294cedc1f19bf61790f81f5adee62f03fcfe4a4d220546d99a2b40 ./artix7/cells_data/gtpe2_common_attrs.json`](./artix7/cells_data/gtpe2_common_attrs.json)
* [`b6c8fbd663d4c7410909f3b7cb0a473d82343e3240810a27e4323ac6220abeb5 ./artix7/cells_data/gtpe2_common_ports.json`](./artix7/cells_data/gtpe2_common_ports.json)
* [`d7c598657e5d66095a732b74bfa559253fba959bf53706cfd464635f07ae6b9b ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`b5a8a5e4aa788f9a8b17a0b0879814d9e8f38f6cbb65740fb537935fb028296a ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md)
* [`560f255b569fd4798989f45104d4a511b51380418d4ca6fc53201141b36b20aa ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
* [`1d8a121c3aa3bca7893429cfb08a8748206134271432daa52cdc9d3f5593bda0 ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
* [`b57ed4b48e47f3bc75e9a95dd15bc40082d3bbb35883a646d98c1ed60402713c ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
* [`f1f528bdfd394f9d11a8fe98e42e4ad67b5b11f96cd49f31f8b61b1de8c585c0 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
* [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
* [`931c1598b75005a8a8e5b2225cc7454c2c7be451cb907bc4c047cb04db99772d ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
* [`5d06132c788097344a9bca7040a08dd0e1632e177ed8def1d7445132020cc768 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
* [`ff29541f33458d2912cc630f03df7ee959246bb783c5840cddea32b42746b52f ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`83549af508a4004ebd53f71249c7e11db7af9c2d603f91bbaafcffe9dd824b9a ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`884af447661ff1cb653cd8280602c2348435366b35bf2627e2221af34899d191 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
* [`128e73ee026cf2238a35c7e993b845e3551919c90fc77b277635bc5098d59741 ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
* [`955daed70c5728c13865eddc9bd7001d93183a50c560559a7b6628aa85b1fbbe ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
* [`b902e72932a9039258a0e469a0499e5621adc1e797e6b201290d05a9313ac3cd ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
* [`a0e37fee3200d72d04ff92c60a840a406f053de4c3d1c779d4ffbcd1823bf47f ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
* [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt)
* [`d3109010f8fced3be08e720741a157d08b7042359e84d04bbe677f50cbf10a04 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
* [`abedfa7f2ee5a4dbc51b582ebae62dd20489f745a4a239e49b18ba3e02be019f ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`a63c62d553aa5811bf3d98c82d998733bf27e28c57328c08e7329f5dd980b9c2 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`ada2b826fc1b0c687ab4194f95b025460db0fbad8fe24a69ed600b1983b51ea8 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`e5ebd51966bcfddb9b04078203231810df64f5afd3e3a608a5fb8fdc7d3c3304 ./artix7/mapping/devices.yaml`](./artix7/mapping/devices.yaml)
* [`9a63d519dcfee4016602553490a53c00a2fbc8cd0355ed201cfa3545650f6ce4 ./artix7/mapping/parts.yaml`](./artix7/mapping/parts.yaml)
@ -213,22 +217,24 @@ Results have checksums;
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_l.origin_info.db`](./artix7/ppips_dsp_l.origin_info.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.db`](./artix7/ppips_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.origin_info.db`](./artix7/ppips_dsp_r.origin_info.db)
* [`9a41911dfa0be59fced626ba228abf9ef7cf020affbd2743a26ed16b6856dfd5 ./artix7/ppips_gtp_channel_0.db`](./artix7/ppips_gtp_channel_0.db)
* [`4179cf95c0e079b2bf699e944e3059470147c60de6cfcdda9bd70c907f6851df ./artix7/ppips_gtp_channel_0_mid_left.db`](./artix7/ppips_gtp_channel_0_mid_left.db)
* [`3550a2e77580e0f8385418efd0beea4d6fe2f7e21544da921116459589e58a9a ./artix7/ppips_gtp_channel_0_mid_right.db`](./artix7/ppips_gtp_channel_0_mid_right.db)
* [`42449df4353f2fc1764ee337f0e18afb0d4b419e611eda5ea7282180587c118b ./artix7/ppips_gtp_channel_1.db`](./artix7/ppips_gtp_channel_1.db)
* [`663a27fa99c2e337e961d6636bf41d57e4bbade7ba31af82623280f40ecc54f7 ./artix7/ppips_gtp_channel_1_mid_left.db`](./artix7/ppips_gtp_channel_1_mid_left.db)
* [`5502dc8909a39565bb584df2e702c9d5aada1ab7b520fa01366eb1e07e9521ca ./artix7/ppips_gtp_channel_1_mid_right.db`](./artix7/ppips_gtp_channel_1_mid_right.db)
* [`b14787fc826a3c64160af864346775ca1e387a08f23679a72c9e4fa11a436b40 ./artix7/ppips_gtp_channel_2.db`](./artix7/ppips_gtp_channel_2.db)
* [`21df745b5828962164f7d7b54df58bb308a2083f8863d5be10e870367f34a1f4 ./artix7/ppips_gtp_channel_2_mid_left.db`](./artix7/ppips_gtp_channel_2_mid_left.db)
* [`993c198a976dd0ffe90592296923210480aec35a3f259295c3486a783390d892 ./artix7/ppips_gtp_channel_2_mid_right.db`](./artix7/ppips_gtp_channel_2_mid_right.db)
* [`229584a094cadcf181cc7c9b04a0c151ad9fc0b230cccc761b33beb7109156ed ./artix7/ppips_gtp_channel_3.db`](./artix7/ppips_gtp_channel_3.db)
* [`df7fe61346d9a21e1b69ba2a045b8da6f6efa4a0d1dfab29f86577475d7b7cc3 ./artix7/ppips_gtp_channel_3_mid_left.db`](./artix7/ppips_gtp_channel_3_mid_left.db)
* [`565286894f6c314d07809888b3c17279f8784bc38dfe59ee16d3b7874ba770f8 ./artix7/ppips_gtp_channel_3_mid_right.db`](./artix7/ppips_gtp_channel_3_mid_right.db)
* [`e5b17573f36b84838c40a76bdf9015fd89bd860bb2dde3a0da80061248bcd17a ./artix7/ppips_gtp_common.db`](./artix7/ppips_gtp_common.db)
* [`afe293d42525ca4fb85e4fc795d841f9d71ac0d3be85b3d5b1c6011834492348 ./artix7/ppips_gtp_common_mid_left.db`](./artix7/ppips_gtp_common_mid_left.db)
* [`6bb1ed0b882bd46476fdc425721b67096282828cc9a7adc22176a634e1253820 ./artix7/ppips_gtp_common_mid_right.db`](./artix7/ppips_gtp_common_mid_right.db)
* [`35dd7280544b90f1de8b8d02b952a2e3180e734653c5a9889dbac3854d887cd3 ./artix7/ppips_gtp_int_interface.db`](./artix7/ppips_gtp_int_interface.db)
* [`cec8e43d2eb67f3eb1d45e1393b8c9809a46e9b82d619e0fa8d421acf65bbd85 ./artix7/ppips_gtp_channel_0.db`](./artix7/ppips_gtp_channel_0.db)
* [`9502d2635bb01f9823a7ff473acce052f97903abefc87230ed29dacb22a93537 ./artix7/ppips_gtp_channel_0_mid_left.db`](./artix7/ppips_gtp_channel_0_mid_left.db)
* [`bd881f11a46fe69af9ab4a84c14c4670c4c274098c2e3d77407639f4e4e8e1eb ./artix7/ppips_gtp_channel_0_mid_right.db`](./artix7/ppips_gtp_channel_0_mid_right.db)
* [`c2ecc077a70e4a077e2b25c1fcc9e4459c635806f378f21f52e20411c90ac04e ./artix7/ppips_gtp_channel_1.db`](./artix7/ppips_gtp_channel_1.db)
* [`653cb2b169ba9abfdc9b74723b67fc9170fd7efea8b7cd5579688f43abeca166 ./artix7/ppips_gtp_channel_1_mid_left.db`](./artix7/ppips_gtp_channel_1_mid_left.db)
* [`518b48f277454295222baba2f7bc46e321630cd2923ad0f25a7de7a2ce0cd8f5 ./artix7/ppips_gtp_channel_1_mid_right.db`](./artix7/ppips_gtp_channel_1_mid_right.db)
* [`793af5ec6f50d440dd5df9739cdad49967adcf0b8f6db656143b703663b0cb4c ./artix7/ppips_gtp_channel_2.db`](./artix7/ppips_gtp_channel_2.db)
* [`e283c878a932cbf9f0af41fa7f220572393cddccaa7a4bfcd098b4e1e8729043 ./artix7/ppips_gtp_channel_2_mid_left.db`](./artix7/ppips_gtp_channel_2_mid_left.db)
* [`450fec8a8618320e905433639af7d55571e557bba586d8ecf5bed611f5876bd4 ./artix7/ppips_gtp_channel_2_mid_right.db`](./artix7/ppips_gtp_channel_2_mid_right.db)
* [`8760eedb9df37a5b1c9116830426af90ca3eb7b1b57b88bafe5462d4feea55b4 ./artix7/ppips_gtp_channel_3.db`](./artix7/ppips_gtp_channel_3.db)
* [`aac1994d80f9d596b442f6c12f0274e36af75dea23c150fd894d4119201df6ee ./artix7/ppips_gtp_channel_3_mid_left.db`](./artix7/ppips_gtp_channel_3_mid_left.db)
* [`3cfedd95d7c8892abfb4e00004f96019494755de7880b47a13053c3978285af5 ./artix7/ppips_gtp_channel_3_mid_right.db`](./artix7/ppips_gtp_channel_3_mid_right.db)
* [`8fed1b3aea95f60e6f03c8f59aed1e0b57b55f8ae03c725cd4c2cf6dbe627332 ./artix7/ppips_gtp_common.db`](./artix7/ppips_gtp_common.db)
* [`875523212b092efe2cb4dcf2a8113bee0612b1a90346b288cac7f350ca7ba976 ./artix7/ppips_gtp_common_mid_left.db`](./artix7/ppips_gtp_common_mid_left.db)
* [`53e657437795033a555a247c3011fecaef3f54e369a106df276d80d383394f1e ./artix7/ppips_gtp_common_mid_right.db`](./artix7/ppips_gtp_common_mid_right.db)
* [`40aa7466e006edc7e2b4265c74455ea6bcc8ddcabeb25535865962a360d0d9e9 ./artix7/ppips_gtp_int_interface.db`](./artix7/ppips_gtp_int_interface.db)
* [`25b73299c2c7ef8e4edc6bece4530b5c550a90db1e46892dad942ffec05b019e ./artix7/ppips_gtp_int_interface_l.db`](./artix7/ppips_gtp_int_interface_l.db)
* [`7066eaf79cfebffff26f86e85c2fb759c991f1440c5e786d1bf97148a977c58a ./artix7/ppips_gtp_int_interface_r.db`](./artix7/ppips_gtp_int_interface_r.db)
* [`edeccdbee739f85558baee09f68ebee6cca1f2121b1ef7e38839e8a9f0797641 ./artix7/ppips_hclk_cmt.db`](./artix7/ppips_hclk_cmt.db)
* [`633e6ad608c7b7fc6b5d863812fea75fd0162bf6d58dd6794e6d3f32100ec2a3 ./artix7/ppips_hclk_ioi3.db`](./artix7/ppips_hclk_ioi3.db)
* [`b61bbc9db6d0de1141a87d787f5d118be0a244802eed712612ff2aa0b6aeb73a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
@ -247,6 +253,10 @@ Results have checksums;
* [`f87e449ccf9c605acad950269bfe104bc3a45daf79c5b7fe21042169feb7a428 ./artix7/ppips_lioi3_sing.db`](./artix7/ppips_lioi3_sing.db)
* [`1046256199fd3c54a5f3ee7e5ec7fd72863882e01cc8da326e487c763159e2f8 ./artix7/ppips_lioi3_tbytesrc.db`](./artix7/ppips_lioi3_tbytesrc.db)
* [`b6255a5ec971695a0aadd4901f2021d839c20b9cff781b2fccc8f5e779295319 ./artix7/ppips_lioi3_tbyteterm.db`](./artix7/ppips_lioi3_tbyteterm.db)
* [`48ad9ebcaa48a039f5bcc9f6d5b4736be64976434ad79bc317e88c4f40b980aa ./artix7/ppips_pcie_bot.db`](./artix7/ppips_pcie_bot.db)
* [`38b7dd3cf1ef560f06933b501059b4d029e1625193038eba112424f9bff630c5 ./artix7/ppips_pcie_int_interface_l.db`](./artix7/ppips_pcie_int_interface_l.db)
* [`e998a9cc7b3ea7f185485133a97510a9ec73dfec574f3b8583eb968073f6a7d5 ./artix7/ppips_pcie_int_interface_r.db`](./artix7/ppips_pcie_int_interface_r.db)
* [`5684a64e33378f61f7b92cee7011c2fc4f85be16762919a86103dc8652c73d63 ./artix7/ppips_pcie_top.db`](./artix7/ppips_pcie_top.db)
* [`5c818ae170303c8f215cb08e33f6682eb18e4c1b142da8c86e209d80199f6512 ./artix7/ppips_rioi3.db`](./artix7/ppips_rioi3.db)
* [`bb65252c9f425d9b6eee636057f458b5b7548ee47228127f29afe0e7e5878682 ./artix7/ppips_rioi3_sing.db`](./artix7/ppips_rioi3_sing.db)
* [`fe8fe52b167f239f3d28ffc0c1f4dd35de5ad2572526ad79500ac2cf89a5dfb2 ./artix7/ppips_rioi3_tbytesrc.db`](./artix7/ppips_rioi3_tbytesrc.db)
@ -279,48 +289,48 @@ Results have checksums;
* [`cf71a4438ae35cb2493b614e895e3d5cf577613a8d9c10cf1c566872a2ea9b4f ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db)
* [`8ab24467b7f56fa8ff0dd334c0588cb196a4d875895abb48afcd33e1e2ba1deb ./artix7/segbits_clk_hrow_top_r.db`](./artix7/segbits_clk_hrow_top_r.db)
* [`cf14bb07343da1aede131d701579bcda71a147da4d8cbefa85e8017f2c54225d ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db)
* [`311bd38ca939dc8643afb130f77c3642f3a89c902634cfa5a06f29c3fb26e9f3 ./artix7/segbits_cmt_top_l_lower_b.db`](./artix7/segbits_cmt_top_l_lower_b.db)
* [`5e5166ef8643919dac09df0f904d212ff72b5c633152e16f7c89c2e650b3ac2b ./artix7/segbits_cmt_top_l_lower_b.origin_info.db`](./artix7/segbits_cmt_top_l_lower_b.origin_info.db)
* [`8c385232c1123d062d161054aca2c0089c9f3d89dac37f2fe35cbf18a2bc10a3 ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db)
* [`79e0d3fbf25cee9b675e356ad190b75e7063ded499a0a6155cc6bded3a36046a ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`8cd75b06942f3fefe474eb10ab4522043d5a52a2ee79c4555a7c89d1d6d11ecb ./artix7/segbits_cmt_top_r_lower_b.db`](./artix7/segbits_cmt_top_r_lower_b.db)
* [`0a36013e20bc01d66d1a73eb2594e67d57898efddeb8de046ebcf65eed259c27 ./artix7/segbits_cmt_top_r_lower_b.origin_info.db`](./artix7/segbits_cmt_top_r_lower_b.origin_info.db)
* [`05dd5d01374a8b40883444d33ea467e5e4363fc329e89402ee9618bde4d6752b ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db)
* [`1117a583fc1c9265aa6dcea7d32f363dd2c5ebe0e657f3a242c5fb0ceb8555fc ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`f67fcf1a6891fbc8a81f8c26403fe901e055b24e070277c5512a344635285bc2 ./artix7/segbits_cmt_top_l_lower_b.db`](./artix7/segbits_cmt_top_l_lower_b.db)
* [`dde4d2632c4fbf25cbab1891bbbc4355b63bde78c3f3646949238ffe60df11bb ./artix7/segbits_cmt_top_l_lower_b.origin_info.db`](./artix7/segbits_cmt_top_l_lower_b.origin_info.db)
* [`310d60fbc6081e27d8a6e06d659870acf9480ca28884813d804b5a2db26037ac ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db)
* [`eb47f86d4be61c185bb3f390d742a99ea9e4577d6ffa225c2c0f4835b4f8a920 ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`4a350d31eb78785fbd6b65044c02d623d6f787606c31a2f01a2efaf9cc2daad7 ./artix7/segbits_cmt_top_r_lower_b.db`](./artix7/segbits_cmt_top_r_lower_b.db)
* [`e712f48558e63ca7b078df3c357344b7977797a47b560f6b65bc953cfc93b815 ./artix7/segbits_cmt_top_r_lower_b.origin_info.db`](./artix7/segbits_cmt_top_r_lower_b.origin_info.db)
* [`6be3a84f654fa195720e2bde7e227711f9798afc48ec680cca57dd0810871cb9 ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db)
* [`882c5ed49538c83baed0003b8e3108e3c69d5324866c0566ce9f9160b5293f3f ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`81e0623ff13a253e3f9303de3d5dfbcf2fc92cf5cba277bd7de69e70c3c527e3 ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db)
* [`18cfd5dd8f59ca704cabeeddb2365486c755185b16a41714cc18ad08818c4f62 ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db)
* [`5297906aaafefd3be356682dc03cc4f8c85d0ec238a7d66bafc8b1b50a6c0c96 ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
* [`1f6d942f652416b24c7cdae7188144cc9a0778fc439d6e9f22ecec5d7833a391 ./artix7/segbits_dsp_r.origin_info.db`](./artix7/segbits_dsp_r.origin_info.db)
* [`43e958853f10cd658ae0af26f78469bdac9b2bd1abb5dbee83f4e9dfad40eaeb ./artix7/segbits_gtp_channel_0.db`](./artix7/segbits_gtp_channel_0.db)
* [`23f87065aec5f4f22dd0c3c0b5e73a50e13e28b3c494f07becf435f219030b30 ./artix7/segbits_gtp_channel_0.origin_info.db`](./artix7/segbits_gtp_channel_0.origin_info.db)
* [`fffd49cbef2952247233e2128b2752bf28f91f05e194495c6b044d125902191e ./artix7/segbits_gtp_channel_0_mid_left.db`](./artix7/segbits_gtp_channel_0_mid_left.db)
* [`3c51cce7195efee2655f0d8bdddbcebd9f7424fc531958a503ce700a209833f4 ./artix7/segbits_gtp_channel_0_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_left.origin_info.db)
* [`cf590acfaf96e259c464dd05b6d9728724941aff4926bf8bd57794c07c6931b7 ./artix7/segbits_gtp_channel_0_mid_right.db`](./artix7/segbits_gtp_channel_0_mid_right.db)
* [`a9c772ded5981040e503509abde4e9dc48619655c4dc75eb6950ca7641a70af3 ./artix7/segbits_gtp_channel_0_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_right.origin_info.db)
* [`ed22f29d7ea7180e50160b86da8c10e081ed9c3c399b7ff5b11f5e3c272d11a3 ./artix7/segbits_gtp_channel_1.db`](./artix7/segbits_gtp_channel_1.db)
* [`4c212e5ad3ac869e0b8e9927a97f32b75d5f5b166eb4a37af83738cb4ea2e95d ./artix7/segbits_gtp_channel_1.origin_info.db`](./artix7/segbits_gtp_channel_1.origin_info.db)
* [`efc28e01454541111a2517802814f6afd6c8d6f44d9ed9bbd79923e547cd2668 ./artix7/segbits_gtp_channel_1_mid_left.db`](./artix7/segbits_gtp_channel_1_mid_left.db)
* [`e3ff98c549a159a928e34d7bccca8a5c513401019d0f2c3f476f56322db4bd3e ./artix7/segbits_gtp_channel_1_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_left.origin_info.db)
* [`0d004b9755465b0d0c937f06d8ee3cfe83b6651810f766e8d2e63fbbccb6cab3 ./artix7/segbits_gtp_channel_1_mid_right.db`](./artix7/segbits_gtp_channel_1_mid_right.db)
* [`f15d88b953d32c73fbebe87a72bbae9a89b7e9f1e8fb53c45898a08f8c390dbc ./artix7/segbits_gtp_channel_1_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_right.origin_info.db)
* [`9a689135198dfacb307687415b086aef5a49e69eb39e331b6238e802907e3088 ./artix7/segbits_gtp_channel_2.db`](./artix7/segbits_gtp_channel_2.db)
* [`f5801a6809eb80627a630a988bc319d65e6b2fa2e56b2d612f07d98060cf6105 ./artix7/segbits_gtp_channel_2.origin_info.db`](./artix7/segbits_gtp_channel_2.origin_info.db)
* [`697dda8e24472fdfc92a94a31f9b6abac78e41b25fcb46303db9cef0016778f5 ./artix7/segbits_gtp_channel_2_mid_left.db`](./artix7/segbits_gtp_channel_2_mid_left.db)
* [`2fa375cc1c9b59a885e4c42764ac7fe816ec550df1dd694dbe55550e9ac495f5 ./artix7/segbits_gtp_channel_2_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_left.origin_info.db)
* [`e4eaec32de51c26916143be6fb83d005652b2dbdc82083f6dbfd6837dd8e6a46 ./artix7/segbits_gtp_channel_2_mid_right.db`](./artix7/segbits_gtp_channel_2_mid_right.db)
* [`d5bcd83a26fcc62bda3d7dffc5e54813fca2098c1a6c2294300f94c5f20b86ee ./artix7/segbits_gtp_channel_2_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_right.origin_info.db)
* [`7e13681d1a2435db935e800c9e8db3e17e1922c167cf470dc2172af733bc95ef ./artix7/segbits_gtp_channel_3.db`](./artix7/segbits_gtp_channel_3.db)
* [`2b7728a26ab3a151e08f27cfa88582d661fc96900c227d5ab6ab6a4ff362e358 ./artix7/segbits_gtp_channel_3.origin_info.db`](./artix7/segbits_gtp_channel_3.origin_info.db)
* [`2d8634163b632d2030104a8c090e0dd935cdd5afd78b7491d3bfd83e1e81887d ./artix7/segbits_gtp_channel_3_mid_left.db`](./artix7/segbits_gtp_channel_3_mid_left.db)
* [`290ca89106b61311978f9b7a9650fddb4dd5fb2b249612f66abdbe5a0a102f75 ./artix7/segbits_gtp_channel_3_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_left.origin_info.db)
* [`4cda734eeec2bfdcd7eab62628b5577277f820aae7ba01c85fa7dbe2389ada1d ./artix7/segbits_gtp_channel_3_mid_right.db`](./artix7/segbits_gtp_channel_3_mid_right.db)
* [`e8357be2f52886f7160aafa6495791ab890808f99a1e396077e17c30e49e6700 ./artix7/segbits_gtp_channel_3_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_right.origin_info.db)
* [`ea2df8227b92dbceb1073077f6453b6eb22eb6add9f330b93490915afd74ac2b ./artix7/segbits_gtp_common.db`](./artix7/segbits_gtp_common.db)
* [`1d1399b298c426c6e15ffb7c75ee1fa9887d3de1210e17a046022ffff4d45287 ./artix7/segbits_gtp_common.origin_info.db`](./artix7/segbits_gtp_common.origin_info.db)
* [`37afc4aaffef82bc42052353e4a68a483be81cc4b08e0847b4627a395fad6a24 ./artix7/segbits_gtp_common_mid_left.db`](./artix7/segbits_gtp_common_mid_left.db)
* [`c792735501a19ea5ffb9808844d8875c21f234e653ed51a33e8fb9c777b4f9ef ./artix7/segbits_gtp_common_mid_left.origin_info.db`](./artix7/segbits_gtp_common_mid_left.origin_info.db)
* [`1207c6985578749fe921840fe35187fd9043733059b463616ca9f8c189c6f81b ./artix7/segbits_gtp_common_mid_right.db`](./artix7/segbits_gtp_common_mid_right.db)
* [`2f4d78754b65f558fb7ec8c89641312ba45e68d434529885be26696204de066b ./artix7/segbits_gtp_common_mid_right.origin_info.db`](./artix7/segbits_gtp_common_mid_right.origin_info.db)
* [`a7a14326fcc4070e63a7586fc841eb8526c8eb4dc8d186cd9e8037f23350d546 ./artix7/segbits_gtp_channel_0.db`](./artix7/segbits_gtp_channel_0.db)
* [`91bafb14948c2a35dc049b415bd16c8cbc88fe7985538984f401f42d5d708970 ./artix7/segbits_gtp_channel_0.origin_info.db`](./artix7/segbits_gtp_channel_0.origin_info.db)
* [`e411594c01c7b33b332a9fd223cd7eceb4ef4e1473edede5cb6969609c0ff7f7 ./artix7/segbits_gtp_channel_0_mid_left.db`](./artix7/segbits_gtp_channel_0_mid_left.db)
* [`834de3b40c70aad66d37510e63e4f5a8a7ec50b89eb690333608dc56586986a3 ./artix7/segbits_gtp_channel_0_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_left.origin_info.db)
* [`aff9007b8c44a3a3549d7862057795f61f09be525befc258266343cdae056eb4 ./artix7/segbits_gtp_channel_0_mid_right.db`](./artix7/segbits_gtp_channel_0_mid_right.db)
* [`b1b96476b53065cdbff088078a6aa4b7818f02eeb797933fba4a028a8caeda06 ./artix7/segbits_gtp_channel_0_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_right.origin_info.db)
* [`226fea8aff6e578e4fc1295bb5cb4e223d80a8ef12730dbda743a449a15cdbe9 ./artix7/segbits_gtp_channel_1.db`](./artix7/segbits_gtp_channel_1.db)
* [`f273392d7d1d8628f5a627fa8373bfec2c8b24726b91a5185e5df00f22afff35 ./artix7/segbits_gtp_channel_1.origin_info.db`](./artix7/segbits_gtp_channel_1.origin_info.db)
* [`4e48837b97ca5240646cf2c5e1d0f680f6a3f0d23937645486d7e908e02bf28f ./artix7/segbits_gtp_channel_1_mid_left.db`](./artix7/segbits_gtp_channel_1_mid_left.db)
* [`2e7b8fe029b4422697b50d0703cbe55cdf1a7c4b398807e2c5999c01b41d88fb ./artix7/segbits_gtp_channel_1_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_left.origin_info.db)
* [`13b281ee07001a36cb7136b8570114c4e5cd5c4a40d18a2252418b0c7f92fa69 ./artix7/segbits_gtp_channel_1_mid_right.db`](./artix7/segbits_gtp_channel_1_mid_right.db)
* [`27df1513b6d254c558d1af092480833812a629f94859e9a9c42a137bc960e797 ./artix7/segbits_gtp_channel_1_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_right.origin_info.db)
* [`74f0502840985582c2b2b8d652cf2ecb28ab4dcf2bc52ccd10c1089e308a59f2 ./artix7/segbits_gtp_channel_2.db`](./artix7/segbits_gtp_channel_2.db)
* [`37a6bfebbb8e200208bb6bbc9510fc03b473b715826b3b9c65a56434e6fb491a ./artix7/segbits_gtp_channel_2.origin_info.db`](./artix7/segbits_gtp_channel_2.origin_info.db)
* [`9f3a29973fe4cc8f71c135a7ec304717c40b855a737cd1bba786e15b20c27184 ./artix7/segbits_gtp_channel_2_mid_left.db`](./artix7/segbits_gtp_channel_2_mid_left.db)
* [`6ca00c289c74f00acdc4a805035d24e6829d592c6ac27e96e66082874d16fab4 ./artix7/segbits_gtp_channel_2_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_left.origin_info.db)
* [`a9117aa88b0531d41dde96012eaf67309f705cc40927afcca92eefde3de9559f ./artix7/segbits_gtp_channel_2_mid_right.db`](./artix7/segbits_gtp_channel_2_mid_right.db)
* [`05e2e7b310ec7e0f08c4d48385ae5fcd26e05f348605705315562ccdb5ba062b ./artix7/segbits_gtp_channel_2_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_right.origin_info.db)
* [`9556bb97435b7f0ab59474677a047a549695248c83a83eccb0dcd35991bd737f ./artix7/segbits_gtp_channel_3.db`](./artix7/segbits_gtp_channel_3.db)
* [`0f4611c5c4b9ed91e29b139818296f3f64ac348b89c709dbc0ceea80d7ede844 ./artix7/segbits_gtp_channel_3.origin_info.db`](./artix7/segbits_gtp_channel_3.origin_info.db)
* [`d3c855bcf82086aa16d6eea3b7aeab7c19fa11c5916d64b8d82026627f934b7d ./artix7/segbits_gtp_channel_3_mid_left.db`](./artix7/segbits_gtp_channel_3_mid_left.db)
* [`f15bbdb97fb3018f3f53e96e9884672c97cf7496923b8075f02cede42e684bd3 ./artix7/segbits_gtp_channel_3_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_left.origin_info.db)
* [`e4f594f168b79d795c7aed60b92cc488d55c23df866d2eb3bf8f51e6d08704d8 ./artix7/segbits_gtp_channel_3_mid_right.db`](./artix7/segbits_gtp_channel_3_mid_right.db)
* [`db62bb5589de46e222495bc7689669686dc88d6e9aa51dbe78005f11578e2d24 ./artix7/segbits_gtp_channel_3_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_right.origin_info.db)
* [`9ec90c0988fcc69eb2a318038610778acab3a28391f968241850f9b59cf8365d ./artix7/segbits_gtp_common.db`](./artix7/segbits_gtp_common.db)
* [`db3370950e12398bfa641ccdf9c9f1522cdded52ee92e423ed9ae11244696819 ./artix7/segbits_gtp_common.origin_info.db`](./artix7/segbits_gtp_common.origin_info.db)
* [`4ed6df3458c728f66719885ceeded8deb1a0106c1157287cae44c9b97467ec4b ./artix7/segbits_gtp_common_mid_left.db`](./artix7/segbits_gtp_common_mid_left.db)
* [`5bb96a2ca569432f210d0a493953706bd945f8f1b39ee78d16eb0ade2efa80f2 ./artix7/segbits_gtp_common_mid_left.origin_info.db`](./artix7/segbits_gtp_common_mid_left.origin_info.db)
* [`f8dddd100f08cd5c801564666d875331c97d133319dfabad8285d94bd6de0e20 ./artix7/segbits_gtp_common_mid_right.db`](./artix7/segbits_gtp_common_mid_right.db)
* [`4cf9dd94cff081643450b89cdbf34d9c95370eeaedb7c9bc89172f9a3c4e229c ./artix7/segbits_gtp_common_mid_right.origin_info.db`](./artix7/segbits_gtp_common_mid_right.origin_info.db)
* [`0716b02a4d15baf2ae6ad06fd828e5e5d14bb6ca6ec4ed73da297863b66d9855 ./artix7/segbits_gtp_int_interface.db`](./artix7/segbits_gtp_int_interface.db)
* [`78df9b3f2977dddf280f5d0586d708bd635aa539d1e784fbc66cfde597670086 ./artix7/segbits_gtp_int_interface.origin_info.db`](./artix7/segbits_gtp_int_interface.origin_info.db)
* [`0cbdfb2e0e68dd296429972a70391d785011b7db5c720b605379d9812a45756c ./artix7/segbits_gtp_int_interface_l.db`](./artix7/segbits_gtp_int_interface_l.db)
@ -338,11 +348,11 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`53f0117e2838f3d7b71a9132f35aec36950a59186cfcd4cb9c39d86149ee28a0 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`c5e7dd396db511c4e0e8bf8b45e7632ae70a1589c028405f1e08e855314ffe53 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`ac84ef8991ce42d55bd72b28e4b26d7ec00f37c94a3d2fb0c77fa4e76ea28194 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`dc42429ae7563134fe7874b0aad2a563363496ff16a8423aa104321559fd82e0 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
* [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./artix7/segbits_lioi3.origin_info.db`](./artix7/segbits_lioi3.origin_info.db)
* [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./artix7/segbits_lioi3_tbytesrc.db`](./artix7/segbits_lioi3_tbytesrc.db)
@ -355,8 +365,8 @@ Results have checksums;
* [`ed58243250118f8cb3e7378e04b9861aa580db4991b7026b3edc439e0cfe0a77 ./artix7/segbits_pcie_int_interface_l.origin_info.db`](./artix7/segbits_pcie_int_interface_l.origin_info.db)
* [`0bc32fce572935289e5ac7b10c95fb96b78418270016546d42ab11276285343e ./artix7/segbits_pcie_int_interface_r.db`](./artix7/segbits_pcie_int_interface_r.db)
* [`ad36811e5e38c911473f2c3a6b805e7bb1f6186408bb6740c0dd906754762e3b ./artix7/segbits_pcie_int_interface_r.origin_info.db`](./artix7/segbits_pcie_int_interface_r.origin_info.db)
* [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
* [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
* [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
* [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
* [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./artix7/segbits_rioi3.db`](./artix7/segbits_rioi3.db)
* [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./artix7/segbits_rioi3.origin_info.db`](./artix7/segbits_rioi3.origin_info.db)
* [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./artix7/segbits_rioi3_tbytesrc.db`](./artix7/segbits_rioi3_tbytesrc.db)
@ -588,7 +598,7 @@ Results have checksums;
* [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
* [`9aaa711d29833f53f765caa74f1e43ac288803d9af8030ce1694b3e3137c4078 ./artix7/xc7a100t/node_wires.json`](./artix7/xc7a100t/node_wires.json)
* [`9cf701615e6f9ed6e89d86738f10ebb9d5bf1a233f1e3251315b2f9159f73391 ./artix7/xc7a100t/tileconn.json`](./artix7/xc7a100t/tileconn.json)
* [`40b95df1b59fd6cd9eb9c1be30ea756fc855c6fd960f9ce402485f44d154d782 ./artix7/xc7a100t/tilegrid.json`](./artix7/xc7a100t/tilegrid.json)
* [`1a06a603d9ffa72000924f1f97f32e6a24e5b4823945db479a0a84ed16a16480 ./artix7/xc7a100t/tilegrid.json`](./artix7/xc7a100t/tilegrid.json)
* [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa ./artix7/xc7a100tcsg324-1/package_pins.csv`](./artix7/xc7a100tcsg324-1/package_pins.csv)
* [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02 ./artix7/xc7a100tcsg324-1/part.json`](./artix7/xc7a100tcsg324-1/part.json)
* [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tcsg324-1/part.yaml`](./artix7/xc7a100tcsg324-1/part.yaml)
@ -600,7 +610,7 @@ Results have checksums;
* [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg676-1/part.yaml`](./artix7/xc7a100tfgg676-1/part.yaml)
* [`f25057c3f5f1273ab0e21bddafcb4499e219d84f7b5a00764b48bcb64dcd4bd2 ./artix7/xc7a200t/node_wires.json`](./artix7/xc7a200t/node_wires.json)
* [`bed4bf8553b0faa4a63964100e6b4a8b5f9ac77dbcac474a2d2cbe7240aa4617 ./artix7/xc7a200t/tileconn.json`](./artix7/xc7a200t/tileconn.json)
* [`95c95a4f20601c927854c0e7e56a5fcd9d90ae00df7d4ef9c7a273f65e15c9a2 ./artix7/xc7a200t/tilegrid.json`](./artix7/xc7a200t/tilegrid.json)
* [`9908f8b3411195a24249a79e4e060f5d34f45f22111cf2139a3ec06d683511a0 ./artix7/xc7a200t/tilegrid.json`](./artix7/xc7a200t/tilegrid.json)
* [`72dd638f5c8f6c36e74765915c01b2fa28e3c28b2c0afd91871ab7b0490a14f3 ./artix7/xc7a200tffg1156-1/package_pins.csv`](./artix7/xc7a200tffg1156-1/package_pins.csv)
* [`fe44ca57c10c7b804357ded2cdea392c008b7b4d5a82ad917fa3148a756e4e42 ./artix7/xc7a200tffg1156-1/part.json`](./artix7/xc7a200tffg1156-1/part.json)
* [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97 ./artix7/xc7a200tffg1156-1/part.yaml`](./artix7/xc7a200tffg1156-1/part.yaml)
@ -618,7 +628,7 @@ Results have checksums;
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tftg256-1/part.yaml`](./artix7/xc7a35tftg256-1/part.yaml)
* [`b60e01fef4c8c8d47fc646190d2d17fc63210cd0e82613624761e7463a7c35a6 ./artix7/xc7a50t/node_wires.json`](./artix7/xc7a50t/node_wires.json)
* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/xc7a50t/tileconn.json`](./artix7/xc7a50t/tileconn.json)
* [`930c3c75e7ecc929c0baaf13249e346092b78a474b54201271d107ed74d5b6ff ./artix7/xc7a50t/tilegrid.json`](./artix7/xc7a50t/tilegrid.json)
* [`84d4da13bc1bbe8da3f18ef4f514473de576c46e2d7e49ca89a58e9cab3cca3e ./artix7/xc7a50t/tilegrid.json`](./artix7/xc7a50t/tilegrid.json)
* [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805 ./artix7/xc7a50tfgg484-1/package_pins.csv`](./artix7/xc7a50tfgg484-1/package_pins.csv)
* [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tfgg484-1/part.json`](./artix7/xc7a50tfgg484-1/part.json)
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1/part.yaml`](./artix7/xc7a50tfgg484-1/part.yaml)
@ -628,7 +638,7 @@ Results have checksums;
### Settings
Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/kintex7.sh)
Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/kintex7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
@ -760,6 +770,10 @@ Results have checksums;
* [`f87e449ccf9c605acad950269bfe104bc3a45daf79c5b7fe21042169feb7a428 ./kintex7/ppips_lioi3_sing.db`](./kintex7/ppips_lioi3_sing.db)
* [`1046256199fd3c54a5f3ee7e5ec7fd72863882e01cc8da326e487c763159e2f8 ./kintex7/ppips_lioi3_tbytesrc.db`](./kintex7/ppips_lioi3_tbytesrc.db)
* [`b6255a5ec971695a0aadd4901f2021d839c20b9cff781b2fccc8f5e779295319 ./kintex7/ppips_lioi3_tbyteterm.db`](./kintex7/ppips_lioi3_tbyteterm.db)
* [`48ad9ebcaa48a039f5bcc9f6d5b4736be64976434ad79bc317e88c4f40b980aa ./kintex7/ppips_pcie_bot.db`](./kintex7/ppips_pcie_bot.db)
* [`38b7dd3cf1ef560f06933b501059b4d029e1625193038eba112424f9bff630c5 ./kintex7/ppips_pcie_int_interface_l.db`](./kintex7/ppips_pcie_int_interface_l.db)
* [`e998a9cc7b3ea7f185485133a97510a9ec73dfec574f3b8583eb968073f6a7d5 ./kintex7/ppips_pcie_int_interface_r.db`](./kintex7/ppips_pcie_int_interface_r.db)
* [`5684a64e33378f61f7b92cee7011c2fc4f85be16762919a86103dc8652c73d63 ./kintex7/ppips_pcie_top.db`](./kintex7/ppips_pcie_top.db)
* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`0cb9b3fb3c7627b1c16330f28fc212188441e087c30b0aefd506883676cde42f ./kintex7/segbits_bram_l.block_ram.origin_info.db`](./kintex7/segbits_bram_l.block_ram.origin_info.db)
* [`3957476dee60377d1050b3c2ad7c2fcdfc8319e3b8243f3ab61646c3596e02de ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
@ -788,14 +802,14 @@ Results have checksums;
* [`cf71a4438ae35cb2493b614e895e3d5cf577613a8d9c10cf1c566872a2ea9b4f ./kintex7/segbits_clk_hrow_bot_r.origin_info.db`](./kintex7/segbits_clk_hrow_bot_r.origin_info.db)
* [`89ca5e5d4e9bc222815bd81e6d94cbff6950b99e3d2e80ac677334dcde40e4c2 ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db)
* [`b9a1e70499c2597a6ae2381d3ab47780f2a69430073c87f2b639901d1f563e65 ./kintex7/segbits_clk_hrow_top_r.origin_info.db`](./kintex7/segbits_clk_hrow_top_r.origin_info.db)
* [`311bd38ca939dc8643afb130f77c3642f3a89c902634cfa5a06f29c3fb26e9f3 ./kintex7/segbits_cmt_top_l_lower_b.db`](./kintex7/segbits_cmt_top_l_lower_b.db)
* [`5e5166ef8643919dac09df0f904d212ff72b5c633152e16f7c89c2e650b3ac2b ./kintex7/segbits_cmt_top_l_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_l_lower_b.origin_info.db)
* [`3e33276e75c69bf622e1019c4bf4b8cf3f7bb8bebcdd500f16e160b49e5a6811 ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db)
* [`a8ba9d40de847f2175429ab3328c585242372124e499a520af2a2d8fb97d1550 ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`8cd75b06942f3fefe474eb10ab4522043d5a52a2ee79c4555a7c89d1d6d11ecb ./kintex7/segbits_cmt_top_r_lower_b.db`](./kintex7/segbits_cmt_top_r_lower_b.db)
* [`0a36013e20bc01d66d1a73eb2594e67d57898efddeb8de046ebcf65eed259c27 ./kintex7/segbits_cmt_top_r_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_r_lower_b.origin_info.db)
* [`ff3f5ed631016fb97d2e949d02b6a4eda93b5291a14b43cda962a93eeed88894 ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db)
* [`a6ea0f1abacda03e873459b43b5fda477a027904533d9bff94c0763bc2e30cef ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`f67fcf1a6891fbc8a81f8c26403fe901e055b24e070277c5512a344635285bc2 ./kintex7/segbits_cmt_top_l_lower_b.db`](./kintex7/segbits_cmt_top_l_lower_b.db)
* [`dde4d2632c4fbf25cbab1891bbbc4355b63bde78c3f3646949238ffe60df11bb ./kintex7/segbits_cmt_top_l_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_l_lower_b.origin_info.db)
* [`84747f20186b10b07c4d0e1ec18f2753a0d6c7d8cb71d55373b0b306e81721d9 ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db)
* [`7e121848ca4a34942ed87fa352db9b9ec41ddf4f420de235633367e6c0494962 ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`4a350d31eb78785fbd6b65044c02d623d6f787606c31a2f01a2efaf9cc2daad7 ./kintex7/segbits_cmt_top_r_lower_b.db`](./kintex7/segbits_cmt_top_r_lower_b.db)
* [`e712f48558e63ca7b078df3c357344b7977797a47b560f6b65bc953cfc93b815 ./kintex7/segbits_cmt_top_r_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_r_lower_b.origin_info.db)
* [`8f938e8163274dc2b39298c571bc6f35bc65ae6e1b6314803ccfc3bb1eb6cf4e ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db)
* [`cca311d41050776907fd73cf41d1933287b65dfd291f3072a6923ad0fc222067 ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`81e0623ff13a253e3f9303de3d5dfbcf2fc92cf5cba277bd7de69e70c3c527e3 ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db)
* [`18cfd5dd8f59ca704cabeeddb2365486c755185b16a41714cc18ad08818c4f62 ./kintex7/segbits_dsp_l.origin_info.db`](./kintex7/segbits_dsp_l.origin_info.db)
* [`5297906aaafefd3be356682dc03cc4f8c85d0ec238a7d66bafc8b1b50a6c0c96 ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db)
@ -811,19 +825,19 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`e1439b1e1f115bff678208fc65c78f4eb104aa59d2599adb5f5c9bda1c554e47 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`a8e4e0a62a4c109423a18d94aaf5a963f187c58ffe17e321088395dad6300b32 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`fdcb761e2a4274a34fb6cf5b9029c5c1d48fca331038366ac2fe0eedb0f635f5 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
* [`be03541f8c9a9fce4375588fc0747427c1bbbe3ca4fc27a5ae5e594435401d3d ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
* [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./kintex7/segbits_lioi3.origin_info.db`](./kintex7/segbits_lioi3.origin_info.db)
* [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./kintex7/segbits_lioi3_tbytesrc.db`](./kintex7/segbits_lioi3_tbytesrc.db)
* [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c ./kintex7/segbits_lioi3_tbytesrc.origin_info.db`](./kintex7/segbits_lioi3_tbytesrc.origin_info.db)
* [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b ./kintex7/segbits_lioi3_tbyteterm.db`](./kintex7/segbits_lioi3_tbyteterm.db)
* [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./kintex7/segbits_lioi3_tbyteterm.origin_info.db`](./kintex7/segbits_lioi3_tbyteterm.origin_info.db)
* [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db)
* [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db)
* [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db)
* [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db)
* [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./kintex7/segbits_rioi3.db`](./kintex7/segbits_rioi3.db)
* [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./kintex7/segbits_rioi3.origin_info.db`](./kintex7/segbits_rioi3.origin_info.db)
* [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./kintex7/segbits_rioi3_tbytesrc.db`](./kintex7/segbits_rioi3_tbytesrc.db)
@ -1007,7 +1021,7 @@ Results have checksums;
### Settings
Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/zynq7.sh)
Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/zynq7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
@ -1180,14 +1194,14 @@ Results have checksums;
* [`c913b6c8399b21d515063a9eba05749e06fcdb24fc40d7a4e1e009e91d7b9c02 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db)
* [`4c9c9effdaa6039eaa0df3c44056be0ceeaa1a34eab9134821f9f3e85f46738c ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db)
* [`dce4badb8750dc9ddf3db28e818df81abf4f2258c189891c35a427616c0cfc71 ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db)
* [`a4f42d6098b3aff51585f5ed58c0d13fb62019287172d98d73a5e0d8884134da ./zynq7/segbits_cmt_top_l_lower_b.db`](./zynq7/segbits_cmt_top_l_lower_b.db)
* [`fe4b0310db36eb87fef9901c790193b7077fbe216b1ba789ef65446c1e3b0b19 ./zynq7/segbits_cmt_top_l_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_l_lower_b.origin_info.db)
* [`3e33276e75c69bf622e1019c4bf4b8cf3f7bb8bebcdd500f16e160b49e5a6811 ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db)
* [`a8ba9d40de847f2175429ab3328c585242372124e499a520af2a2d8fb97d1550 ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`32cc74ba971e07fea70818fb15cd9b0e66e2cbd3f971ac68ca0e0f69337c11ca ./zynq7/segbits_cmt_top_r_lower_b.db`](./zynq7/segbits_cmt_top_r_lower_b.db)
* [`a526b7838198cdd3d9733b59aa41fc07ae55b1b3f7dfb1d6f9c3193c6384573a ./zynq7/segbits_cmt_top_r_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_r_lower_b.origin_info.db)
* [`ff3f5ed631016fb97d2e949d02b6a4eda93b5291a14b43cda962a93eeed88894 ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db)
* [`a6ea0f1abacda03e873459b43b5fda477a027904533d9bff94c0763bc2e30cef ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`a27bb7c254f63ac3cb9498e070d31f81b5763a31c395e94ad83f669692d18fa3 ./zynq7/segbits_cmt_top_l_lower_b.db`](./zynq7/segbits_cmt_top_l_lower_b.db)
* [`72ac477ff993341126a717a2bbfa2466e774119f3c145e6579f65b77ddba130f ./zynq7/segbits_cmt_top_l_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_l_lower_b.origin_info.db)
* [`84747f20186b10b07c4d0e1ec18f2753a0d6c7d8cb71d55373b0b306e81721d9 ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db)
* [`7e121848ca4a34942ed87fa352db9b9ec41ddf4f420de235633367e6c0494962 ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`316ec3a054a9bb371a9315aaf7e7ee2a351ef43098fc4510880e332d6286c90e ./zynq7/segbits_cmt_top_r_lower_b.db`](./zynq7/segbits_cmt_top_r_lower_b.db)
* [`db6e283a3f418b2e9c5c1946bdb7145183ed70b783018b0013ff04f676d37a47 ./zynq7/segbits_cmt_top_r_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_r_lower_b.origin_info.db)
* [`8f938e8163274dc2b39298c571bc6f35bc65ae6e1b6314803ccfc3bb1eb6cf4e ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db)
* [`cca311d41050776907fd73cf41d1933287b65dfd291f3072a6923ad0fc222067 ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`81e0623ff13a253e3f9303de3d5dfbcf2fc92cf5cba277bd7de69e70c3c527e3 ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db)
* [`18cfd5dd8f59ca704cabeeddb2365486c755185b16a41714cc18ad08818c4f62 ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db)
* [`5297906aaafefd3be356682dc03cc4f8c85d0ec238a7d66bafc8b1b50a6c0c96 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db)
@ -1203,19 +1217,19 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
* [`621e9074a0f82f119ee9746ff098e92505920351aa885f6106952abef368858b ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`66c9451631fbcde9a417fa19168a60a8bae3a991823d6773ffa1543396dde30e ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
* [`a55eef9788528b90c6433681387fd48064d4af45fe820d76e3016978e962f9d2 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`578bb187f19d5a0dff2e5dccda6fde721e03b25abbe4287fb48d563f484e0866 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
* [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./zynq7/segbits_lioi3.origin_info.db`](./zynq7/segbits_lioi3.origin_info.db)
* [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./zynq7/segbits_lioi3_tbytesrc.db`](./zynq7/segbits_lioi3_tbytesrc.db)
* [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c ./zynq7/segbits_lioi3_tbytesrc.origin_info.db`](./zynq7/segbits_lioi3_tbytesrc.origin_info.db)
* [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b ./zynq7/segbits_lioi3_tbyteterm.db`](./zynq7/segbits_lioi3_tbyteterm.db)
* [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./zynq7/segbits_lioi3_tbyteterm.origin_info.db`](./zynq7/segbits_lioi3_tbyteterm.origin_info.db)
* [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./zynq7/segbits_rioi3.db`](./zynq7/segbits_rioi3.db)
* [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./zynq7/segbits_rioi3.origin_info.db`](./zynq7/segbits_rioi3.origin_info.db)
* [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./zynq7/segbits_rioi3_tbytesrc.db`](./zynq7/segbits_rioi3_tbytesrc.db)

3645
artix7/cells_data/gtpe2_channel_attrs.json Normal file
View File

File diff suppressed because it is too large Load Diff

910
artix7/cells_data/gtpe2_channel_ports.json Normal file
View File

@ -0,0 +1,910 @@
{
"CFGRESET": {
"direction": "input",
"width": 1
},
"CLKRSVD0": {
"direction": "input",
"width": 1
},
"CLKRSVD1": {
"direction": "input",
"width": 1
},
"DMONFIFORESET": {
"direction": "input",
"width": 1
},
"DMONITORCLK": {
"direction": "input",
"width": 1
},
"DMONITOROUT": {
"direction": "output",
"width": 15
},
"DRPADDR": {
"direction": "input",
"width": 9
},
"DRPCLK": {
"direction": "input",
"width": 1
},
"DRPDI": {
"direction": "input",
"width": 16
},
"DRPDO": {
"direction": "output",
"width": 16
},
"DRPEN": {
"direction": "input",
"width": 1
},
"DRPRDY": {
"direction": "output",
"width": 1
},
"DRPWE": {
"direction": "input",
"width": 1
},
"EYESCANDATAERROR": {
"direction": "output",
"width": 1
},
"EYESCANMODE": {
"direction": "input",
"width": 1
},
"EYESCANRESET": {
"direction": "input",
"width": 1
},
"EYESCANTRIGGER": {
"direction": "input",
"width": 1
},
"GTPRXN": {
"direction": "input",
"width": 1
},
"GTPRXP": {
"direction": "input",
"width": 1
},
"GTPTXN": {
"direction": "output",
"width": 1
},
"GTPTXP": {
"direction": "output",
"width": 1
},
"GTRESETSEL": {
"direction": "input",
"width": 1
},
"GTRSVD": {
"direction": "input",
"width": 16
},
"GTRXRESET": {
"direction": "input",
"width": 1
},
"GTTXRESET": {
"direction": "input",
"width": 1
},
"LOOPBACK": {
"direction": "input",
"width": 3
},
"PCSRSVDIN": {
"direction": "input",
"width": 16
},
"PCSRSVDOUT": {
"direction": "output",
"width": 16
},
"PHYSTATUS": {
"direction": "output",
"width": 1
},
"PLL0CLK": {
"direction": "input",
"width": 1
},
"PLL0REFCLK": {
"direction": "input",
"width": 1
},
"PLL1CLK": {
"direction": "input",
"width": 1
},
"PLL1REFCLK": {
"direction": "input",
"width": 1
},
"PMARSVDIN0": {
"direction": "input",
"width": 1
},
"PMARSVDIN1": {
"direction": "input",
"width": 1
},
"PMARSVDIN2": {
"direction": "input",
"width": 1
},
"PMARSVDIN3": {
"direction": "input",
"width": 1
},
"PMARSVDIN4": {
"direction": "input",
"width": 1
},
"PMARSVDOUT0": {
"direction": "output",
"width": 1
},
"PMARSVDOUT1": {
"direction": "output",
"width": 1
},
"RESETOVRD": {
"direction": "input",
"width": 1
},
"RX8B10BEN": {
"direction": "input",
"width": 1
},
"RXADAPTSELTEST": {
"direction": "input",
"width": 14
},
"RXBUFRESET": {
"direction": "input",
"width": 1
},
"RXBUFSTATUS": {
"direction": "output",
"width": 3
},
"RXBYTEISALIGNED": {
"direction": "output",
"width": 1
},
"RXBYTEREALIGN": {
"direction": "output",
"width": 1
},
"RXCDRFREQRESET": {
"direction": "input",
"width": 1
},
"RXCDRHOLD": {
"direction": "input",
"width": 1
},
"RXCDRLOCK": {
"direction": "output",
"width": 1
},
"RXCDROVRDEN": {
"direction": "input",
"width": 1
},
"RXCDRRESET": {
"direction": "input",
"width": 1
},
"RXCDRRESETRSV": {
"direction": "input",
"width": 1
},
"RXCHANBONDSEQ": {
"direction": "output",
"width": 1
},
"RXCHANISALIGNED": {
"direction": "output",
"width": 1
},
"RXCHANREALIGN": {
"direction": "output",
"width": 1
},
"RXCHARISCOMMA": {
"direction": "output",
"width": 4
},
"RXCHARISK": {
"direction": "output",
"width": 4
},
"RXCHBONDEN": {
"direction": "input",
"width": 1
},
"RXCHBONDI": {
"direction": "input",
"width": 4
},
"RXCHBONDLEVEL": {
"direction": "input",
"width": 3
},
"RXCHBONDMASTER": {
"direction": "input",
"width": 1
},
"RXCHBONDO": {
"direction": "output",
"width": 4
},
"RXCHBONDSLAVE": {
"direction": "input",
"width": 1
},
"RXCLKCORCNT": {
"direction": "output",
"width": 2
},
"RXCOMINITDET": {
"direction": "output",
"width": 1
},
"RXCOMMADET": {
"direction": "output",
"width": 1
},
"RXCOMMADETEN": {
"direction": "input",
"width": 1
},
"RXCOMSASDET": {
"direction": "output",
"width": 1
},
"RXCOMWAKEDET": {
"direction": "output",
"width": 1
},
"RXDATA": {
"direction": "output",
"width": 32
},
"RXDATAVALID": {
"direction": "output",
"width": 2
},
"RXDDIEN": {
"direction": "input",
"width": 1
},
"RXDFEXYDEN": {
"direction": "input",
"width": 1
},
"RXDISPERR": {
"direction": "output",
"width": 4
},
"RXDLYBYPASS": {
"direction": "input",
"width": 1
},
"RXDLYEN": {
"direction": "input",
"width": 1
},
"RXDLYOVRDEN": {
"direction": "input",
"width": 1
},
"RXDLYSRESET": {
"direction": "input",
"width": 1
},
"RXDLYSRESETDONE": {
"direction": "output",
"width": 1
},
"RXELECIDLE": {
"direction": "output",
"width": 1
},
"RXELECIDLEMODE": {
"direction": "input",
"width": 2
},
"RXGEARBOXSLIP": {
"direction": "input",
"width": 1
},
"RXHEADER": {
"direction": "output",
"width": 3
},
"RXHEADERVALID": {
"direction": "output",
"width": 1
},
"RXLPMHFHOLD": {
"direction": "input",
"width": 1
},
"RXLPMHFOVRDEN": {
"direction": "input",
"width": 1
},
"RXLPMLFHOLD": {
"direction": "input",
"width": 1
},
"RXLPMLFOVRDEN": {
"direction": "input",
"width": 1
},
"RXLPMOSINTNTRLEN": {
"direction": "input",
"width": 1
},
"RXLPMRESET": {
"direction": "input",
"width": 1
},
"RXMCOMMAALIGNEN": {
"direction": "input",
"width": 1
},
"RXNOTINTABLE": {
"direction": "output",
"width": 4
},
"RXOOBRESET": {
"direction": "input",
"width": 1
},
"RXOSCALRESET": {
"direction": "input",
"width": 1
},
"RXOSHOLD": {
"direction": "input",
"width": 1
},
"RXOSINTCFG": {
"direction": "input",
"width": 4
},
"RXOSINTDONE": {
"direction": "output",
"width": 1
},
"RXOSINTEN": {
"direction": "input",
"width": 1
},
"RXOSINTHOLD": {
"direction": "input",
"width": 1
},
"RXOSINTID0": {
"direction": "input",
"width": 4
},
"RXOSINTNTRLEN": {
"direction": "input",
"width": 1
},
"RXOSINTOVRDEN": {
"direction": "input",
"width": 1
},
"RXOSINTPD": {
"direction": "input",
"width": 1
},
"RXOSINTSTARTED": {
"direction": "output",
"width": 1
},
"RXOSINTSTROBE": {
"direction": "input",
"width": 1
},
"RXOSINTSTROBEDONE": {
"direction": "output",
"width": 1
},
"RXOSINTSTROBESTARTED": {
"direction": "output",
"width": 1
},
"RXOSINTTESTOVRDEN": {
"direction": "input",
"width": 1
},
"RXOSOVRDEN": {
"direction": "input",
"width": 1
},
"RXOUTCLK": {
"direction": "output",
"width": 1
},
"RXOUTCLKFABRIC": {
"direction": "output",
"width": 1
},
"RXOUTCLKPCS": {
"direction": "output",
"width": 1
},
"RXOUTCLKSEL": {
"direction": "input",
"width": 3
},
"RXPCOMMAALIGNEN": {
"direction": "input",
"width": 1
},
"RXPCSRESET": {
"direction": "input",
"width": 1
},
"RXPD": {
"direction": "input",
"width": 2
},
"RXPHALIGN": {
"direction": "input",
"width": 1
},
"RXPHALIGNDONE": {
"direction": "output",
"width": 1
},
"RXPHALIGNEN": {
"direction": "input",
"width": 1
},
"RXPHDLYPD": {
"direction": "input",
"width": 1
},
"RXPHDLYRESET": {
"direction": "input",
"width": 1
},
"RXPHMONITOR": {
"direction": "output",
"width": 5
},
"RXPHOVRDEN": {
"direction": "input",
"width": 1
},
"RXPHSLIPMONITOR": {
"direction": "output",
"width": 5
},
"RXPMARESET": {
"direction": "input",
"width": 1
},
"RXPMARESETDONE": {
"direction": "output",
"width": 1
},
"RXPOLARITY": {
"direction": "input",
"width": 1
},
"RXPRBSCNTRESET": {
"direction": "input",
"width": 1
},
"RXPRBSERR": {
"direction": "output",
"width": 1
},
"RXPRBSSEL": {
"direction": "input",
"width": 3
},
"RXRATE": {
"direction": "input",
"width": 3
},
"RXRATEDONE": {
"direction": "output",
"width": 1
},
"RXRATEMODE": {
"direction": "input",
"width": 1
},
"RXRESETDONE": {
"direction": "output",
"width": 1
},
"RXSLIDE": {
"direction": "input",
"width": 1
},
"RXSTARTOFSEQ": {
"direction": "output",
"width": 2
},
"RXSTATUS": {
"direction": "output",
"width": 3
},
"RXSYNCALLIN": {
"direction": "input",
"width": 1
},
"RXSYNCDONE": {
"direction": "output",
"width": 1
},
"RXSYNCIN": {
"direction": "input",
"width": 1
},
"RXSYNCMODE": {
"direction": "input",
"width": 1
},
"RXSYNCOUT": {
"direction": "output",
"width": 1
},
"RXSYSCLKSEL": {
"direction": "input",
"width": 2
},
"RXUSERRDY": {
"direction": "input",
"width": 1
},
"RXUSRCLK": {
"direction": "input",
"width": 1
},
"RXUSRCLK2": {
"direction": "input",
"width": 1
},
"RXVALID": {
"direction": "output",
"width": 1
},
"SETERRSTATUS": {
"direction": "input",
"width": 1
},
"SIGVALIDCLK": {
"direction": "input",
"width": 1
},
"TSTIN": {
"direction": "input",
"width": 20
},
"TX8B10BBYPASS": {
"direction": "input",
"width": 4
},
"TX8B10BEN": {
"direction": "input",
"width": 1
},
"TXBUFDIFFCTRL": {
"direction": "input",
"width": 3
},
"TXBUFSTATUS": {
"direction": "output",
"width": 2
},
"TXCHARDISPMODE": {
"direction": "input",
"width": 4
},
"TXCHARDISPVAL": {
"direction": "input",
"width": 4
},
"TXCHARISK": {
"direction": "input",
"width": 4
},
"TXCOMFINISH": {
"direction": "output",
"width": 1
},
"TXCOMINIT": {
"direction": "input",
"width": 1
},
"TXCOMSAS": {
"direction": "input",
"width": 1
},
"TXCOMWAKE": {
"direction": "input",
"width": 1
},
"TXDATA": {
"direction": "input",
"width": 32
},
"TXDEEMPH": {
"direction": "input",
"width": 1
},
"TXDETECTRX": {
"direction": "input",
"width": 1
},
"TXDIFFCTRL": {
"direction": "input",
"width": 4
},
"TXDIFFPD": {
"direction": "input",
"width": 1
},
"TXDLYBYPASS": {
"direction": "input",
"width": 1
},
"TXDLYEN": {
"direction": "input",
"width": 1
},
"TXDLYHOLD": {
"direction": "input",
"width": 1
},
"TXDLYOVRDEN": {
"direction": "input",
"width": 1
},
"TXDLYSRESET": {
"direction": "input",
"width": 1
},
"TXDLYSRESETDONE": {
"direction": "output",
"width": 1
},
"TXDLYUPDOWN": {
"direction": "input",
"width": 1
},
"TXELECIDLE": {
"direction": "input",
"width": 1
},
"TXGEARBOXREADY": {
"direction": "output",
"width": 1
},
"TXHEADER": {
"direction": "input",
"width": 3
},
"TXINHIBIT": {
"direction": "input",
"width": 1
},
"TXMAINCURSOR": {
"direction": "input",
"width": 7
},
"TXMARGIN": {
"direction": "input",
"width": 3
},
"TXOUTCLK": {
"direction": "output",
"width": 1
},
"TXOUTCLKFABRIC": {
"direction": "output",
"width": 1
},
"TXOUTCLKPCS": {
"direction": "output",
"width": 1
},
"TXOUTCLKSEL": {
"direction": "input",
"width": 3
},
"TXPCSRESET": {
"direction": "input",
"width": 1
},
"TXPD": {
"direction": "input",
"width": 2
},
"TXPDELECIDLEMODE": {
"direction": "input",
"width": 1
},
"TXPHALIGN": {
"direction": "input",
"width": 1
},
"TXPHALIGNDONE": {
"direction": "output",
"width": 1
},
"TXPHALIGNEN": {
"direction": "input",
"width": 1
},
"TXPHDLYPD": {
"direction": "input",
"width": 1
},
"TXPHDLYRESET": {
"direction": "input",
"width": 1
},
"TXPHDLYTSTCLK": {
"direction": "input",
"width": 1
},
"TXPHINIT": {
"direction": "input",
"width": 1
},
"TXPHINITDONE": {
"direction": "output",
"width": 1
},
"TXPHOVRDEN": {
"direction": "input",
"width": 1
},
"TXPIPPMEN": {
"direction": "input",
"width": 1
},
"TXPIPPMOVRDEN": {
"direction": "input",
"width": 1
},
"TXPIPPMPD": {
"direction": "input",
"width": 1
},
"TXPIPPMSEL": {
"direction": "input",
"width": 1
},
"TXPIPPMSTEPSIZE": {
"direction": "input",
"width": 5
},
"TXPISOPD": {
"direction": "input",
"width": 1
},
"TXPMARESET": {
"direction": "input",
"width": 1
},
"TXPMARESETDONE": {
"direction": "output",
"width": 1
},
"TXPOLARITY": {
"direction": "input",
"width": 1
},
"TXPOSTCURSOR": {
"direction": "input",
"width": 5
},
"TXPOSTCURSORINV": {
"direction": "input",
"width": 1
},
"TXPRBSFORCEERR": {
"direction": "input",
"width": 1
},
"TXPRBSSEL": {
"direction": "input",
"width": 3
},
"TXPRECURSOR": {
"direction": "input",
"width": 5
},
"TXPRECURSORINV": {
"direction": "input",
"width": 1
},
"TXRATE": {
"direction": "input",
"width": 3
},
"TXRATEDONE": {
"direction": "output",
"width": 1
},
"TXRATEMODE": {
"direction": "input",
"width": 1
},
"TXRESETDONE": {
"direction": "output",
"width": 1
},
"TXSEQUENCE": {
"direction": "input",
"width": 7
},
"TXSTARTSEQ": {
"direction": "input",
"width": 1
},
"TXSWING": {
"direction": "input",
"width": 1
},
"TXSYNCALLIN": {
"direction": "input",
"width": 1
},
"TXSYNCDONE": {
"direction": "output",
"width": 1
},
"TXSYNCIN": {
"direction": "input",
"width": 1
},
"TXSYNCMODE": {
"direction": "input",
"width": 1
},
"TXSYNCOUT": {
"direction": "output",
"width": 1
},
"TXSYSCLKSEL": {
"direction": "input",
"width": 2
},
"TXUSERRDY": {
"direction": "input",
"width": 1
},
"TXUSRCLK": {
"direction": "input",
"width": 1
},
"TXUSRCLK2": {
"direction": "input",
"width": 1
}
}

177
artix7/cells_data/gtpe2_common_attrs.json Normal file
View File

@ -0,0 +1,177 @@
{
"BIAS_CFG": {
"digits": 64,
"type": "BIN",
"values": [
18445618199572250625
]
},
"COMMON_CFG": {
"digits": 32,
"type": "BIN",
"values": [
4294836225
]
},
"PLL0_CFG": {
"digits": 27,
"type": "BIN",
"values": [
134150145
]
},
"PLL0_DMON_CFG": {
"digits": 1,
"type": "BIN",
"values": [
1
]
},
"PLL0_FBDIV": {
"digits": 6,
"encoding": [
16,
0,
1,
2,
3
],
"type": "INT",
"values": [
1,
2,
3,
4,
5
]
},
"PLL0_FBDIV_45": {
"digits": 1,
"encoding": [
0,
1
],
"type": "INT",
"values": [
4,
5
]
},
"PLL0_INIT_CFG": {
"digits": 24,
"type": "BIN",
"values": [
16711425
]
},
"PLL0_LOCK_CFG": {
"digits": 9,
"type": "BIN",
"values": [
511
]
},
"PLL0_REFCLK_DIV": {
"digits": 5,
"encoding": [
16,
0
],
"type": "INT",
"values": [
1,
2
]
},
"PLL1_CFG": {
"digits": 27,
"type": "BIN",
"values": [
134150145
]
},
"PLL1_DMON_CFG": {
"digits": 1,
"type": "BIN",
"values": [
1
]
},
"PLL1_FBDIV": {
"digits": 6,
"encoding": [
16,
0,
1,
2,
3
],
"type": "INT",
"values": [
1,
2,
3,
4,
5
]
},
"PLL1_FBDIV_45": {
"digits": 1,
"encoding": [
0,
1
],
"type": "INT",
"values": [
4,
5
]
},
"PLL1_INIT_CFG": {
"digits": 24,
"type": "BIN",
"values": [
16711425
]
},
"PLL1_LOCK_CFG": {
"digits": 9,
"type": "BIN",
"values": [
511
]
},
"PLL1_REFCLK_DIV": {
"digits": 5,
"encoding": [
16,
0
],
"type": "INT",
"values": [
1,
2
]
},
"PLL_CLKOUT_CFG": {
"digits": 8,
"type": "BIN",
"values": [
255
]
},
"RSVD_ATTR0": {
"digits": 16,
"type": "BIN",
"values": [
65535
]
},
"RSVD_ATTR1": {
"digits": 16,
"type": "BIN",
"values": [
65535
]
}
}

186
artix7/cells_data/gtpe2_common_ports.json Normal file
View File

@ -0,0 +1,186 @@
{
"BGBYPASSB": {
"direction": "input",
"width": 1
},
"BGMONITORENB": {
"direction": "input",
"width": 1
},
"BGPDB": {
"direction": "input",
"width": 1
},
"BGRCALOVRD": {
"direction": "input",
"width": 5
},
"BGRCALOVRDENB": {
"direction": "input",
"width": 1
},
"DMONITOROUT": {
"direction": "output",
"width": 8
},
"DRPADDR": {
"direction": "input",
"width": 8
},
"DRPCLK": {
"direction": "input",
"width": 1
},
"DRPDI": {
"direction": "input",
"width": 16
},
"DRPDO": {
"direction": "output",
"width": 16
},
"DRPEN": {
"direction": "input",
"width": 1
},
"DRPRDY": {
"direction": "output",
"width": 1
},
"DRPWE": {
"direction": "input",
"width": 1
},
"GTGREFCLK0": {
"direction": "input",
"width": 1
},
"GTGREFCLK1": {
"direction": "input",
"width": 1
},
"GTREFCLK0": {
"direction": "input",
"width": 1
},
"GTREFCLK1": {
"direction": "input",
"width": 1
},
"GTWESTREFCLK0": {
"direction": "input",
"width": 1
},
"GTWESTREFCLK1": {
"direction": "input",
"width": 1
},
"PLL0FBCLKLOST": {
"direction": "output",
"width": 1
},
"PLL0LOCK": {
"direction": "output",
"width": 1
},
"PLL0LOCKDETCLK": {
"direction": "input",
"width": 1
},
"PLL0LOCKEN": {
"direction": "input",
"width": 1
},
"PLL0OUTCLK": {
"direction": "output",
"width": 1
},
"PLL0OUTREFCLK": {
"direction": "output",
"width": 1
},
"PLL0PD": {
"direction": "input",
"width": 1
},
"PLL0REFCLKLOST": {
"direction": "output",
"width": 1
},
"PLL0REFCLKSEL": {
"direction": "input",
"width": 3
},
"PLL0RESET": {
"direction": "input",
"width": 1
},
"PLL1FBCLKLOST": {
"direction": "output",
"width": 1
},
"PLL1LOCK": {
"direction": "output",
"width": 1
},
"PLL1LOCKDETCLK": {
"direction": "input",
"width": 1
},
"PLL1LOCKEN": {
"direction": "input",
"width": 1
},
"PLL1OUTCLK": {
"direction": "output",
"width": 1
},
"PLL1OUTREFCLK": {
"direction": "output",
"width": 1
},
"PLL1PD": {
"direction": "input",
"width": 1
},
"PLL1REFCLKLOST": {
"direction": "output",
"width": 1
},
"PLL1REFCLKSEL": {
"direction": "input",
"width": 3
},
"PLL1RESET": {
"direction": "input",
"width": 1
},
"PLLRSVD1": {
"direction": "input",
"width": 16
},
"PLLRSVD2": {
"direction": "input",
"width": 5
},
"PMARSVD": {
"direction": "input",
"width": 8
},
"PMARSVDOUT": {
"direction": "output",
"width": 16
},
"RCALENB": {
"direction": "input",
"width": 1
},
"REFCLKOUTMONITOR0": {
"direction": "output",
"width": 1
},
"REFCLKOUTMONITOR1": {
"direction": "output",
"width": 1
}
}

10
artix7/harness/arty-a7/pmod/design.json
View File

@ -1078,8 +1078,8 @@
"INT_R_X1Y116.WW2BEG2.NN6END3",
"INT_R_X23Y46.IMUX24.SE2END0",
"LIOB33_SING_X0Y99.IOB_Y1.IN_TERM.NONE",
"LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_SING_X0Y99.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_SING_X0Y99.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y3.IOB_Y0.IN_TERM.NONE",
@ -1128,8 +1128,8 @@
"LIOB33_X0Y51.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y51.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y51.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y51.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y51.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y53.IOB_Y0.IN_TERM.NONE",
@ -1138,8 +1138,8 @@
"LIOB33_X0Y53.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y53.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y53.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y53.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y53.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y75.IOB_Y0.IN_TERM.NONE",
@ -1148,8 +1148,8 @@
"LIOB33_X0Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y75.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y75.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y75.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y77.IOB_Y0.IN_TERM.NONE",
@ -1158,8 +1158,8 @@
"LIOB33_X0Y77.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y77.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y77.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y77.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y77.IOB_Y1.PULLTYPE.NONE",
"LIOI3_SING_X0Y99.IDELAY_Y1.IDELAY_TYPE_FIXED",

8
artix7/harness/arty-a7/swbut/design.json
View File

@ -892,8 +892,8 @@
"LIOB33_X0Y123.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y123.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y123.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y123.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y123.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y125.IOB_Y0.IN_TERM.NONE",
@ -902,8 +902,8 @@
"LIOB33_X0Y125.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y125.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y125.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y125.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y125.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y127.IOB_Y0.IN_TERM.NONE",
@ -912,16 +912,16 @@
"LIOB33_X0Y127.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y127.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y127.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y127.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y127.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y137.IOB_Y0.IN_TERM.NONE",
"LIOB33_X0Y137.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y137.IOB_Y0.PULLTYPE.PULLDOWN",
"LIOB33_X0Y137.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y137.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y137.IOB_Y1.PULLTYPE.NONE",
"LIOI3_TBYTETERM_X0Y137.IDELAY_Y0.IDELAY_TYPE_FIXED",

2
artix7/harness/arty-a7/uart/design.json
View File

@ -371,8 +371,8 @@
"LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y121.IOB_Y0.PULLTYPE.PULLDOWN",
"LIOB33_X0Y121.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y121.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y121.IOB_Y1.PULLTYPE.NONE",
"LIOI3_X0Y1.IDELAY_Y0.IDELAY_TYPE_FIXED",

16
artix7/harness/basys3/swbut/design.json
View File

@ -3532,8 +3532,8 @@
"LIOB33_X0Y5.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y5.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y5.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y7.IOB_Y0.IN_TERM.NONE",
@ -3542,8 +3542,8 @@
"LIOB33_X0Y7.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y7.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y7.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y9.IOB_Y0.IN_TERM.NONE",
@ -3552,8 +3552,8 @@
"LIOB33_X0Y9.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y9.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y9.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y11.IOB_Y0.IN_TERM.NONE",
@ -3562,8 +3562,8 @@
"LIOB33_X0Y11.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y11.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y11.IOB_Y1.IN_TERM.NONE",
"LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"LIOB33_X0Y11.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y11.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y17.IOB_Y0.IN_TERM.NONE",
@ -3772,8 +3772,8 @@
"RIOB33_X43Y39.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y39.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y39.IOB_Y1.IN_TERM.NONE",
"RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"RIOB33_X43Y39.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y39.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y43.IOB_Y0.IN_TERM.NONE",
@ -3782,8 +3782,8 @@
"RIOB33_X43Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y43.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y43.IOB_Y1.IN_TERM.NONE",
"RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"RIOB33_X43Y43.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y43.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y45.IOB_Y0.IN_TERM.NONE",
@ -3792,8 +3792,8 @@
"RIOB33_X43Y45.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y45.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y45.IOB_Y1.IN_TERM.NONE",
"RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"RIOB33_X43Y45.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y45.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y47.IOB_Y0.IN_TERM.NONE",
@ -3802,8 +3802,8 @@
"RIOB33_X43Y47.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y47.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y47.IOB_Y1.IN_TERM.NONE",
"RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY",
"RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
"RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY",
"RIOB33_X43Y47.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y47.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y61.IOB_Y0.IN_TERM.NONE",

180
artix7/ppips_gtp_channel_0.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_0_mid_left.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_0_mid_right.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_1.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_1_mid_left.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_1_mid_right.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_2.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_2_mid_left.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_2_mid_right.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_3.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_3_mid_left.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

180
artix7/ppips_gtp_channel_3_mid_right.db
View File

@ -10,6 +10,10 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always
@ -36,6 +40,7 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always
@ -47,6 +52,8 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always
@ -81,6 +88,9 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always
@ -344,3 +354,173 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always
GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always

77
artix7/ppips_gtp_common.db
View File

@ -1,5 +1,15 @@
GTP_COMMON.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always
GTP_COMMON.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always
GTP_COMMON.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always
GTP_COMMON.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always
GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always
GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always
GTP_COMMON.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always
GTP_COMMON.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always
GTP_COMMON.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always
GTP_COMMON.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always
GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always
GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always
GTP_COMMON.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always
GTP_COMMON.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always
GTP_COMMON.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always
@ -7,6 +17,16 @@ GTP_COMMON.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always
GTP_COMMON.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always
GTP_COMMON.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always
GTP_COMMON.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK0.GTPE2_COMMON_RXOUTCLK_0 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK1.GTPE2_COMMON_RXOUTCLK_1 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK2.GTPE2_COMMON_TXOUTCLK_0 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK3.GTPE2_COMMON_TXOUTCLK_1 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK4.IBUFDS_GTPE2_0_MGTCLKOUT always
GTP_COMMON.GTPE2_COMMON_MGT_CLK5.IBUFDS_GTPE2_1_MGTCLKOUT always
GTP_COMMON.GTPE2_COMMON_MGT_CLK6.GTPE2_COMMON_RXOUTCLK_2 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK7.GTPE2_COMMON_RXOUTCLK_3 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK8.GTPE2_COMMON_TXOUTCLK_2 always
GTP_COMMON.GTPE2_COMMON_MGT_CLK9.GTPE2_COMMON_TXOUTCLK_3 always
GTP_COMMON.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always
GTP_COMMON.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always
GTP_COMMON.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always
@ -47,12 +67,18 @@ GTP_COMMON.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always
GTP_COMMON.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always
GTP_COMMON.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always
GTP_COMMON.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always
GTP_COMMON.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always
GTP_COMMON.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always
GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always
GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always
GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always
GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always
GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always
GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always
GTP_COMMON.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always
GTP_COMMON.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always
GTP_COMMON.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always
GTP_COMMON.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always
GTP_COMMON.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always
GTP_COMMON.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always
@ -82,3 +108,54 @@ GTP_COMMON.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always
GTP_COMMON.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always
GTP_COMMON.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always
GTP_COMMON.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always
GTP_COMMON.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always
GTP_COMMON.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always
GTP_COMMON.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always

67
artix7/ppips_gtp_common_mid_left.db
View File

@ -1,5 +1,15 @@
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always
@ -47,12 +57,18 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always
@ -82,3 +98,54 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always
GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always

67
artix7/ppips_gtp_common_mid_right.db
View File

@ -1,5 +1,15 @@
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always
@ -47,12 +57,18 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always
@ -82,3 +98,54 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always
GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always

72
artix7/ppips_gtp_int_interface.db
View File

@ -1,3 +1,75 @@
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY0.GTPE2_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY1.GTPE2_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY2.GTPE2_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY3.GTPE2_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY4.GTPE2_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY5.GTPE2_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY6.GTPE2_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY7.GTPE2_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY8.GTPE2_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY9.GTPE2_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY10.GTPE2_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY11.GTPE2_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY12.GTPE2_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY13.GTPE2_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY14.GTPE2_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY15.GTPE2_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY16.GTPE2_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY17.GTPE2_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY18.GTPE2_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY19.GTPE2_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY20.GTPE2_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY21.GTPE2_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY22.GTPE2_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY23.GTPE2_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY24.GTPE2_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY25.GTPE2_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY26.GTPE2_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY27.GTPE2_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY28.GTPE2_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY29.GTPE2_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY30.GTPE2_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY31.GTPE2_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY32.GTPE2_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY33.GTPE2_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY34.GTPE2_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY35.GTPE2_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY36.GTPE2_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY37.GTPE2_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY38.GTPE2_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY39.GTPE2_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY40.GTPE2_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY41.GTPE2_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY42.GTPE2_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY43.GTPE2_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY44.GTPE2_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY45.GTPE2_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY46.GTPE2_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY47.GTPE2_INT_INTERFACE_IMUX47 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT0.GTPE2_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT1.GTPE2_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT2.GTPE2_INT_INTERFACE_IMUX2 always

120
artix7/ppips_gtp_int_interface_l.db Normal file
View File

@ -0,0 +1,120 @@
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS0.GTPE2_INT_INTERFACE_LOGIC_OUTS_B0 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS1.GTPE2_INT_INTERFACE_LOGIC_OUTS_B1 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS2.GTPE2_INT_INTERFACE_LOGIC_OUTS_B2 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS3.GTPE2_INT_INTERFACE_LOGIC_OUTS_B3 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS4.GTPE2_INT_INTERFACE_LOGIC_OUTS_B4 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS5.GTPE2_INT_INTERFACE_LOGIC_OUTS_B5 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS6.GTPE2_INT_INTERFACE_LOGIC_OUTS_B6 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS7.GTPE2_INT_INTERFACE_LOGIC_OUTS_B7 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS8.GTPE2_INT_INTERFACE_LOGIC_OUTS_B8 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS9.GTPE2_INT_INTERFACE_LOGIC_OUTS_B9 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS10.GTPE2_INT_INTERFACE_LOGIC_OUTS_B10 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS11.GTPE2_INT_INTERFACE_LOGIC_OUTS_B11 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS12.GTPE2_INT_INTERFACE_LOGIC_OUTS_B12 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS13.GTPE2_INT_INTERFACE_LOGIC_OUTS_B13 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS14.GTPE2_INT_INTERFACE_LOGIC_OUTS_B14 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS15.GTPE2_INT_INTERFACE_LOGIC_OUTS_B15 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS16.GTPE2_INT_INTERFACE_LOGIC_OUTS_B16 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS17.GTPE2_INT_INTERFACE_LOGIC_OUTS_B17 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS18.GTPE2_INT_INTERFACE_LOGIC_OUTS_B18 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS19.GTPE2_INT_INTERFACE_LOGIC_OUTS_B19 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS20.GTPE2_INT_INTERFACE_LOGIC_OUTS_B20 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS21.GTPE2_INT_INTERFACE_LOGIC_OUTS_B21 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS22.GTPE2_INT_INTERFACE_LOGIC_OUTS_B22 always
GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS23.GTPE2_INT_INTERFACE_LOGIC_OUTS_B23 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY0.GTPE2_LEFT_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY1.GTPE2_LEFT_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY2.GTPE2_LEFT_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY3.GTPE2_LEFT_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY4.GTPE2_LEFT_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY5.GTPE2_LEFT_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY6.GTPE2_LEFT_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY7.GTPE2_LEFT_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY8.GTPE2_LEFT_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY9.GTPE2_LEFT_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY10.GTPE2_LEFT_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY11.GTPE2_LEFT_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY12.GTPE2_LEFT_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY13.GTPE2_LEFT_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY14.GTPE2_LEFT_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY15.GTPE2_LEFT_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY16.GTPE2_LEFT_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY17.GTPE2_LEFT_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY18.GTPE2_LEFT_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY19.GTPE2_LEFT_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY20.GTPE2_LEFT_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY21.GTPE2_LEFT_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY22.GTPE2_LEFT_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY23.GTPE2_LEFT_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY24.GTPE2_LEFT_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY25.GTPE2_LEFT_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY26.GTPE2_LEFT_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY27.GTPE2_LEFT_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY28.GTPE2_LEFT_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY29.GTPE2_LEFT_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY30.GTPE2_LEFT_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY31.GTPE2_LEFT_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY32.GTPE2_LEFT_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY33.GTPE2_LEFT_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY34.GTPE2_LEFT_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY35.GTPE2_LEFT_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY36.GTPE2_LEFT_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY37.GTPE2_LEFT_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY38.GTPE2_LEFT_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY39.GTPE2_LEFT_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY40.GTPE2_LEFT_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY41.GTPE2_LEFT_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY42.GTPE2_LEFT_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY43.GTPE2_LEFT_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY44.GTPE2_LEFT_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY45.GTPE2_LEFT_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY46.GTPE2_LEFT_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY47.GTPE2_LEFT_INT_INTERFACE_IMUX47 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT0.GTPE2_LEFT_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT1.GTPE2_LEFT_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT2.GTPE2_LEFT_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT3.GTPE2_LEFT_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT4.GTPE2_LEFT_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT5.GTPE2_LEFT_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT6.GTPE2_LEFT_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT7.GTPE2_LEFT_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT8.GTPE2_LEFT_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT9.GTPE2_LEFT_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT10.GTPE2_LEFT_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT11.GTPE2_LEFT_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT12.GTPE2_LEFT_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT13.GTPE2_LEFT_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT14.GTPE2_LEFT_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT15.GTPE2_LEFT_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT16.GTPE2_LEFT_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT17.GTPE2_LEFT_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT18.GTPE2_LEFT_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT19.GTPE2_LEFT_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT20.GTPE2_LEFT_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT21.GTPE2_LEFT_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT22.GTPE2_LEFT_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT23.GTPE2_LEFT_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT24.GTPE2_LEFT_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT25.GTPE2_LEFT_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT26.GTPE2_LEFT_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT27.GTPE2_LEFT_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT28.GTPE2_LEFT_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT29.GTPE2_LEFT_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT30.GTPE2_LEFT_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT31.GTPE2_LEFT_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT32.GTPE2_LEFT_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT33.GTPE2_LEFT_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT34.GTPE2_LEFT_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT35.GTPE2_LEFT_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT36.GTPE2_LEFT_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT37.GTPE2_LEFT_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT38.GTPE2_LEFT_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT39.GTPE2_LEFT_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT40.GTPE2_LEFT_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT41.GTPE2_LEFT_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT42.GTPE2_LEFT_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT43.GTPE2_LEFT_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT44.GTPE2_LEFT_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT45.GTPE2_LEFT_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT46.GTPE2_LEFT_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT47.GTPE2_LEFT_INT_INTERFACE_IMUX47 always

120
artix7/ppips_gtp_int_interface_r.db Normal file
View File

@ -0,0 +1,120 @@
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS0.GTPE2_INT_INTERFACE_LOGIC_OUTS_B0 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS1.GTPE2_INT_INTERFACE_LOGIC_OUTS_B1 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS2.GTPE2_INT_INTERFACE_LOGIC_OUTS_B2 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS3.GTPE2_INT_INTERFACE_LOGIC_OUTS_B3 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS4.GTPE2_INT_INTERFACE_LOGIC_OUTS_B4 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS5.GTPE2_INT_INTERFACE_LOGIC_OUTS_B5 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS6.GTPE2_INT_INTERFACE_LOGIC_OUTS_B6 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS7.GTPE2_INT_INTERFACE_LOGIC_OUTS_B7 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS8.GTPE2_INT_INTERFACE_LOGIC_OUTS_B8 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS9.GTPE2_INT_INTERFACE_LOGIC_OUTS_B9 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS10.GTPE2_INT_INTERFACE_LOGIC_OUTS_B10 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS11.GTPE2_INT_INTERFACE_LOGIC_OUTS_B11 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS12.GTPE2_INT_INTERFACE_LOGIC_OUTS_B12 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS13.GTPE2_INT_INTERFACE_LOGIC_OUTS_B13 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS14.GTPE2_INT_INTERFACE_LOGIC_OUTS_B14 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS15.GTPE2_INT_INTERFACE_LOGIC_OUTS_B15 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS16.GTPE2_INT_INTERFACE_LOGIC_OUTS_B16 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS17.GTPE2_INT_INTERFACE_LOGIC_OUTS_B17 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS18.GTPE2_INT_INTERFACE_LOGIC_OUTS_B18 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS19.GTPE2_INT_INTERFACE_LOGIC_OUTS_B19 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS20.GTPE2_INT_INTERFACE_LOGIC_OUTS_B20 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS21.GTPE2_INT_INTERFACE_LOGIC_OUTS_B21 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS22.GTPE2_INT_INTERFACE_LOGIC_OUTS_B22 always
GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS23.GTPE2_INT_INTERFACE_LOGIC_OUTS_B23 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY0.GTPE2_R_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY1.GTPE2_R_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY2.GTPE2_R_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY3.GTPE2_R_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY4.GTPE2_R_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY5.GTPE2_R_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY6.GTPE2_R_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY7.GTPE2_R_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY8.GTPE2_R_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY9.GTPE2_R_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY10.GTPE2_R_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY11.GTPE2_R_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY12.GTPE2_R_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY13.GTPE2_R_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY14.GTPE2_R_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY15.GTPE2_R_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY16.GTPE2_R_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY17.GTPE2_R_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY18.GTPE2_R_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY19.GTPE2_R_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY20.GTPE2_R_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY21.GTPE2_R_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY22.GTPE2_R_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY23.GTPE2_R_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY24.GTPE2_R_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY25.GTPE2_R_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY26.GTPE2_R_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY27.GTPE2_R_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY28.GTPE2_R_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY29.GTPE2_R_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY30.GTPE2_R_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY31.GTPE2_R_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY32.GTPE2_R_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY33.GTPE2_R_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY34.GTPE2_R_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY35.GTPE2_R_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY36.GTPE2_R_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY37.GTPE2_R_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY38.GTPE2_R_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY39.GTPE2_R_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY40.GTPE2_R_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY41.GTPE2_R_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY42.GTPE2_R_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY43.GTPE2_R_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY44.GTPE2_R_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY45.GTPE2_R_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY46.GTPE2_R_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY47.GTPE2_R_INT_INTERFACE_IMUX47 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT0.GTPE2_R_INT_INTERFACE_IMUX0 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT1.GTPE2_R_INT_INTERFACE_IMUX1 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT2.GTPE2_R_INT_INTERFACE_IMUX2 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT3.GTPE2_R_INT_INTERFACE_IMUX3 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT4.GTPE2_R_INT_INTERFACE_IMUX4 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT5.GTPE2_R_INT_INTERFACE_IMUX5 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT6.GTPE2_R_INT_INTERFACE_IMUX6 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT7.GTPE2_R_INT_INTERFACE_IMUX7 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT8.GTPE2_R_INT_INTERFACE_IMUX8 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT9.GTPE2_R_INT_INTERFACE_IMUX9 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT10.GTPE2_R_INT_INTERFACE_IMUX10 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT11.GTPE2_R_INT_INTERFACE_IMUX11 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT12.GTPE2_R_INT_INTERFACE_IMUX12 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT13.GTPE2_R_INT_INTERFACE_IMUX13 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT14.GTPE2_R_INT_INTERFACE_IMUX14 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT15.GTPE2_R_INT_INTERFACE_IMUX15 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT16.GTPE2_R_INT_INTERFACE_IMUX16 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT17.GTPE2_R_INT_INTERFACE_IMUX17 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT18.GTPE2_R_INT_INTERFACE_IMUX18 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT19.GTPE2_R_INT_INTERFACE_IMUX19 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT20.GTPE2_R_INT_INTERFACE_IMUX20 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT21.GTPE2_R_INT_INTERFACE_IMUX21 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT22.GTPE2_R_INT_INTERFACE_IMUX22 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT23.GTPE2_R_INT_INTERFACE_IMUX23 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT24.GTPE2_R_INT_INTERFACE_IMUX24 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT25.GTPE2_R_INT_INTERFACE_IMUX25 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT26.GTPE2_R_INT_INTERFACE_IMUX26 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT27.GTPE2_R_INT_INTERFACE_IMUX27 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT28.GTPE2_R_INT_INTERFACE_IMUX28 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT29.GTPE2_R_INT_INTERFACE_IMUX29 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT30.GTPE2_R_INT_INTERFACE_IMUX30 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT31.GTPE2_R_INT_INTERFACE_IMUX31 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT32.GTPE2_R_INT_INTERFACE_IMUX32 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT33.GTPE2_R_INT_INTERFACE_IMUX33 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT34.GTPE2_R_INT_INTERFACE_IMUX34 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT35.GTPE2_R_INT_INTERFACE_IMUX35 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT36.GTPE2_R_INT_INTERFACE_IMUX36 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT37.GTPE2_R_INT_INTERFACE_IMUX37 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT38.GTPE2_R_INT_INTERFACE_IMUX38 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT39.GTPE2_R_INT_INTERFACE_IMUX39 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT40.GTPE2_R_INT_INTERFACE_IMUX40 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT41.GTPE2_R_INT_INTERFACE_IMUX41 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT42.GTPE2_R_INT_INTERFACE_IMUX42 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT43.GTPE2_R_INT_INTERFACE_IMUX43 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT44.GTPE2_R_INT_INTERFACE_IMUX44 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT45.GTPE2_R_INT_INTERFACE_IMUX45 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT46.GTPE2_R_INT_INTERFACE_IMUX46 always
GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT47.GTPE2_R_INT_INTERFACE_IMUX47 always

1736
artix7/ppips_pcie_bot.db Normal file
View File

File diff suppressed because it is too large Load Diff

120
artix7/ppips_pcie_int_interface_l.db Normal file
View File

@ -0,0 +1,120 @@
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L_DELAY0 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L0 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L_DELAY1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L_DELAY2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L_DELAY3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L_DELAY4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L_DELAY5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L_DELAY6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L_DELAY7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L_DELAY8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L_DELAY9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L_DELAY10 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L10 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L_DELAY11 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L11 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L_DELAY12 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L12 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L_DELAY13 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L13 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_DELAY14 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L14 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L15 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L16 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L17 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L18 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L_DELAY19 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L19 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L_DELAY20 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L20 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L_DELAY21 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L21 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L_DELAY22 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L22 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L_DELAY23 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L23 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L_DELAY24 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L24 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L_DELAY25 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L25 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L_DELAY26 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L26 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L_DELAY27 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L27 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L_DELAY28 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L28 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L_DELAY29 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L29 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L_DELAY30 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L30 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L_DELAY31 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L31 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L32 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L33 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L_DELAY34 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L34 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L_DELAY35 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L35 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L_DELAY36 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L36 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L_DELAY37 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L37 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L_DELAY38 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L38 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L_DELAY39 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L39 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L_DELAY40 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L40 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L_DELAY41 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L41 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L_DELAY42 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L42 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L_DELAY43 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L43 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L_DELAY44 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L44 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L_DELAY45 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L45 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L_DELAY46 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L46 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L_DELAY47 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L47 always

120
artix7/ppips_pcie_int_interface_r.db Normal file
View File

@ -0,0 +1,120 @@
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX_DELAY0 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX0 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX_DELAY1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX_DELAY2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX_DELAY3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX_DELAY4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX_DELAY5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX_DELAY6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX_DELAY7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX_DELAY8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX_DELAY9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX_DELAY10 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX10 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX_DELAY11 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX11 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX_DELAY12 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX12 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX_DELAY13 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX13 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX_DELAY14 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX14 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX_DELAY15 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX15 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX_DELAY16 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX16 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX_DELAY17 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX17 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX_DELAY18 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX18 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX19 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX20 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX21 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX22 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX23 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX24 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX25 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX_DELAY26 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX26 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX_DELAY27 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX27 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX_DELAY28 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX28 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX_DELAY29 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX29 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX_DELAY30 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX30 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX_DELAY31 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX31 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX32 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX_DELAY33 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX33 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX_DELAY34 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX34 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX_DELAY35 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX35 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX_DELAY36 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX36 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX_DELAY37 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX37 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX_DELAY38 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX38 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX_DELAY39 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX39 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX_DELAY40 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX40 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX_DELAY41 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX41 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX_DELAY42 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX42 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX_DELAY43 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX43 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX_DELAY44 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX44 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX_DELAY45 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX45 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX_DELAY46 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX46 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX_DELAY47 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX47 always

441
artix7/ppips_pcie_top.db Normal file
View File

@ -0,0 +1,441 @@
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_0.PCIE_TOP_TRNRD59 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_1.PCIE_TOP_TRNRD63 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_2.PCIE_TOP_TRNRD67 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_3.PCIE_TOP_TRNRD71 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_4.PCIE_TOP_TRNRD75 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_0.PCIE_TOP_MIMRXWDATA20 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_1.PCIE_TOP_MIMRXWDATA24 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_2.PCIE_TOP_MIMRXWADDR2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_3.PCIE_TOP_TRNRD83 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_4.PCIE_TOP_TRNRD79 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_0.PCIE_TOP_TRNRD60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_1.PCIE_TOP_TRNRD64 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_2.PCIE_TOP_TRNRD68 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_3.PCIE_TOP_TRNRD72 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TOP_TRNRD76 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_0.PCIE_TOP_MIMRXWADDR12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TOP_TRNRD91 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_2.PCIE_TOP_MIMRXWDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_3.PCIE_TOP_TRNRD84 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_4.PCIE_TOP_TRNTDSTRDY3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_0.PCIE_TOP_TRNRD61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_1.PCIE_TOP_TRNRD65 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_2.PCIE_TOP_TRNRD69 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TOP_TRNRD73 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_4.PCIE_TOP_TRNRD77 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_0.PCIE_TOP_TRNRD95 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TOP_MIMRXWDATA12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_2.PCIE_TOP_TRNRD87 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_3.PCIE_TOP_TRNRD85 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_4.PCIE_TOP_TRNRD80 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_0.PCIE_TOP_TRNRD62 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_1.PCIE_TOP_TRNRD66 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_2.PCIE_TOP_TRNRD70 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_3.PCIE_TOP_TRNRD74 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TOP_TRNRD78 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TOP_MIMRXRADDR10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TOP_TRNRD92 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_2.PCIE_TOP_TRNRD88 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_3.PCIE_TOP_MIMRXWDATA9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_4.PCIE_TOP_TRNRD81 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_0.PCIE_TOP_TRNRDLLPDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TOP_TRNRDLLPDATA36 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_2.PCIE_TOP_TRNRDLLPDATA40 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TOP_TRNRDLLPDATA44 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_4.PCIE_TOP_TRNRDLLPDATA48 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_0.PCIE_TOP_TRNRD96 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TOP_TRNRD93 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_2.PCIE_TOP_TRNRD89 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TOP_TRNRD86 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_4.PCIE_TOP_TRNRD82 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_0.PCIE_TOP_TRNRDLLPDATA33 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TOP_TRNRDLLPDATA37 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_2.PCIE_TOP_TRNRDLLPDATA41 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TOP_TRNRDLLPDATA45 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TOP_TRNRDLLPDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TOP_TRNRD97 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_1.PCIE_TOP_MIMRXWDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_2.PCIE_TOP_MIMRXRADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TOP_TRNRDLLPDATA56 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TOP_TRNRDLLPDATA52 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_0.PCIE_TOP_PIPETXMARGIN2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TOP_TRNRDLLPDATA38 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_2.PCIE_TOP_TRNRDLLPDATA42 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TOP_TRNRDLLPDATA46 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_4.PCIE_TOP_TRNRDLLPDATA50 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_0.PCIE_TOP_TRNRD98 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_1.PCIE_TOP_TRNRD94 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_2.PCIE_TOP_TRNRD90 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_3.PCIE_TOP_TRNRDLLPDATA57 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_4.PCIE_TOP_TRNRDLLPDATA53 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_0.PCIE_TOP_TRNRDLLPDATA34 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TOP_TRNRDLLPDATA39 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_2.PCIE_TOP_TRNRDLLPDATA43 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TOP_TRNRDLLPDATA47 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TOP_TRNRDLLPDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TOP_PL2SUSPENDOK always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_1.PCIE_TOP_MIMRXWDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_2.PCIE_TOP_TRNRDLLPDATA60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_3.PCIE_TOP_TRNRDLLPDATA58 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_4.PCIE_TOP_TRNRDLLPDATA54 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_0.PCIE_TOP_TRNRDLLPDATA35 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TOP_CFGPMRCVENTERL23N always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_2.PCIE_TOP_CFGPMCSRPMEEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TOP_CFGTRANSACTIONADDR0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TOP_CFGTRANSACTIONADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TOP_MIMRXRADDR9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_1.PCIE_TOP_MIMRXWDATA8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TOP_TRNRDLLPDATA61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_3.PCIE_TOP_MIMRXWDATA19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_4.PCIE_TOP_MIMRXWDATA29 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_0.PCIE_TOP_CFGPCIELINKSTATE1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_1.PCIE_TOP_CFGPMRCVREQACKN always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_2.PCIE_TOP_CFGPMCSRPMESTATUS always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_3.PCIE_TOP_CFGTRANSACTIONADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TOP_CFGTRANSACTIONADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_0.PCIE_TOP_MIMRXWDATA4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_1.PCIE_TOP_MIMRXWADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_2.PCIE_TOP_MIMRXWDATA17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_3.PCIE_TOP_TRNRDLLPDATA59 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_4.PCIE_TOP_MIMRXWDATA13 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_0.PCIE_TOP_CFGPCIELINKSTATE2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_2.PCIE_TOP_CFGTRANSACTION always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_3.PCIE_TOP_CFGTRANSACTIONADDR2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_4.PCIE_TOP_CFGTRANSACTIONADDR6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_0.PCIE_TOP_MIMRXRADDR11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_1.PCIE_TOP_TRNRDLLPSRCRDY0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_2.PCIE_TOP_TRNRDLLPDATA62 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_3.PCIE_TOP_MIMRXWDATA25 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_4.PCIE_TOP_MIMRXWDATA15 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_0.PCIE_TOP_CFGPMRCVASREQL1N always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_2.PCIE_TOP_CFGTRANSACTIONTYPE always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_3.PCIE_TOP_CFGTRANSACTIONADDR3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_4.PCIE_TOP_CFGCOMMANDIOENABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_0.PCIE_TOP_MIMRXWDATA0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_1.PCIE_TOP_MIMRXRADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_2.PCIE_TOP_TRNRDLLPDATA63 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_3.PCIE_TOP_CFGMGMTDO20 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_4.PCIE_TOP_MIMRXWDATA35 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_0.PCIE_TOP_CFGPMRCVENTERL1N always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_1.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_2.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_0.PCIE_TOP_PL2RECOVERY always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_1.PCIE_TOP_MIMRXREN always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_2.PCIE_TOP_MIMRXRADDR2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_3.PCIE_TOP_CFGMGMTDO21 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_4.PCIE_TOP_TRNRDLLPDATA55 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_0.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_1.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_2.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_0.PCIE_TOP_MIMRXWDATA1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_1.PCIE_TOP_MIMRXWDATA26 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_2.PCIE_TOP_MIMRXRADDR0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_3.PCIE_TOP_CFGMGMTDO22 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_4.PCIE_TOP_CFGMGMTDO24 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_0.PCIE_TOP_CFGLINKCONTROLRCB always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_1.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_4.PCIE_TOP_CFGDEVCONTROL2IDOREQEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_0.PCIE_TOP_DBGVECA18 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_1.PCIE_TOP_TRNRDLLPSRCRDY1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_2.PCIE_TOP_MIMRXWDATA28 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_3.PCIE_TOP_MIMRXWDATA23 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_4.PCIE_TOP_CFGMGMTDO25 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_0.PCIE_TOP_CFGLINKCONTROLLINKDISABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_1.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_3.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_4.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_0.PCIE_TOP_MIMRXWDATA22 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_1.PCIE_TOP_MIMRXWADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_2.PCIE_TOP_MIMRXWDATA3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_3.PCIE_TOP_CFGMGMTDO23 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_4.PCIE_TOP_CFGMGMTDO26 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_0.PCIE_TOP_PIPETXMARGIN1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_1.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_2.PCIE_TOP_CFGVCTCVCMAP3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_3.PCIE_TOP_DRPRDY always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_4.PCIE_TOP_DRPDO3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_0.PCIE_TOP_MIMRXWDATA6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_1.PCIE_TOP_LL2TFCINIT1SEQ always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_2.PCIE_TOP_CFGMGMTDO17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_3.PCIE_TOP_CFGMGMTDO28 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_4.PCIE_TOP_CFGMGMTDO27 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_0.PCIE_TOP_CFGLINKCONTROLRETRAINLINK always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_1.PCIE_TOP_CFGVCTCVCMAP0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_2.PCIE_TOP_CFGVCTCVCMAP4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_3.PCIE_TOP_DRPDO0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_4.PCIE_TOP_DRPDO4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_0.PCIE_TOP_MIMRXRADDR8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_1.PCIE_TOP_MIMRXWDATA34 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_2.PCIE_TOP_CFGMGMTDO18 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_3.PCIE_TOP_CFGMGMTDO29 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_4.PCIE_TOP_CFGCOMMANDMEMENABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_0.PCIE_TOP_PIPETXMARGIN0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_1.PCIE_TOP_CFGVCTCVCMAP1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_2.PCIE_TOP_CFGVCTCVCMAP5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_3.PCIE_TOP_DRPDO1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_4.PCIE_TOP_DRPDO5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_0.PCIE_TOP_MIMRXWDATA2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_1.PCIE_TOP_MIMRXWEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_2.PCIE_TOP_MIMRXWDATA30 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_3.PCIE_TOP_CFGMGMTDO30 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_4.PCIE_TOP_MIMRXWDATA11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_1.PCIE_TOP_CFGVCTCVCMAP2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_2.PCIE_TOP_CFGVCTCVCMAP6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_3.PCIE_TOP_DRPDO2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_4.PCIE_TOP_DRPDO6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_0.PCIE_TOP_DBGVECA19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_1.PCIE_TOP_MIMRXWDATA10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_2.PCIE_TOP_CFGMGMTDO19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_3.PCIE_TOP_MIMRXWDATA21 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_4.PCIE_TOP_MIMRXWDATA27 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_0.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_1.PCIE_TOP_DRPDO11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_2.PCIE_TOP_DRPDO15 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_3.PCIE_TOP_DBGVECA3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_4.PCIE_TOP_DBGVECA7 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_0.PCIE_TOP_DBGVECA20 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_1.PCIE_TOP_LL2TFCINIT2SEQ always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_2.PCIE_TOP_DBGVECA14 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_3.PCIE_TOP_DBGVECA12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_4.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_0.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_1.PCIE_TOP_DRPDO12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_2.PCIE_TOP_DBGVECA0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_3.PCIE_TOP_DBGVECA4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_4.PCIE_TOP_DBGVECA8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_0.PCIE_TOP_DBGVECA21 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_1.PCIE_TOP_CFGMGMTDO16 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_2.PCIE_TOP_MIMRXWDATA31 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_3.PCIE_TOP_DBGVECA13 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_4.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_1.PCIE_TOP_DRPDO13 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_2.PCIE_TOP_DBGVECA1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_3.PCIE_TOP_DBGVECA5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_4.PCIE_TOP_DBGVECA9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_0.PCIE_TOP_DBGVECB10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_1.PCIE_TOP_DBGVECA16 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_2.PCIE_TOP_MIMRXWDATA33 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_3.PCIE_TOP_MIMRXWDATA5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_4.PCIE_TOP_DBGVECA11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_0.PCIE_TOP_PLDBGVEC8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_1.PCIE_TOP_DRPDO14 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_2.PCIE_TOP_DBGVECA2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_3.PCIE_TOP_DBGVECA6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_4.PCIE_TOP_DBGVECA10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_1.PCIE_TOP_DBGVECA17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_2.PCIE_TOP_DBGVECA15 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_3.PCIE_TOP_MIMRXWDATA7 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_4.PCIE_TOP_CFGDEVCONTROL2LTREN always
PCIE_TOP.PCIE_TOP_CFGERRLOCKEDN.PCIE_IMUX17_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRNORECOVERYN.PCIE_IMUX18_R_2 always
PCIE_TOP.PCIE_TOP_CFGINTERRUPTN.PCIE_IMUX19_R_4 always
PCIE_TOP.PCIE_TOP_LL2SENDPMACK.PCIE_IMUX2_L_4 always
PCIE_TOP.PCIE_TOP_LL2SUSPENDNOW.PCIE_IMUX16_R_3 always
PCIE_TOP.PCIE_TOP_LL2TLPRCV.PCIE_IMUX2_L_3 always
PCIE_TOP.PCIE_TOP_PIPERX0CHANISALIGNED.PCIE_IMUX33_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0PHYSTATUS.PCIE_IMUX37_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0VALID.PCIE_IMUX36_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX4CHANISALIGNED.PCIE_IMUX33_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4PHYSTATUS.PCIE_IMUX37_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4VALID.PCIE_IMUX36_R_0 always
PCIE_TOP.PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK.PCIE_IMUX18_R_3 always
PCIE_TOP.PCIE_TOP_TL2PPMSUSPENDREQ.PCIE_IMUX17_R_3 always
PCIE_TOP.PCIE_TOP_TRNTDLLPSRCRDY.PCIE_IMUX1_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID0.PCIE_IMUX11_L_1 always
PCIE_TOP.PCIE_TOP_CFGDEVID1.PCIE_IMUX8_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID2.PCIE_IMUX9_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID3.PCIE_IMUX10_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID4.PCIE_IMUX11_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID5.PCIE_IMUX8_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID6.PCIE_IMUX9_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID7.PCIE_IMUX10_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID8.PCIE_IMUX11_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID9.PCIE_IMUX8_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID10.PCIE_IMUX9_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID11.PCIE_IMUX10_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID12.PCIE_IMUX11_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID13.PCIE_IMUX21_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID14.PCIE_IMUX22_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID15.PCIE_IMUX23_R_4 always
PCIE_TOP.PCIE_TOP_CFGDSN57.PCIE_IMUX8_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN58.PCIE_IMUX9_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN59.PCIE_IMUX10_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN60.PCIE_IMUX11_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN61.PCIE_IMUX8_L_1 always
PCIE_TOP.PCIE_TOP_CFGDSN62.PCIE_IMUX9_L_1 always
PCIE_TOP.PCIE_TOP_CFGDSN63.PCIE_IMUX10_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG0.PCIE_IMUX19_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG1.PCIE_IMUX20_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG2.PCIE_IMUX20_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG3.PCIE_IMUX21_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG4.PCIE_IMUX22_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG5.PCIE_IMUX23_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG6.PCIE_IMUX13_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG7.PCIE_IMUX14_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG8.PCIE_IMUX15_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG9.PCIE_IMUX16_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG10.PCIE_IMUX24_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG11.PCIE_IMUX21_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER26.PCIE_IMUX4_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER27.PCIE_IMUX5_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER28.PCIE_IMUX6_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER29.PCIE_IMUX7_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER30.PCIE_IMUX4_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER31.PCIE_IMUX5_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER32.PCIE_IMUX6_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER33.PCIE_IMUX7_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER34.PCIE_IMUX4_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER35.PCIE_IMUX5_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER36.PCIE_IMUX6_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER37.PCIE_IMUX7_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER38.PCIE_IMUX4_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER39.PCIE_IMUX5_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER40.PCIE_IMUX6_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER41.PCIE_IMUX7_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER42.PCIE_IMUX4_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER43.PCIE_IMUX5_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER44.PCIE_IMUX6_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER45.PCIE_IMUX7_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER46.PCIE_IMUX17_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER47.PCIE_IMUX18_R_4 always
PCIE_TOP.PCIE_TOP_CFGINTERRUPTDI0.PCIE_IMUX20_R_4 always
PCIE_TOP.PCIE_TOP_CFGVENDID0.PCIE_IMUX24_R_4 always
PCIE_TOP.PCIE_TOP_DBGMODE0.PCIE_IMUX25_R_4 always
PCIE_TOP.PCIE_TOP_DRPADDR7.PCIE_IMUX12_L_0 always
PCIE_TOP.PCIE_TOP_DRPADDR8.PCIE_IMUX13_L_0 always
PCIE_TOP.PCIE_TOP_DRPDI0.PCIE_IMUX12_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI1.PCIE_IMUX13_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI2.PCIE_IMUX14_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI3.PCIE_IMUX15_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI4.PCIE_IMUX12_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI5.PCIE_IMUX13_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI6.PCIE_IMUX14_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI7.PCIE_IMUX15_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI8.PCIE_IMUX12_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI9.PCIE_IMUX13_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI10.PCIE_IMUX14_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI11.PCIE_IMUX15_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI12.PCIE_IMUX12_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI13.PCIE_IMUX13_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI14.PCIE_IMUX14_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI15.PCIE_IMUX15_L_4 always
PCIE_TOP.PCIE_TOP_LL2SENDASREQL1.PCIE_IMUX1_L_4 always
PCIE_TOP.PCIE_TOP_LL2SENDENTERL1.PCIE_IMUX3_L_3 always
PCIE_TOP.PCIE_TOP_LL2SENDENTERL23.PCIE_IMUX0_L_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA20.PCIE_IMUX0_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA21.PCIE_IMUX1_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA22.PCIE_IMUX2_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA23.PCIE_IMUX3_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA24.PCIE_IMUX0_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA25.PCIE_IMUX1_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA26.PCIE_IMUX2_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA27.PCIE_IMUX3_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA28.PCIE_IMUX0_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA29.PCIE_IMUX1_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA30.PCIE_IMUX2_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA31.PCIE_IMUX3_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA32.PCIE_IMUX0_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA33.PCIE_IMUX1_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA34.PCIE_IMUX2_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA35.PCIE_IMUX3_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA36.PCIE_IMUX0_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA37.PCIE_IMUX1_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA38.PCIE_IMUX2_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA39.PCIE_IMUX3_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA40.PCIE_IMUX4_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA41.PCIE_IMUX5_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA42.PCIE_IMUX6_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA43.PCIE_IMUX7_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA44.PCIE_IMUX4_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA45.PCIE_IMUX5_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA46.PCIE_IMUX6_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA47.PCIE_IMUX7_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA48.PCIE_IMUX4_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA49.PCIE_IMUX5_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA50.PCIE_IMUX6_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA51.PCIE_IMUX7_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA52.PCIE_IMUX4_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA53.PCIE_IMUX5_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA54.PCIE_IMUX6_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA55.PCIE_IMUX7_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX0CHARISK0.PCIE_IMUX16_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA0.PCIE_IMUX37_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA1.PCIE_IMUX36_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA2.PCIE_IMUX33_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA3.PCIE_IMUX32_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA4.PCIE_IMUX39_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA5.PCIE_IMUX38_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA6.PCIE_IMUX35_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA7.PCIE_IMUX34_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX4CHARISK0.PCIE_IMUX16_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA0.PCIE_IMUX37_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA1.PCIE_IMUX36_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA2.PCIE_IMUX33_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA3.PCIE_IMUX32_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA4.PCIE_IMUX39_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA5.PCIE_IMUX38_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA6.PCIE_IMUX35_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA7.PCIE_IMUX34_R_0 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE0.PCIE_IMUX3_L_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE1.PCIE_IMUX8_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE2.PCIE_IMUX9_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE3.PCIE_IMUX10_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE4.PCIE_IMUX11_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD8.PCIE_IMUX8_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD9.PCIE_IMUX9_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD10.PCIE_IMUX10_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD11.PCIE_IMUX11_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD12.PCIE_IMUX8_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD13.PCIE_IMUX9_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD14.PCIE_IMUX10_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD15.PCIE_IMUX11_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD16.PCIE_IMUX8_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD17.PCIE_IMUX9_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD18.PCIE_IMUX10_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD19.PCIE_IMUX11_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD20.PCIE_IMUX8_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD21.PCIE_IMUX9_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD22.PCIE_IMUX10_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD23.PCIE_IMUX11_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD24.PCIE_IMUX4_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD25.PCIE_IMUX5_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD26.PCIE_IMUX6_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD27.PCIE_IMUX7_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD28.PCIE_IMUX12_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD29.PCIE_IMUX13_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD30.PCIE_IMUX14_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD31.PCIE_IMUX15_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD32.PCIE_IMUX12_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD33.PCIE_IMUX13_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD34.PCIE_IMUX14_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD35.PCIE_IMUX15_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD36.PCIE_IMUX12_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD37.PCIE_IMUX13_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD38.PCIE_IMUX14_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD39.PCIE_IMUX15_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD40.PCIE_IMUX12_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD41.PCIE_IMUX13_R_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA19.PCIE_IMUX0_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA20.PCIE_IMUX1_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA21.PCIE_IMUX2_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA22.PCIE_IMUX3_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA23.PCIE_IMUX0_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA24.PCIE_IMUX1_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA25.PCIE_IMUX2_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA26.PCIE_IMUX3_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA27.PCIE_IMUX0_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA28.PCIE_IMUX1_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA29.PCIE_IMUX2_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA30.PCIE_IMUX3_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA31.PCIE_IMUX0_L_3 always

756
artix7/segbits_cmt_top_l_lower_b.db
View File

@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_L_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94
CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389
CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388
CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387
CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386
CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385
CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384
CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395
CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394
CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393
CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN 28_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] 29_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] 28_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] 29_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] 28_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] 29_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] 28_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] 29_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] 28_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] 29_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] 28_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST 29_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808

756
artix7/segbits_cmt_top_l_lower_b.origin_info.db
View File

@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_L_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

690
artix7/segbits_cmt_top_l_upper_t.db
View File

@ -21,348 +21,348 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] 28_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] 29_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] 28_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] 29_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] 28_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] 29_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] 28_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] 29_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] 28_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] 29_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST 28_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247

690
artix7/segbits_cmt_top_l_upper_t.origin_info.db
View File

@ -21,348 +21,348 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

756
artix7/segbits_cmt_top_r_lower_b.db
View File

@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_R_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94
CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389
CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388
CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387
CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386
CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385
CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384
CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395
CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394
CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393
CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN 28_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] 29_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] 28_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] 29_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] 28_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] 29_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] 28_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] 29_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] 28_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] 29_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] 28_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST 29_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808

756
artix7/segbits_cmt_top_r_lower_b.origin_info.db
View File

@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_R_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

690
artix7/segbits_cmt_top_r_upper_t.db
View File

@ -21,348 +21,348 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] 28_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] 29_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] 28_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] 29_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] 28_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] 29_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] 28_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] 29_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] 28_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] 29_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST 28_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247

690
artix7/segbits_cmt_top_r_upper_t.origin_info.db
View File

@ -21,348 +21,348 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

3254
artix7/segbits_gtp_channel_0.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_0.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_0_mid_left.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_0_mid_left.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_0_mid_right.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_0_mid_right.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_1.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_1.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_1_mid_left.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_1_mid_left.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_1_mid_right.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_1_mid_right.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_2.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_2.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_2_mid_left.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_2_mid_left.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_2_mid_right.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_2_mid_right.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_3.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_3.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_3_mid_left.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_3_mid_left.origin_info.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_3_mid_right.db
View File

File diff suppressed because it is too large Load Diff

3254
artix7/segbits_gtp_channel_3_mid_right.origin_info.db
View File

File diff suppressed because it is too large Load Diff

556
artix7/segbits_gtp_common.db
View File

@ -1,284 +1,284 @@
GTP_COMMON.ENABLE_DRP 24_1613 25_1613
GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[0] 29_1581
GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[1] 28_1582
GTP_COMMON.IBUFDS_GTE2_Y0.CLKCM_CFG 28_1580
GTP_COMMON.IBUFDS_GTE2_Y0.CLKRCV_TRST 28_1576
GTP_COMMON.IBUFDS_GTE2_Y0.IN_USE 28_1578
GTP_COMMON.IBUFDS_GTE2_Y1.CLKCM_CFG 29_1580
GTP_COMMON.IBUFDS_GTE2_Y1.CLKRCV_TRST 29_1576
GTP_COMMON.IBUFDS_GTE2_Y1.IN_USE 28_1579
GTP_COMMON.GTPE2.BIAS_CFG[0] 28_1640
GTP_COMMON.GTPE2.BIAS_CFG[1] 29_1640
GTP_COMMON.GTPE2.BIAS_CFG[2] 28_1641
GTP_COMMON.GTPE2.BIAS_CFG[3] 29_1641
GTP_COMMON.GTPE2.BIAS_CFG[4] 28_1642
GTP_COMMON.GTPE2.BIAS_CFG[5] 29_1642
GTP_COMMON.GTPE2.BIAS_CFG[6] 28_1643
GTP_COMMON.GTPE2.BIAS_CFG[7] 29_1643
GTP_COMMON.GTPE2.BIAS_CFG[8] 28_1644
GTP_COMMON.GTPE2.BIAS_CFG[9] 29_1644
GTP_COMMON.GTPE2.BIAS_CFG[10] 28_1645
GTP_COMMON.GTPE2.BIAS_CFG[11] 29_1645
GTP_COMMON.GTPE2.BIAS_CFG[12] 28_1646
GTP_COMMON.GTPE2.BIAS_CFG[13] 29_1646
GTP_COMMON.GTPE2.BIAS_CFG[14] 28_1647
GTP_COMMON.GTPE2.BIAS_CFG[15] 29_1647
GTP_COMMON.GTPE2.BIAS_CFG[16] 28_1648
GTP_COMMON.GTPE2.BIAS_CFG[17] 29_1648
GTP_COMMON.GTPE2.BIAS_CFG[18] 28_1649
GTP_COMMON.GTPE2.BIAS_CFG[19] 29_1649
GTP_COMMON.GTPE2.BIAS_CFG[20] 28_1650
GTP_COMMON.GTPE2.BIAS_CFG[21] 29_1650
GTP_COMMON.GTPE2.BIAS_CFG[22] 28_1651
GTP_COMMON.GTPE2.BIAS_CFG[23] 29_1651
GTP_COMMON.GTPE2.BIAS_CFG[24] 28_1652
GTP_COMMON.GTPE2.BIAS_CFG[25] 29_1652
GTP_COMMON.GTPE2.BIAS_CFG[26] 28_1653
GTP_COMMON.GTPE2.BIAS_CFG[27] 29_1653
GTP_COMMON.GTPE2.BIAS_CFG[28] 28_1654
GTP_COMMON.GTPE2.BIAS_CFG[29] 29_1654
GTP_COMMON.GTPE2.BIAS_CFG[30] 28_1655
GTP_COMMON.GTPE2.BIAS_CFG[31] 29_1655
GTP_COMMON.GTPE2.BIAS_CFG[32] 28_1656
GTP_COMMON.GTPE2.BIAS_CFG[33] 29_1656
GTP_COMMON.GTPE2.BIAS_CFG[34] 28_1657
GTP_COMMON.GTPE2.BIAS_CFG[35] 29_1657
GTP_COMMON.GTPE2.BIAS_CFG[36] 28_1658
GTP_COMMON.GTPE2.BIAS_CFG[37] 29_1658
GTP_COMMON.GTPE2.BIAS_CFG[38] 28_1659
GTP_COMMON.GTPE2.BIAS_CFG[39] 29_1659
GTP_COMMON.GTPE2.BIAS_CFG[40] 28_1660
GTP_COMMON.GTPE2.BIAS_CFG[41] 29_1660
GTP_COMMON.GTPE2.BIAS_CFG[42] 28_1661
GTP_COMMON.GTPE2.BIAS_CFG[43] 29_1661
GTP_COMMON.GTPE2.BIAS_CFG[44] 28_1662
GTP_COMMON.GTPE2.BIAS_CFG[45] 29_1662
GTP_COMMON.GTPE2.BIAS_CFG[46] 28_1663
GTP_COMMON.GTPE2.BIAS_CFG[47] 29_1663
GTP_COMMON.GTPE2.BIAS_CFG[48] 28_1664
GTP_COMMON.GTPE2.BIAS_CFG[49] 29_1664
GTP_COMMON.GTPE2.BIAS_CFG[50] 28_1665
GTP_COMMON.GTPE2.BIAS_CFG[51] 29_1665
GTP_COMMON.GTPE2.BIAS_CFG[52] 28_1666
GTP_COMMON.GTPE2.BIAS_CFG[53] 29_1666
GTP_COMMON.GTPE2.BIAS_CFG[54] 28_1667
GTP_COMMON.GTPE2.BIAS_CFG[55] 29_1667
GTP_COMMON.GTPE2.BIAS_CFG[56] 28_1668
GTP_COMMON.GTPE2.BIAS_CFG[57] 29_1668
GTP_COMMON.GTPE2.BIAS_CFG[58] 28_1669
GTP_COMMON.GTPE2.BIAS_CFG[59] 29_1669
GTP_COMMON.GTPE2.BIAS_CFG[60] 28_1670
GTP_COMMON.GTPE2.BIAS_CFG[61] 29_1670
GTP_COMMON.GTPE2.BIAS_CFG[62] 28_1671
GTP_COMMON.GTPE2.BIAS_CFG[63] 29_1671
GTP_COMMON.GTPE2.BOTH_GTREFCLK_USED 29_1439 29_1807
GTP_COMMON.GTPE2.COMMON_CFG[0] 28_1544
GTP_COMMON.GTPE2.COMMON_CFG[1] 29_1544
GTP_COMMON.GTPE2.COMMON_CFG[2] 28_1545
GTP_COMMON.GTPE2.COMMON_CFG[3] 29_1545
GTP_COMMON.GTPE2.COMMON_CFG[4] 28_1546
GTP_COMMON.GTPE2.COMMON_CFG[5] 29_1546
GTP_COMMON.GTPE2.COMMON_CFG[6] 28_1547
GTP_COMMON.GTPE2.COMMON_CFG[7] 29_1547
GTP_COMMON.GTPE2.COMMON_CFG[8] 28_1548
GTP_COMMON.GTPE2.COMMON_CFG[9] 29_1548
GTP_COMMON.GTPE2.COMMON_CFG[10] 28_1549
GTP_COMMON.GTPE2.COMMON_CFG[11] 29_1549
GTP_COMMON.GTPE2.COMMON_CFG[12] 28_1550
GTP_COMMON.GTPE2.COMMON_CFG[13] 29_1550
GTP_COMMON.GTPE2.COMMON_CFG[14] 28_1551
GTP_COMMON.GTPE2.COMMON_CFG[15] 29_1551
GTP_COMMON.GTPE2.COMMON_CFG[16] 28_1552
GTP_COMMON.GTPE2.COMMON_CFG[17] 29_1552
GTP_COMMON.GTPE2.COMMON_CFG[18] 28_1553
GTP_COMMON.GTPE2.COMMON_CFG[19] 29_1553
GTP_COMMON.GTPE2.COMMON_CFG[20] 28_1554
GTP_COMMON.GTPE2.COMMON_CFG[21] 29_1554
GTP_COMMON.GTPE2.COMMON_CFG[22] 28_1555
GTP_COMMON.GTPE2.COMMON_CFG[23] 29_1555
GTP_COMMON.GTPE2.COMMON_CFG[24] 28_1556
GTP_COMMON.GTPE2.COMMON_CFG[25] 29_1556
GTP_COMMON.GTPE2.COMMON_CFG[26] 28_1557
GTP_COMMON.GTPE2.COMMON_CFG[27] 29_1557
GTP_COMMON.GTPE2.COMMON_CFG[28] 28_1558
GTP_COMMON.GTPE2.COMMON_CFG[29] 29_1558
GTP_COMMON.GTPE2.COMMON_CFG[30] 28_1559
GTP_COMMON.GTPE2.COMMON_CFG[31] 29_1559
GTP_COMMON.GTPE2.IN_USE 28_1584
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[0] 28_1560
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[1] 29_1560
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[2] 28_1561
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[3] 29_1561
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[4] 28_1562
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[5] 29_1562
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[6] 28_1563
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[7] 29_1563
GTP_COMMON.GTPE2.RSVD_ATTR0[0] 28_1488
GTP_COMMON.GTPE2.RSVD_ATTR0[1] 29_1488
GTP_COMMON.GTPE2.RSVD_ATTR0[2] 28_1489
GTP_COMMON.GTPE2.RSVD_ATTR0[3] 29_1489
GTP_COMMON.GTPE2.RSVD_ATTR0[4] 28_1490
GTP_COMMON.GTPE2.RSVD_ATTR0[5] 29_1490
GTP_COMMON.GTPE2.RSVD_ATTR0[6] 28_1491
GTP_COMMON.GTPE2.RSVD_ATTR0[7] 29_1491
GTP_COMMON.GTPE2.RSVD_ATTR0[8] 28_1492
GTP_COMMON.GTPE2.RSVD_ATTR0[9] 29_1492
GTP_COMMON.GTPE2.RSVD_ATTR0[10] 28_1493
GTP_COMMON.GTPE2.RSVD_ATTR0[11] 29_1493
GTP_COMMON.GTPE2.RSVD_ATTR0[12] 28_1494
GTP_COMMON.GTPE2.RSVD_ATTR0[13] 29_1494
GTP_COMMON.GTPE2.RSVD_ATTR0[14] 28_1495
GTP_COMMON.GTPE2.RSVD_ATTR0[15] 29_1495
GTP_COMMON.GTPE2.RSVD_ATTR1[0] 28_1728
GTP_COMMON.GTPE2.RSVD_ATTR1[1] 29_1728
GTP_COMMON.GTPE2.RSVD_ATTR1[2] 28_1729
GTP_COMMON.GTPE2.RSVD_ATTR1[3] 29_1729
GTP_COMMON.GTPE2.RSVD_ATTR1[4] 28_1730
GTP_COMMON.GTPE2.RSVD_ATTR1[5] 29_1730
GTP_COMMON.GTPE2.RSVD_ATTR1[6] 28_1731
GTP_COMMON.GTPE2.RSVD_ATTR1[7] 29_1731
GTP_COMMON.GTPE2.RSVD_ATTR1[8] 28_1732
GTP_COMMON.GTPE2.RSVD_ATTR1[9] 29_1732
GTP_COMMON.GTPE2.RSVD_ATTR1[10] 28_1733
GTP_COMMON.GTPE2.RSVD_ATTR1[11] 29_1733
GTP_COMMON.GTPE2.RSVD_ATTR1[12] 28_1734
GTP_COMMON.GTPE2.RSVD_ATTR1[13] 29_1734
GTP_COMMON.GTPE2.RSVD_ATTR1[14] 28_1735
GTP_COMMON.GTPE2.RSVD_ATTR1[15] 29_1735
GTP_COMMON.GTPE2.ZINV_DRPCLK 28_1516
GTP_COMMON.GTPE2.ZINV_PLL0LOCKDETCLK 29_1512
GTP_COMMON.GTPE2.ZINV_PLL1LOCKDETCLK 28_1512
GTP_COMMON.GTPE2.GTREFCLK0_USED 28_1438 28_1806
GTP_COMMON.GTPE2.GTREFCLK1_USED 29_1438 29_1806
GTP_COMMON.GTPE2.PLL0_CFG[0] 28_1424
GTP_COMMON.GTPE2.PLL0_CFG[1] 29_1424
GTP_COMMON.GTPE2.PLL0_CFG[2] 28_1425
GTP_COMMON.GTPE2.PLL0_CFG[3] 29_1425
GTP_COMMON.GTPE2.PLL0_CFG[4] 28_1426
GTP_COMMON.GTPE2.PLL0_CFG[5] 29_1426
GTP_COMMON.GTPE2.PLL0_CFG[6] 28_1427
GTP_COMMON.GTPE2.PLL0_CFG[7] 29_1427
GTP_COMMON.GTPE2.PLL0_CFG[8] 28_1428
GTP_COMMON.GTPE2.PLL0_CFG[9] 29_1428
GTP_COMMON.GTPE2.PLL0_CFG[10] 28_1429
GTP_COMMON.GTPE2.PLL0_CFG[11] 29_1429
GTP_COMMON.GTPE2.PLL0_CFG[12] 28_1430
GTP_COMMON.GTPE2.PLL0_CFG[13] 29_1430
GTP_COMMON.GTPE2.PLL0_CFG[14] 28_1431
GTP_COMMON.GTPE2.PLL0_CFG[15] 29_1431
GTP_COMMON.GTPE2.PLL0_CFG[16] 28_1432
GTP_COMMON.GTPE2.PLL0_CFG[17] 29_1432
GTP_COMMON.GTPE2.PLL0_CFG[18] 28_1433
GTP_COMMON.GTPE2.PLL0_CFG[19] 29_1433
GTP_COMMON.GTPE2.PLL0_CFG[20] 28_1434
GTP_COMMON.GTPE2.PLL0_CFG[21] 29_1434
GTP_COMMON.GTPE2.PLL0_CFG[22] 28_1435
GTP_COMMON.GTPE2.PLL0_CFG[23] 29_1435
GTP_COMMON.GTPE2.PLL0_CFG[24] 28_1436
GTP_COMMON.GTPE2.PLL0_CFG[25] 29_1436
GTP_COMMON.GTPE2.PLL0_CFG[26] 28_1437
GTP_COMMON.GTPE2.PLL0_DMON_CFG[0] 28_1528
GTP_COMMON.GTPE2.PLL0_FBDIV[0] 28_1440
GTP_COMMON.GTPE2.PLL0_FBDIV[1] 29_1440
GTP_COMMON.GTPE2.PLL0_FBDIV[4] 28_1442
GTP_COMMON.GTPE2.PLL0_FBDIV_45[0] 29_1443
GTP_COMMON.GTPE2.PLL0_INIT_CFG[0] 28_1456
GTP_COMMON.GTPE2.PLL0_INIT_CFG[1] 29_1456
GTP_COMMON.GTPE2.PLL0_INIT_CFG[2] 28_1457
GTP_COMMON.GTPE2.PLL0_INIT_CFG[3] 29_1457
GTP_COMMON.GTPE2.PLL0_INIT_CFG[4] 28_1458
GTP_COMMON.GTPE2.PLL0_INIT_CFG[5] 29_1458
GTP_COMMON.GTPE2.PLL0_INIT_CFG[6] 28_1459
GTP_COMMON.GTPE2.PLL0_INIT_CFG[7] 29_1459
GTP_COMMON.GTPE2.PLL0_INIT_CFG[8] 28_1460
GTP_COMMON.GTPE2.PLL0_INIT_CFG[9] 29_1460
GTP_COMMON.GTPE2.PLL0_INIT_CFG[10] 28_1461
GTP_COMMON.GTPE2.PLL0_INIT_CFG[11] 29_1461
GTP_COMMON.GTPE2.PLL0_INIT_CFG[12] 28_1462
GTP_COMMON.GTPE2.PLL0_INIT_CFG[13] 29_1462
GTP_COMMON.GTPE2.PLL0_INIT_CFG[14] 28_1463
GTP_COMMON.GTPE2.PLL0_INIT_CFG[15] 29_1463
GTP_COMMON.GTPE2.PLL0_INIT_CFG[16] 28_1464
GTP_COMMON.GTPE2.PLL0_INIT_CFG[17] 29_1464
GTP_COMMON.GTPE2.PLL0_INIT_CFG[18] 28_1465
GTP_COMMON.GTPE2.PLL0_INIT_CFG[19] 29_1465
GTP_COMMON.GTPE2.PLL0_INIT_CFG[20] 28_1466
GTP_COMMON.GTPE2.PLL0_INIT_CFG[21] 29_1466
GTP_COMMON.GTPE2.PLL0_INIT_CFG[22] 28_1467
GTP_COMMON.GTPE2.PLL0_INIT_CFG[23] 29_1467
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[0] 28_1448
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[1] 29_1448
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[2] 28_1449
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[3] 29_1449
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[4] 28_1450
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[5] 29_1450
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[6] 28_1451
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[7] 29_1451
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[8] 28_1452
GTP_COMMON.GTPE2.PLL0_REFCLK_DIV[4] 29_1446
GTP_COMMON.GTPE2.PLL1_CFG[0] 28_1792
GTP_COMMON.GTPE2.PLL1_CFG[1] 29_1792
GTP_COMMON.GTPE2.PLL1_CFG[2] 28_1793
GTP_COMMON.GTPE2.PLL1_CFG[3] 29_1793
GTP_COMMON.GTPE2.PLL1_CFG[4] 28_1794
GTP_COMMON.GTPE2.PLL1_CFG[5] 29_1794
GTP_COMMON.GTPE2.PLL1_CFG[6] 28_1795
GTP_COMMON.GTPE2.PLL1_CFG[7] 29_1795
GTP_COMMON.GTPE2.PLL1_CFG[8] 28_1796
GTP_COMMON.GTPE2.PLL1_CFG[9] 29_1796
GTP_COMMON.GTPE2.PLL1_CFG[10] 28_1797
GTP_COMMON.GTPE2.PLL1_CFG[11] 29_1797
GTP_COMMON.GTPE2.PLL1_CFG[12] 28_1798
GTP_COMMON.GTPE2.PLL1_CFG[13] 29_1798
GTP_COMMON.GTPE2.PLL1_CFG[14] 28_1799
GTP_COMMON.GTPE2.PLL1_CFG[15] 29_1799
GTP_COMMON.GTPE2.PLL1_CFG[16] 28_1800
GTP_COMMON.GTPE2.PLL1_CFG[17] 29_1800
GTP_COMMON.GTPE2.PLL1_CFG[18] 28_1801
GTP_COMMON.GTPE2.PLL1_CFG[19] 29_1801
GTP_COMMON.GTPE2.PLL1_CFG[20] 28_1802
GTP_COMMON.GTPE2.PLL1_CFG[21] 29_1802
GTP_COMMON.GTPE2.PLL1_CFG[22] 28_1803
GTP_COMMON.GTPE2.PLL1_CFG[23] 29_1803
GTP_COMMON.GTPE2.PLL1_CFG[24] 28_1804
GTP_COMMON.GTPE2.PLL1_CFG[25] 29_1804
GTP_COMMON.GTPE2.PLL1_CFG[26] 28_1805
GTP_COMMON.GTPE2.PLL1_DMON_CFG[0] 29_1528
GTP_COMMON.GTPE2.PLL1_FBDIV[0] 28_1784
GTP_COMMON.GTPE2.PLL1_FBDIV[1] 29_1784
GTP_COMMON.GTPE2.PLL1_FBDIV[4] 28_1786
GTP_COMMON.GTPE2.PLL1_FBDIV_45[0] 29_1787
GTP_COMMON.GTPE2.PLL1_INIT_CFG[0] 28_1760
GTP_COMMON.GTPE2.PLL1_INIT_CFG[1] 29_1760
GTP_COMMON.GTPE2.PLL1_INIT_CFG[2] 28_1761
GTP_COMMON.GTPE2.PLL1_INIT_CFG[3] 29_1761
GTP_COMMON.GTPE2.PLL1_INIT_CFG[4] 28_1762
GTP_COMMON.GTPE2.PLL1_INIT_CFG[5] 29_1762
GTP_COMMON.GTPE2.PLL1_INIT_CFG[6] 28_1763
GTP_COMMON.GTPE2.PLL1_INIT_CFG[7] 29_1763
GTP_COMMON.GTPE2.PLL1_INIT_CFG[8] 28_1764
GTP_COMMON.GTPE2.PLL1_INIT_CFG[9] 29_1764
GTP_COMMON.GTPE2.PLL1_INIT_CFG[10] 28_1765
GTP_COMMON.GTPE2.PLL1_INIT_CFG[11] 29_1765
GTP_COMMON.GTPE2.PLL1_INIT_CFG[12] 28_1766
GTP_COMMON.GTPE2.PLL1_INIT_CFG[13] 29_1766
GTP_COMMON.GTPE2.PLL1_INIT_CFG[14] 28_1767
GTP_COMMON.GTPE2.PLL1_INIT_CFG[15] 29_1767
GTP_COMMON.GTPE2.PLL1_INIT_CFG[16] 28_1768
GTP_COMMON.GTPE2.PLL1_INIT_CFG[17] 29_1768
GTP_COMMON.GTPE2.PLL1_INIT_CFG[18] 28_1769
GTP_COMMON.GTPE2.PLL1_INIT_CFG[19] 29_1769
GTP_COMMON.GTPE2.PLL1_INIT_CFG[20] 28_1770
GTP_COMMON.GTPE2.PLL1_INIT_CFG[21] 29_1770
GTP_COMMON.GTPE2.PLL1_INIT_CFG[22] 28_1771
GTP_COMMON.GTPE2.PLL1_INIT_CFG[23] 29_1771
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[0] 28_1776
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[1] 29_1776
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[2] 28_1777
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[3] 29_1777
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[4] 28_1778
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[5] 29_1778
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[6] 28_1779
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[7] 29_1779
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[8] 28_1780
GTP_COMMON.GTPE2.PLL1_REFCLK_DIV[4] 29_1790
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[0] 28_1640
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[1] 29_1640
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[2] 28_1641
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[3] 29_1641
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[4] 28_1642
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[5] 29_1642
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[6] 28_1643
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[7] 29_1643
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[8] 28_1644
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[9] 29_1644
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[10] 28_1645
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[11] 29_1645
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[12] 28_1646
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[13] 29_1646
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[14] 28_1647
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[15] 29_1647
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[16] 28_1648
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[17] 29_1648
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[18] 28_1649
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[19] 29_1649
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[20] 28_1650
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[21] 29_1650
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[22] 28_1651
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[23] 29_1651
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[24] 28_1652
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[25] 29_1652
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[26] 28_1653
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[27] 29_1653
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[28] 28_1654
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[29] 29_1654
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[30] 28_1655
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[31] 29_1655
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[32] 28_1656
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[33] 29_1656
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[34] 28_1657
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[35] 29_1657
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[36] 28_1658
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[37] 29_1658
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[38] 28_1659
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[39] 29_1659
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[40] 28_1660
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[41] 29_1660
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[42] 28_1661
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[43] 29_1661
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[44] 28_1662
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[45] 29_1662
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[46] 28_1663
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[47] 29_1663
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[48] 28_1664
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[49] 29_1664
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[50] 28_1665
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[51] 29_1665
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[52] 28_1666
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[53] 29_1666
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[54] 28_1667
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[55] 29_1667
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[56] 28_1668
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[57] 29_1668
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[58] 28_1669
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[59] 29_1669
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[60] 28_1670
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[61] 29_1670
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[62] 28_1671
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[63] 29_1671
GTP_COMMON.GTPE2_COMMON.BOTH_GTREFCLK_USED 29_1439 29_1807
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[0] 28_1544
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[1] 29_1544
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[2] 28_1545
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[3] 29_1545
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[4] 28_1546
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[5] 29_1546
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[6] 28_1547
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[7] 29_1547
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[8] 28_1548
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[9] 29_1548
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[10] 28_1549
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[11] 29_1549
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[12] 28_1550
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[13] 29_1550
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[14] 28_1551
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[15] 29_1551
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[16] 28_1552
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[17] 29_1552
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[18] 28_1553
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[19] 29_1553
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[20] 28_1554
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[21] 29_1554
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[22] 28_1555
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[23] 29_1555
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[24] 28_1556
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[25] 29_1556
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[26] 28_1557
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[27] 29_1557
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[28] 28_1558
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[29] 29_1558
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[30] 28_1559
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[31] 29_1559
GTP_COMMON.GTPE2_COMMON.ENABLE_DRP 24_1613 25_1613
GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] 29_1581
GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] 28_1582
GTP_COMMON.GTPE2_COMMON.IN_USE 28_1584
GTP_COMMON.GTPE2_COMMON.INV_DRPCLK 28_1516
GTP_COMMON.GTPE2_COMMON.INV_PLL0LOCKDETCLK 29_1512
GTP_COMMON.GTPE2_COMMON.INV_PLL1LOCKDETCLK 28_1512
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[0] 28_1560
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[1] 29_1560
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[2] 28_1561
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[3] 29_1561
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[4] 28_1562
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[5] 29_1562
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[6] 28_1563
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[7] 29_1563
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[0] 28_1488
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[1] 29_1488
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[2] 28_1489
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[3] 29_1489
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[4] 28_1490
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[5] 29_1490
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[6] 28_1491
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[7] 29_1491
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[8] 28_1492
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[9] 29_1492
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[10] 28_1493
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[11] 29_1493
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[12] 28_1494
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[13] 29_1494
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[14] 28_1495
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[15] 29_1495
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[0] 28_1728
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[1] 29_1728
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[2] 28_1729
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[3] 29_1729
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[4] 28_1730
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[5] 29_1730
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[6] 28_1731
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[7] 29_1731
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[8] 28_1732
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[9] 29_1732
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[10] 28_1733
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[11] 29_1733
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[12] 28_1734
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[13] 29_1734
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[14] 28_1735
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[15] 29_1735
GTP_COMMON.GTPE2_COMMON.GTREFCLK0_USED 28_1438 28_1806
GTP_COMMON.GTPE2_COMMON.GTREFCLK1_USED 29_1438 29_1806
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[0] 28_1424
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[1] 29_1424
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[2] 28_1425
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[3] 29_1425
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[4] 28_1426
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[5] 29_1426
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[6] 28_1427
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[7] 29_1427
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[8] 28_1428
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[9] 29_1428
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[10] 28_1429
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[11] 29_1429
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[12] 28_1430
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[13] 29_1430
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[14] 28_1431
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[15] 29_1431
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[16] 28_1432
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[17] 29_1432
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[18] 28_1433
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[19] 29_1433
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[20] 28_1434
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[21] 29_1434
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[22] 28_1435
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[23] 29_1435
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[24] 28_1436
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[25] 29_1436
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[26] 28_1437
GTP_COMMON.GTPE2_COMMON.PLL0_DMON_CFG[0] 28_1528
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[0] 28_1440
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[1] 29_1440
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[4] 28_1442
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV_45[0] 29_1443
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[0] 28_1456
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[1] 29_1456
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[2] 28_1457
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[3] 29_1457
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[4] 28_1458
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[5] 29_1458
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[6] 28_1459
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[7] 29_1459
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[8] 28_1460
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[9] 29_1460
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[10] 28_1461
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[11] 29_1461
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[12] 28_1462
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[13] 29_1462
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[14] 28_1463
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[15] 29_1463
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[16] 28_1464
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[17] 29_1464
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[18] 28_1465
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[19] 29_1465
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[20] 28_1466
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[21] 29_1466
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[22] 28_1467
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[23] 29_1467
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[0] 28_1448
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[1] 29_1448
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[2] 28_1449
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[3] 29_1449
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[4] 28_1450
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[5] 29_1450
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[6] 28_1451
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[7] 29_1451
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[8] 28_1452
GTP_COMMON.GTPE2_COMMON.PLL0_REFCLK_DIV[4] 29_1446
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[0] 28_1792
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[1] 29_1792
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[2] 28_1793
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[3] 29_1793
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[4] 28_1794
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[5] 29_1794
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[6] 28_1795
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[7] 29_1795
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[8] 28_1796
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[9] 29_1796
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[10] 28_1797
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[11] 29_1797
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[12] 28_1798
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[13] 29_1798
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[14] 28_1799
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[15] 29_1799
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[16] 28_1800
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[17] 29_1800
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[18] 28_1801
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[19] 29_1801
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[20] 28_1802
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[21] 29_1802
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[22] 28_1803
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[23] 29_1803
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[24] 28_1804
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[25] 29_1804
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[26] 28_1805
GTP_COMMON.GTPE2_COMMON.PLL1_DMON_CFG[0] 29_1528
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[0] 28_1784
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[1] 29_1784
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[4] 28_1786
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV_45[0] 29_1787
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[0] 28_1760
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[1] 29_1760
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[2] 28_1761
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[3] 29_1761
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[4] 28_1762
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[5] 29_1762
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[6] 28_1763
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[7] 29_1763
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[8] 28_1764
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[9] 29_1764
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[10] 28_1765
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[11] 29_1765
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[12] 28_1766
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[13] 29_1766
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[14] 28_1767
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[15] 29_1767
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[16] 28_1768
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[17] 29_1768
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[18] 28_1769
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[19] 29_1769
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[20] 28_1770
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[21] 29_1770
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[22] 28_1771
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[23] 29_1771
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[0] 28_1776
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[1] 29_1776
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[2] 28_1777
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[3] 29_1777
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[4] 28_1778
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[5] 29_1778
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[6] 28_1779
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[7] 29_1779
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[8] 28_1780
GTP_COMMON.GTPE2_COMMON.PLL1_REFCLK_DIV[4] 29_1790

556
artix7/segbits_gtp_common.origin_info.db
View File

@ -1,284 +1,284 @@
GTP_COMMON.ENABLE_DRP origin:063-gtp-common-conf 24_1613 25_1613
GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 29_1581
GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 28_1582
GTP_COMMON.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 28_1580
GTP_COMMON.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 28_1576
GTP_COMMON.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 28_1578
GTP_COMMON.IBUFDS_GTE2_Y1.CLKCM_CFG origin:063-gtp-common-conf 29_1580
GTP_COMMON.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 29_1576
GTP_COMMON.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 28_1579
GTP_COMMON.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 28_1640
GTP_COMMON.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 29_1640
GTP_COMMON.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 28_1641
GTP_COMMON.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 29_1641
GTP_COMMON.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 28_1642
GTP_COMMON.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 29_1642
GTP_COMMON.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 28_1643
GTP_COMMON.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 29_1643
GTP_COMMON.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 28_1644
GTP_COMMON.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 29_1644
GTP_COMMON.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 28_1645
GTP_COMMON.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 29_1645
GTP_COMMON.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 28_1646
GTP_COMMON.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 29_1646
GTP_COMMON.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 28_1647
GTP_COMMON.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 29_1647
GTP_COMMON.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 28_1648
GTP_COMMON.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 29_1648
GTP_COMMON.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 28_1649
GTP_COMMON.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 29_1649
GTP_COMMON.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 28_1650
GTP_COMMON.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 29_1650
GTP_COMMON.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 28_1651
GTP_COMMON.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 29_1651
GTP_COMMON.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 28_1652
GTP_COMMON.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 29_1652
GTP_COMMON.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 28_1653
GTP_COMMON.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 29_1653
GTP_COMMON.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 28_1654
GTP_COMMON.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 29_1654
GTP_COMMON.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 28_1655
GTP_COMMON.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 29_1655
GTP_COMMON.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 28_1656
GTP_COMMON.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 29_1656
GTP_COMMON.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 28_1657
GTP_COMMON.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 29_1657
GTP_COMMON.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 28_1658
GTP_COMMON.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 29_1658
GTP_COMMON.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 28_1659
GTP_COMMON.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 29_1659
GTP_COMMON.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 28_1660
GTP_COMMON.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 29_1660
GTP_COMMON.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 28_1661
GTP_COMMON.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 29_1661
GTP_COMMON.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 28_1662
GTP_COMMON.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 29_1662
GTP_COMMON.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 28_1663
GTP_COMMON.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 29_1663
GTP_COMMON.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 28_1664
GTP_COMMON.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 29_1664
GTP_COMMON.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 28_1665
GTP_COMMON.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 29_1665
GTP_COMMON.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 28_1666
GTP_COMMON.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 29_1666
GTP_COMMON.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 28_1667
GTP_COMMON.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 29_1667
GTP_COMMON.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 28_1668
GTP_COMMON.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 29_1668
GTP_COMMON.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 28_1669
GTP_COMMON.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 29_1669
GTP_COMMON.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 28_1670
GTP_COMMON.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 29_1670
GTP_COMMON.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 28_1671
GTP_COMMON.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 29_1671
GTP_COMMON.GTPE2.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 29_1439 29_1807
GTP_COMMON.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 28_1544
GTP_COMMON.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 29_1544
GTP_COMMON.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 28_1545
GTP_COMMON.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 29_1545
GTP_COMMON.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 28_1546
GTP_COMMON.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 29_1546
GTP_COMMON.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 28_1547
GTP_COMMON.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 29_1547
GTP_COMMON.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 28_1548
GTP_COMMON.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 29_1548
GTP_COMMON.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 28_1549
GTP_COMMON.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 29_1549
GTP_COMMON.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 28_1550
GTP_COMMON.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 29_1550
GTP_COMMON.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 28_1551
GTP_COMMON.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 29_1551
GTP_COMMON.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 28_1552
GTP_COMMON.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 29_1552
GTP_COMMON.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 28_1553
GTP_COMMON.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 29_1553
GTP_COMMON.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 28_1554
GTP_COMMON.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 29_1554
GTP_COMMON.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 28_1555
GTP_COMMON.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 29_1555
GTP_COMMON.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 28_1556
GTP_COMMON.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 29_1556
GTP_COMMON.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 28_1557
GTP_COMMON.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 29_1557
GTP_COMMON.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 28_1558
GTP_COMMON.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 29_1558
GTP_COMMON.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 28_1559
GTP_COMMON.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 29_1559
GTP_COMMON.GTPE2.IN_USE origin:063-gtp-common-conf 28_1584
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 28_1560
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 29_1560
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 28_1561
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 29_1561
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 28_1562
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 29_1562
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 28_1563
GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 29_1563
GTP_COMMON.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 28_1488
GTP_COMMON.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 29_1488
GTP_COMMON.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 28_1489
GTP_COMMON.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 29_1489
GTP_COMMON.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 28_1490
GTP_COMMON.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 29_1490
GTP_COMMON.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 28_1491
GTP_COMMON.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 29_1491
GTP_COMMON.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 28_1492
GTP_COMMON.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 29_1492
GTP_COMMON.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 28_1493
GTP_COMMON.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 29_1493
GTP_COMMON.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 28_1494
GTP_COMMON.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 29_1494
GTP_COMMON.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 28_1495
GTP_COMMON.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 29_1495
GTP_COMMON.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 28_1728
GTP_COMMON.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 29_1728
GTP_COMMON.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 28_1729
GTP_COMMON.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 29_1729
GTP_COMMON.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 28_1730
GTP_COMMON.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 29_1730
GTP_COMMON.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 28_1731
GTP_COMMON.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 29_1731
GTP_COMMON.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 28_1732
GTP_COMMON.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 29_1732
GTP_COMMON.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 28_1733
GTP_COMMON.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 29_1733
GTP_COMMON.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 28_1734
GTP_COMMON.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 29_1734
GTP_COMMON.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 28_1735
GTP_COMMON.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 29_1735
GTP_COMMON.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 28_1516
GTP_COMMON.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 29_1512
GTP_COMMON.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 28_1512
GTP_COMMON.GTPE2.GTREFCLK0_USED origin:063-gtp-common-conf 28_1438 28_1806
GTP_COMMON.GTPE2.GTREFCLK1_USED origin:063-gtp-common-conf 29_1438 29_1806
GTP_COMMON.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 28_1424
GTP_COMMON.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 29_1424
GTP_COMMON.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 28_1425
GTP_COMMON.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 29_1425
GTP_COMMON.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 28_1426
GTP_COMMON.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 29_1426
GTP_COMMON.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 28_1427
GTP_COMMON.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 29_1427
GTP_COMMON.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 28_1428
GTP_COMMON.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 29_1428
GTP_COMMON.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 28_1429
GTP_COMMON.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 29_1429
GTP_COMMON.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 28_1430
GTP_COMMON.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 29_1430
GTP_COMMON.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 28_1431
GTP_COMMON.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 29_1431
GTP_COMMON.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 28_1432
GTP_COMMON.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 29_1432
GTP_COMMON.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 28_1433
GTP_COMMON.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 29_1433
GTP_COMMON.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 28_1434
GTP_COMMON.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 29_1434
GTP_COMMON.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 28_1435
GTP_COMMON.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 29_1435
GTP_COMMON.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 28_1436
GTP_COMMON.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 29_1436
GTP_COMMON.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 28_1437
GTP_COMMON.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 28_1528
GTP_COMMON.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 28_1440
GTP_COMMON.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 29_1440
GTP_COMMON.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 28_1442
GTP_COMMON.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 29_1443
GTP_COMMON.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 28_1456
GTP_COMMON.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 29_1456
GTP_COMMON.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 28_1457
GTP_COMMON.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 29_1457
GTP_COMMON.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 28_1458
GTP_COMMON.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 29_1458
GTP_COMMON.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 28_1459
GTP_COMMON.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 29_1459
GTP_COMMON.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 28_1460
GTP_COMMON.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 29_1460
GTP_COMMON.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 28_1461
GTP_COMMON.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 29_1461
GTP_COMMON.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 28_1462
GTP_COMMON.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 29_1462
GTP_COMMON.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 28_1463
GTP_COMMON.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 29_1463
GTP_COMMON.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 28_1464
GTP_COMMON.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 29_1464
GTP_COMMON.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 28_1465
GTP_COMMON.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 29_1465
GTP_COMMON.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 28_1466
GTP_COMMON.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 29_1466
GTP_COMMON.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 28_1467
GTP_COMMON.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 29_1467
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 28_1448
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 29_1448
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 28_1449
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 29_1449
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 28_1450
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 29_1450
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 28_1451
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 29_1451
GTP_COMMON.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 28_1452
GTP_COMMON.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1446
GTP_COMMON.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 28_1792
GTP_COMMON.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 29_1792
GTP_COMMON.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 28_1793
GTP_COMMON.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 29_1793
GTP_COMMON.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 28_1794
GTP_COMMON.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 29_1794
GTP_COMMON.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 28_1795
GTP_COMMON.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 29_1795
GTP_COMMON.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 28_1796
GTP_COMMON.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 29_1796
GTP_COMMON.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 28_1797
GTP_COMMON.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 29_1797
GTP_COMMON.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 28_1798
GTP_COMMON.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 29_1798
GTP_COMMON.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 28_1799
GTP_COMMON.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 29_1799
GTP_COMMON.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 28_1800
GTP_COMMON.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 29_1800
GTP_COMMON.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 28_1801
GTP_COMMON.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 29_1801
GTP_COMMON.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 28_1802
GTP_COMMON.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 29_1802
GTP_COMMON.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 28_1803
GTP_COMMON.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 29_1803
GTP_COMMON.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 28_1804
GTP_COMMON.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 29_1804
GTP_COMMON.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 28_1805
GTP_COMMON.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 29_1528
GTP_COMMON.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 28_1784
GTP_COMMON.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 29_1784
GTP_COMMON.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 28_1786
GTP_COMMON.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 29_1787
GTP_COMMON.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 28_1760
GTP_COMMON.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 29_1760
GTP_COMMON.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 28_1761
GTP_COMMON.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 29_1761
GTP_COMMON.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 28_1762
GTP_COMMON.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 29_1762
GTP_COMMON.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 28_1763
GTP_COMMON.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 29_1763
GTP_COMMON.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 28_1764
GTP_COMMON.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 29_1764
GTP_COMMON.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 28_1765
GTP_COMMON.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 29_1765
GTP_COMMON.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 28_1766
GTP_COMMON.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 29_1766
GTP_COMMON.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 28_1767
GTP_COMMON.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 29_1767
GTP_COMMON.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 28_1768
GTP_COMMON.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 29_1768
GTP_COMMON.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 28_1769
GTP_COMMON.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 29_1769
GTP_COMMON.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 28_1770
GTP_COMMON.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 29_1770
GTP_COMMON.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 28_1771
GTP_COMMON.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 29_1771
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 28_1776
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 29_1776
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 28_1777
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 29_1777
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 28_1778
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 29_1778
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 28_1779
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 29_1779
GTP_COMMON.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 28_1780
GTP_COMMON.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1790
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[0] origin:063-gtp-common-conf 28_1640
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[1] origin:063-gtp-common-conf 29_1640
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[2] origin:063-gtp-common-conf 28_1641
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[3] origin:063-gtp-common-conf 29_1641
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[4] origin:063-gtp-common-conf 28_1642
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[5] origin:063-gtp-common-conf 29_1642
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[6] origin:063-gtp-common-conf 28_1643
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[7] origin:063-gtp-common-conf 29_1643
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[8] origin:063-gtp-common-conf 28_1644
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[9] origin:063-gtp-common-conf 29_1644
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[10] origin:063-gtp-common-conf 28_1645
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[11] origin:063-gtp-common-conf 29_1645
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[12] origin:063-gtp-common-conf 28_1646
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[13] origin:063-gtp-common-conf 29_1646
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[14] origin:063-gtp-common-conf 28_1647
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[15] origin:063-gtp-common-conf 29_1647
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[16] origin:063-gtp-common-conf 28_1648
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[17] origin:063-gtp-common-conf 29_1648
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[18] origin:063-gtp-common-conf 28_1649
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[19] origin:063-gtp-common-conf 29_1649
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[20] origin:063-gtp-common-conf 28_1650
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[21] origin:063-gtp-common-conf 29_1650
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[22] origin:063-gtp-common-conf 28_1651
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[23] origin:063-gtp-common-conf 29_1651
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[24] origin:063-gtp-common-conf 28_1652
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[25] origin:063-gtp-common-conf 29_1652
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[26] origin:063-gtp-common-conf 28_1653
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[27] origin:063-gtp-common-conf 29_1653
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[28] origin:063-gtp-common-conf 28_1654
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[29] origin:063-gtp-common-conf 29_1654
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[30] origin:063-gtp-common-conf 28_1655
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[31] origin:063-gtp-common-conf 29_1655
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[32] origin:063-gtp-common-conf 28_1656
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[33] origin:063-gtp-common-conf 29_1656
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[34] origin:063-gtp-common-conf 28_1657
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[35] origin:063-gtp-common-conf 29_1657
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[36] origin:063-gtp-common-conf 28_1658
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[37] origin:063-gtp-common-conf 29_1658
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[38] origin:063-gtp-common-conf 28_1659
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[39] origin:063-gtp-common-conf 29_1659
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[40] origin:063-gtp-common-conf 28_1660
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[41] origin:063-gtp-common-conf 29_1660
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[42] origin:063-gtp-common-conf 28_1661
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[43] origin:063-gtp-common-conf 29_1661
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[44] origin:063-gtp-common-conf 28_1662
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[45] origin:063-gtp-common-conf 29_1662
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[46] origin:063-gtp-common-conf 28_1663
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[47] origin:063-gtp-common-conf 29_1663
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[48] origin:063-gtp-common-conf 28_1664
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[49] origin:063-gtp-common-conf 29_1664
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[50] origin:063-gtp-common-conf 28_1665
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[51] origin:063-gtp-common-conf 29_1665
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[52] origin:063-gtp-common-conf 28_1666
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[53] origin:063-gtp-common-conf 29_1666
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[54] origin:063-gtp-common-conf 28_1667
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[55] origin:063-gtp-common-conf 29_1667
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[56] origin:063-gtp-common-conf 28_1668
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[57] origin:063-gtp-common-conf 29_1668
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[58] origin:063-gtp-common-conf 28_1669
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[59] origin:063-gtp-common-conf 29_1669
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[60] origin:063-gtp-common-conf 28_1670
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[61] origin:063-gtp-common-conf 29_1670
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[62] origin:063-gtp-common-conf 28_1671
GTP_COMMON.GTPE2_COMMON.BIAS_CFG[63] origin:063-gtp-common-conf 29_1671
GTP_COMMON.GTPE2_COMMON.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 29_1439 29_1807
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[0] origin:063-gtp-common-conf 28_1544
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[1] origin:063-gtp-common-conf 29_1544
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[2] origin:063-gtp-common-conf 28_1545
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[3] origin:063-gtp-common-conf 29_1545
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[4] origin:063-gtp-common-conf 28_1546
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[5] origin:063-gtp-common-conf 29_1546
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[6] origin:063-gtp-common-conf 28_1547
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[7] origin:063-gtp-common-conf 29_1547
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[8] origin:063-gtp-common-conf 28_1548
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[9] origin:063-gtp-common-conf 29_1548
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[10] origin:063-gtp-common-conf 28_1549
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[11] origin:063-gtp-common-conf 29_1549
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[12] origin:063-gtp-common-conf 28_1550
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[13] origin:063-gtp-common-conf 29_1550
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[14] origin:063-gtp-common-conf 28_1551
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[15] origin:063-gtp-common-conf 29_1551
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[16] origin:063-gtp-common-conf 28_1552
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[17] origin:063-gtp-common-conf 29_1552
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[18] origin:063-gtp-common-conf 28_1553
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[19] origin:063-gtp-common-conf 29_1553
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[20] origin:063-gtp-common-conf 28_1554
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[21] origin:063-gtp-common-conf 29_1554
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[22] origin:063-gtp-common-conf 28_1555
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[23] origin:063-gtp-common-conf 29_1555
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[24] origin:063-gtp-common-conf 28_1556
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[25] origin:063-gtp-common-conf 29_1556
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[26] origin:063-gtp-common-conf 28_1557
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[27] origin:063-gtp-common-conf 29_1557
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[28] origin:063-gtp-common-conf 28_1558
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[29] origin:063-gtp-common-conf 29_1558
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[30] origin:063-gtp-common-conf 28_1559
GTP_COMMON.GTPE2_COMMON.COMMON_CFG[31] origin:063-gtp-common-conf 29_1559
GTP_COMMON.GTPE2_COMMON.ENABLE_DRP origin:063-gtp-common-conf 24_1613 25_1613
GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] origin:063-gtp-common-conf 29_1581
GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] origin:063-gtp-common-conf 28_1582
GTP_COMMON.GTPE2_COMMON.IN_USE origin:063-gtp-common-conf 28_1584
GTP_COMMON.GTPE2_COMMON.INV_DRPCLK origin:063-gtp-common-conf 28_1516
GTP_COMMON.GTPE2_COMMON.INV_PLL0LOCKDETCLK origin:063-gtp-common-conf 29_1512
GTP_COMMON.GTPE2_COMMON.INV_PLL1LOCKDETCLK origin:063-gtp-common-conf 28_1512
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 28_1560
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 29_1560
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 28_1561
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 29_1561
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 28_1562
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 29_1562
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 28_1563
GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 29_1563
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[0] origin:063-gtp-common-conf 28_1488
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[1] origin:063-gtp-common-conf 29_1488
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[2] origin:063-gtp-common-conf 28_1489
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[3] origin:063-gtp-common-conf 29_1489
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[4] origin:063-gtp-common-conf 28_1490
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[5] origin:063-gtp-common-conf 29_1490
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[6] origin:063-gtp-common-conf 28_1491
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[7] origin:063-gtp-common-conf 29_1491
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[8] origin:063-gtp-common-conf 28_1492
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[9] origin:063-gtp-common-conf 29_1492
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[10] origin:063-gtp-common-conf 28_1493
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[11] origin:063-gtp-common-conf 29_1493
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[12] origin:063-gtp-common-conf 28_1494
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[13] origin:063-gtp-common-conf 29_1494
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[14] origin:063-gtp-common-conf 28_1495
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[15] origin:063-gtp-common-conf 29_1495
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[0] origin:063-gtp-common-conf 28_1728
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[1] origin:063-gtp-common-conf 29_1728
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[2] origin:063-gtp-common-conf 28_1729
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[3] origin:063-gtp-common-conf 29_1729
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[4] origin:063-gtp-common-conf 28_1730
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[5] origin:063-gtp-common-conf 29_1730
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[6] origin:063-gtp-common-conf 28_1731
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[7] origin:063-gtp-common-conf 29_1731
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[8] origin:063-gtp-common-conf 28_1732
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[9] origin:063-gtp-common-conf 29_1732
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[10] origin:063-gtp-common-conf 28_1733
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[11] origin:063-gtp-common-conf 29_1733
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[12] origin:063-gtp-common-conf 28_1734
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[13] origin:063-gtp-common-conf 29_1734
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[14] origin:063-gtp-common-conf 28_1735
GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[15] origin:063-gtp-common-conf 29_1735
GTP_COMMON.GTPE2_COMMON.GTREFCLK0_USED origin:063-gtp-common-conf 28_1438 28_1806
GTP_COMMON.GTPE2_COMMON.GTREFCLK1_USED origin:063-gtp-common-conf 29_1438 29_1806
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[0] origin:063-gtp-common-conf 28_1424
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[1] origin:063-gtp-common-conf 29_1424
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[2] origin:063-gtp-common-conf 28_1425
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[3] origin:063-gtp-common-conf 29_1425
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[4] origin:063-gtp-common-conf 28_1426
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[5] origin:063-gtp-common-conf 29_1426
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[6] origin:063-gtp-common-conf 28_1427
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[7] origin:063-gtp-common-conf 29_1427
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[8] origin:063-gtp-common-conf 28_1428
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[9] origin:063-gtp-common-conf 29_1428
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[10] origin:063-gtp-common-conf 28_1429
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[11] origin:063-gtp-common-conf 29_1429
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[12] origin:063-gtp-common-conf 28_1430
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[13] origin:063-gtp-common-conf 29_1430
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[14] origin:063-gtp-common-conf 28_1431
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[15] origin:063-gtp-common-conf 29_1431
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[16] origin:063-gtp-common-conf 28_1432
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[17] origin:063-gtp-common-conf 29_1432
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[18] origin:063-gtp-common-conf 28_1433
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[19] origin:063-gtp-common-conf 29_1433
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[20] origin:063-gtp-common-conf 28_1434
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[21] origin:063-gtp-common-conf 29_1434
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[22] origin:063-gtp-common-conf 28_1435
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[23] origin:063-gtp-common-conf 29_1435
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[24] origin:063-gtp-common-conf 28_1436
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[25] origin:063-gtp-common-conf 29_1436
GTP_COMMON.GTPE2_COMMON.PLL0_CFG[26] origin:063-gtp-common-conf 28_1437
GTP_COMMON.GTPE2_COMMON.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 28_1528
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[0] origin:063-gtp-common-conf 28_1440
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[1] origin:063-gtp-common-conf 29_1440
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[4] origin:063-gtp-common-conf 28_1442
GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 29_1443
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 28_1456
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 29_1456
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 28_1457
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 29_1457
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 28_1458
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 29_1458
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 28_1459
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 29_1459
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 28_1460
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 29_1460
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 28_1461
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 29_1461
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 28_1462
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 29_1462
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 28_1463
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 29_1463
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 28_1464
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 29_1464
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 28_1465
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 29_1465
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 28_1466
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 29_1466
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 28_1467
GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 29_1467
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 28_1448
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 29_1448
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 28_1449
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 29_1449
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 28_1450
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 29_1450
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 28_1451
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 29_1451
GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 28_1452
GTP_COMMON.GTPE2_COMMON.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1446
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[0] origin:063-gtp-common-conf 28_1792
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[1] origin:063-gtp-common-conf 29_1792
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[2] origin:063-gtp-common-conf 28_1793
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[3] origin:063-gtp-common-conf 29_1793
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[4] origin:063-gtp-common-conf 28_1794
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[5] origin:063-gtp-common-conf 29_1794
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[6] origin:063-gtp-common-conf 28_1795
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[7] origin:063-gtp-common-conf 29_1795
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[8] origin:063-gtp-common-conf 28_1796
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[9] origin:063-gtp-common-conf 29_1796
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[10] origin:063-gtp-common-conf 28_1797
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[11] origin:063-gtp-common-conf 29_1797
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[12] origin:063-gtp-common-conf 28_1798
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[13] origin:063-gtp-common-conf 29_1798
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[14] origin:063-gtp-common-conf 28_1799
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[15] origin:063-gtp-common-conf 29_1799
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[16] origin:063-gtp-common-conf 28_1800
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[17] origin:063-gtp-common-conf 29_1800
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[18] origin:063-gtp-common-conf 28_1801
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[19] origin:063-gtp-common-conf 29_1801
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[20] origin:063-gtp-common-conf 28_1802
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[21] origin:063-gtp-common-conf 29_1802
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[22] origin:063-gtp-common-conf 28_1803
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[23] origin:063-gtp-common-conf 29_1803
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[24] origin:063-gtp-common-conf 28_1804
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[25] origin:063-gtp-common-conf 29_1804
GTP_COMMON.GTPE2_COMMON.PLL1_CFG[26] origin:063-gtp-common-conf 28_1805
GTP_COMMON.GTPE2_COMMON.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 29_1528
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[0] origin:063-gtp-common-conf 28_1784
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[1] origin:063-gtp-common-conf 29_1784
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[4] origin:063-gtp-common-conf 28_1786
GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 29_1787
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 28_1760
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 29_1760
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 28_1761
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 29_1761
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 28_1762
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 29_1762
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 28_1763
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 29_1763
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 28_1764
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 29_1764
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 28_1765
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 29_1765
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 28_1766
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 29_1766
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 28_1767
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 29_1767
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 28_1768
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 29_1768
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 28_1769
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 29_1769
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 28_1770
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 29_1770
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 28_1771
GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 29_1771
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 28_1776
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 29_1776
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 28_1777
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 29_1777
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 28_1778
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 29_1778
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 28_1779
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 29_1779
GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 28_1780
GTP_COMMON.GTPE2_COMMON.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1790

556
artix7/segbits_gtp_common_mid_left.db
View File

@ -1,4 +1,3 @@
GTP_COMMON_MID_LEFT.ENABLE_DRP 00_1613 01_1613
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 02_1614 03_1617 03_1622
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 02_1614 02_1622 03_1616
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX 02_1615 03_1617
@ -167,8 +166,6 @@ GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 06_1623 07_1617
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 06_1620 07_1617
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 06_1623 07_1616
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 06_1620 07_1616
GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[0] 01_1581
GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[1] 00_1582
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKCM_CFG 00_1580
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKRCV_TRST 00_1576
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.IN_USE 00_1578
@ -177,103 +174,150 @@ GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKRCV_TRST 01_1576
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.IN_USE 00_1579
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT 07_1629
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT 06_1627
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[0] 00_1640
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[1] 01_1640
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[2] 00_1641
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[3] 01_1641
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[4] 00_1642
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[5] 01_1642
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[6] 00_1643
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[7] 01_1643
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[8] 00_1644
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[9] 01_1644
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[10] 00_1645
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[11] 01_1645
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[12] 00_1646
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[13] 01_1646
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[14] 00_1647
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[15] 01_1647
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[16] 00_1648
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[17] 01_1648
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[18] 00_1649
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[19] 01_1649
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[20] 00_1650
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[21] 01_1650
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[22] 00_1651
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[23] 01_1651
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[24] 00_1652
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[25] 01_1652
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[26] 00_1653
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[27] 01_1653
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[28] 00_1654
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[29] 01_1654
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[30] 00_1655
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[31] 01_1655
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[32] 00_1656
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[33] 01_1656
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[34] 00_1657
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[35] 01_1657
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[36] 00_1658
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[37] 01_1658
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[38] 00_1659
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[39] 01_1659
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[40] 00_1660
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[41] 01_1660
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[42] 00_1661
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[43] 01_1661
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[44] 00_1662
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[45] 01_1662
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[46] 00_1663
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[47] 01_1663
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[48] 00_1664
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[49] 01_1664
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[50] 00_1665
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[51] 01_1665
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[52] 00_1666
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[53] 01_1666
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[54] 00_1667
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[55] 01_1667
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[56] 00_1668
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[57] 01_1668
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[58] 00_1669
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[59] 01_1669
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[60] 00_1670
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[61] 01_1670
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[62] 00_1671
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[63] 01_1671
GTP_COMMON_MID_LEFT.GTPE2.BOTH_GTREFCLK_USED 01_1439 01_1807
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[0] 00_1544
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[1] 01_1544
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[2] 00_1545
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[3] 01_1545
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[4] 00_1546
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[5] 01_1546
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[6] 00_1547
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[7] 01_1547
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[8] 00_1548
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[9] 01_1548
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[10] 00_1549
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[11] 01_1549
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[12] 00_1550
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[13] 01_1550
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[14] 00_1551
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[15] 01_1551
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[16] 00_1552
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[17] 01_1552
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[18] 00_1553
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[19] 01_1553
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[20] 00_1554
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[21] 01_1554
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[22] 00_1555
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[23] 01_1555
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[24] 00_1556
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[25] 01_1556
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[26] 00_1557
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[27] 01_1557
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[28] 00_1558
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[29] 01_1558
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[30] 00_1559
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[31] 01_1559
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[0] 00_1640
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[1] 01_1640
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[2] 00_1641
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[3] 01_1641
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[4] 00_1642
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[5] 01_1642
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[6] 00_1643
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[7] 01_1643
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[8] 00_1644
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[9] 01_1644
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[10] 00_1645
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[11] 01_1645
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[12] 00_1646
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[13] 01_1646
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[14] 00_1647
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[15] 01_1647
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[16] 00_1648
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[17] 01_1648
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[18] 00_1649
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[19] 01_1649
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[20] 00_1650
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[21] 01_1650
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[22] 00_1651
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[23] 01_1651
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[24] 00_1652
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[25] 01_1652
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[26] 00_1653
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[27] 01_1653
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[28] 00_1654
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[29] 01_1654
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[30] 00_1655
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[31] 01_1655
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[32] 00_1656
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[33] 01_1656
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[34] 00_1657
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[35] 01_1657
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[36] 00_1658
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[37] 01_1658
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[38] 00_1659
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[39] 01_1659
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[40] 00_1660
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[41] 01_1660
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[42] 00_1661
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[43] 01_1661
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[44] 00_1662
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[45] 01_1662
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[46] 00_1663
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[47] 01_1663
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[48] 00_1664
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[49] 01_1664
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[50] 00_1665
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[51] 01_1665
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[52] 00_1666
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[53] 01_1666
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[54] 00_1667
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[55] 01_1667
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[56] 00_1668
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[57] 01_1668
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[58] 00_1669
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[59] 01_1669
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[60] 00_1670
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[61] 01_1670
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[62] 00_1671
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[63] 01_1671
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BOTH_GTREFCLK_USED 01_1439 01_1807
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[0] 00_1544
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[1] 01_1544
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[2] 00_1545
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[3] 01_1545
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[4] 00_1546
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[5] 01_1546
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[6] 00_1547
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[7] 01_1547
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[8] 00_1548
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[9] 01_1548
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[10] 00_1549
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[11] 01_1549
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[12] 00_1550
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[13] 01_1550
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[14] 00_1551
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[15] 01_1551
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[16] 00_1552
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[17] 01_1552
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[18] 00_1553
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[19] 01_1553
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[20] 00_1554
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[21] 01_1554
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[22] 00_1555
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[23] 01_1555
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[24] 00_1556
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[25] 01_1556
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[26] 00_1557
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[27] 01_1557
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[28] 00_1558
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[29] 01_1558
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[30] 00_1559
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[31] 01_1559
GTP_COMMON_MID_LEFT.GTPE2_COMMON.ENABLE_DRP 00_1613 01_1613
GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] 01_1581
GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] 00_1582
GTP_COMMON_MID_LEFT.GTPE2_COMMON.IN_USE 00_1584
GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_DRPCLK 00_1516
GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL0LOCKDETCLK 01_1512
GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL1LOCKDETCLK 00_1512
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] 00_1560
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] 01_1560
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] 00_1561
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] 01_1561
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] 00_1562
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] 01_1562
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] 00_1563
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] 01_1563
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[0] 00_1488
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[1] 01_1488
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[2] 00_1489
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[3] 01_1489
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[4] 00_1490
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[5] 01_1490
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[6] 00_1491
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[7] 01_1491
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[8] 00_1492
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[9] 01_1492
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[10] 00_1493
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[11] 01_1493
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[12] 00_1494
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[13] 01_1494
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[14] 00_1495
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[15] 01_1495
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[0] 00_1728
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[1] 01_1728
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[2] 00_1729
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[3] 01_1729
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[4] 00_1730
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[5] 01_1730
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[6] 00_1731
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[7] 01_1731
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[8] 00_1732
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[9] 01_1732
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[10] 00_1733
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[11] 01_1733
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[12] 00_1734
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[13] 01_1734
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[14] 00_1735
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[15] 01_1735
GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 06_1628
GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 07_1627
GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 07_1630
@ -282,181 +326,137 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 06_1629
GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 07_1628
GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 07_1631
GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 06_1631
GTP_COMMON_MID_LEFT.GTPE2.IN_USE 00_1584
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[0] 00_1560
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[1] 01_1560
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[2] 00_1561
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[3] 01_1561
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[4] 00_1562
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[5] 01_1562
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[6] 00_1563
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[7] 01_1563
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[0] 00_1488
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[1] 01_1488
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[2] 00_1489
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[3] 01_1489
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[4] 00_1490
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[5] 01_1490
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[6] 00_1491
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[7] 01_1491
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[8] 00_1492
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[9] 01_1492
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[10] 00_1493
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[11] 01_1493
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[12] 00_1494
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[13] 01_1494
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[14] 00_1495
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[15] 01_1495
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[0] 00_1728
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[1] 01_1728
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[2] 00_1729
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[3] 01_1729
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[4] 00_1730
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[5] 01_1730
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[6] 00_1731
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[7] 01_1731
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[8] 00_1732
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[9] 01_1732
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[10] 00_1733
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[11] 01_1733
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[12] 00_1734
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[13] 01_1734
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[14] 00_1735
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[15] 01_1735
GTP_COMMON_MID_LEFT.GTPE2.ZINV_DRPCLK 00_1516
GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL0LOCKDETCLK 01_1512
GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL1LOCKDETCLK 00_1512
GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK0_USED 00_1438 00_1806
GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK1_USED 01_1438 01_1806
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[0] 00_1424
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[1] 01_1424
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[2] 00_1425
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[3] 01_1425
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[4] 00_1426
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[5] 01_1426
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[6] 00_1427
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[7] 01_1427
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[8] 00_1428
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[9] 01_1428
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[10] 00_1429
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[11] 01_1429
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[12] 00_1430
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[13] 01_1430
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[14] 00_1431
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[15] 01_1431
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[16] 00_1432
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[17] 01_1432
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[18] 00_1433
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[19] 01_1433
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[20] 00_1434
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[21] 01_1434
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[22] 00_1435
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[23] 01_1435
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[24] 00_1436
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[25] 01_1436
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[26] 00_1437
GTP_COMMON_MID_LEFT.GTPE2.PLL0_DMON_CFG[0] 00_1528
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[0] 00_1440
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[1] 01_1440
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[4] 00_1442
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV_45[0] 01_1443
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[0] 00_1456
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[1] 01_1456
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[2] 00_1457
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[3] 01_1457
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[4] 00_1458
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[5] 01_1458
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[6] 00_1459
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[7] 01_1459
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[8] 00_1460
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[9] 01_1460
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[10] 00_1461
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[11] 01_1461
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[12] 00_1462
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[13] 01_1462
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[14] 00_1463
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[15] 01_1463
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[16] 00_1464
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[17] 01_1464
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[18] 00_1465
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[19] 01_1465
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[20] 00_1466
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[21] 01_1466
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[22] 00_1467
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[23] 01_1467
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[0] 00_1448
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[1] 01_1448
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[2] 00_1449
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[3] 01_1449
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[4] 00_1450
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[5] 01_1450
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[6] 00_1451
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[7] 01_1451
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[8] 00_1452
GTP_COMMON_MID_LEFT.GTPE2.PLL0_REFCLK_DIV[4] 01_1446
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[0] 00_1792
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[1] 01_1792
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[2] 00_1793
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[3] 01_1793
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[4] 00_1794
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[5] 01_1794
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[6] 00_1795
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[7] 01_1795
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[8] 00_1796
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[9] 01_1796
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[10] 00_1797
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[11] 01_1797
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[12] 00_1798
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[13] 01_1798
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[14] 00_1799
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[15] 01_1799
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[16] 00_1800
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[17] 01_1800
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[18] 00_1801
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[19] 01_1801
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[20] 00_1802
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[21] 01_1802
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[22] 00_1803
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[23] 01_1803
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[24] 00_1804
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[25] 01_1804
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[26] 00_1805
GTP_COMMON_MID_LEFT.GTPE2.PLL1_DMON_CFG[0] 01_1528
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[0] 00_1784
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[1] 01_1784
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[4] 00_1786
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV_45[0] 01_1787
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[0] 00_1760
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[1] 01_1760
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[2] 00_1761
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[3] 01_1761
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[4] 00_1762
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[5] 01_1762
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[6] 00_1763
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[7] 01_1763
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[8] 00_1764
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[9] 01_1764
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[10] 00_1765
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[11] 01_1765
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[12] 00_1766
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[13] 01_1766
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[14] 00_1767
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[15] 01_1767
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[16] 00_1768
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[17] 01_1768
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[18] 00_1769
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[19] 01_1769
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[20] 00_1770
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[21] 01_1770
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[22] 00_1771
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[23] 01_1771
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[0] 00_1776
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[1] 01_1776
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[2] 00_1777
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[3] 01_1777
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[4] 00_1778
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[5] 01_1778
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[6] 00_1779
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[7] 01_1779
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[8] 00_1780
GTP_COMMON_MID_LEFT.GTPE2.PLL1_REFCLK_DIV[4] 01_1790
GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK0_USED 00_1438 00_1806
GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK1_USED 01_1438 01_1806
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[0] 00_1424
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[1] 01_1424
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[2] 00_1425
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[3] 01_1425
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[4] 00_1426
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[5] 01_1426
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[6] 00_1427
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[7] 01_1427
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[8] 00_1428
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[9] 01_1428
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[10] 00_1429
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[11] 01_1429
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[12] 00_1430
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[13] 01_1430
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[14] 00_1431
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[15] 01_1431
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[16] 00_1432
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[17] 01_1432
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[18] 00_1433
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[19] 01_1433
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[20] 00_1434
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[21] 01_1434
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[22] 00_1435
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[23] 01_1435
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[24] 00_1436
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[25] 01_1436
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[26] 00_1437
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_DMON_CFG[0] 00_1528
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[0] 00_1440
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[1] 01_1440
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[4] 00_1442
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV_45[0] 01_1443
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[0] 00_1456
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[1] 01_1456
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[2] 00_1457
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[3] 01_1457
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[4] 00_1458
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[5] 01_1458
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[6] 00_1459
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[7] 01_1459
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[8] 00_1460
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[9] 01_1460
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[10] 00_1461
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[11] 01_1461
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[12] 00_1462
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[13] 01_1462
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[14] 00_1463
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[15] 01_1463
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[16] 00_1464
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[17] 01_1464
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[18] 00_1465
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[19] 01_1465
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[20] 00_1466
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[21] 01_1466
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[22] 00_1467
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[23] 01_1467
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[0] 00_1448
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[1] 01_1448
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[2] 00_1449
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[3] 01_1449
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[4] 00_1450
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[5] 01_1450
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[6] 00_1451
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[7] 01_1451
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[8] 00_1452
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] 01_1446
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[0] 00_1792
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[1] 01_1792
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[2] 00_1793
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[3] 01_1793
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[4] 00_1794
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[5] 01_1794
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[6] 00_1795
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[7] 01_1795
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[8] 00_1796
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[9] 01_1796
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[10] 00_1797
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[11] 01_1797
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[12] 00_1798
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[13] 01_1798
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[14] 00_1799
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[15] 01_1799
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[16] 00_1800
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[17] 01_1800
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[18] 00_1801
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[19] 01_1801
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[20] 00_1802
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[21] 01_1802
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[22] 00_1803
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[23] 01_1803
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[24] 00_1804
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[25] 01_1804
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[26] 00_1805
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_DMON_CFG[0] 01_1528
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[0] 00_1784
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[1] 01_1784
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[4] 00_1786
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV_45[0] 01_1787
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[0] 00_1760
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[1] 01_1760
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[2] 00_1761
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[3] 01_1761
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[4] 00_1762
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[5] 01_1762
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[6] 00_1763
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[7] 01_1763
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[8] 00_1764
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[9] 01_1764
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[10] 00_1765
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[11] 01_1765
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[12] 00_1766
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[13] 01_1766
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[14] 00_1767
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[15] 01_1767
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[16] 00_1768
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[17] 01_1768
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[18] 00_1769
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[19] 01_1769
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[20] 00_1770
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[21] 01_1770
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[22] 00_1771
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[23] 01_1771
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[0] 00_1776
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[1] 01_1776
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[2] 00_1777
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[3] 01_1777
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[4] 00_1778
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[5] 01_1778
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[6] 00_1779
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[7] 01_1779
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[8] 00_1780
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] 01_1790

556
artix7/segbits_gtp_common_mid_left.origin_info.db
View File

@ -1,4 +1,3 @@
GTP_COMMON_MID_LEFT.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 origin:065b-gtp-common-pips 02_1614 03_1617 03_1622
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 origin:065b-gtp-common-pips 02_1614 02_1622 03_1616
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX origin:065-gtp-common-pips 02_1615 03_1617
@ -167,8 +166,6 @@ GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 origin:065-gtp-
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 origin:065-gtp-common-pips 06_1620 07_1617
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 origin:065-gtp-common-pips 06_1623 07_1616
GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 origin:065-gtp-common-pips 06_1620 07_1616
GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 01_1581
GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 00_1582
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 00_1580
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 00_1576
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 00_1578
@ -177,103 +174,150 @@ GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 01_157
GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 00_1579
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT origin:065-gtp-common-pips 07_1629
GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT origin:065-gtp-common-pips 06_1627
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671
GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671
GTP_COMMON_MID_LEFT.GTPE2.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559
GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671
GTP_COMMON_MID_LEFT.GTPE2_COMMON.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559
GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559
GTP_COMMON_MID_LEFT.GTPE2_COMMON.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613
GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] origin:063-gtp-common-conf 01_1581
GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] origin:063-gtp-common-conf 00_1582
GTP_COMMON_MID_LEFT.GTPE2_COMMON.IN_USE origin:063-gtp-common-conf 00_1584
GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_DRPCLK origin:063-gtp-common-conf 00_1516
GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512
GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735
GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735
GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 origin:065-gtp-common-pips 06_1628
GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 origin:065-gtp-common-pips 07_1627
GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 origin:065-gtp-common-pips 07_1630
@ -282,181 +326,137 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 origin:0
GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 origin:065-gtp-common-pips 07_1628
GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 origin:065-gtp-common-pips 07_1631
GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 origin:065-gtp-common-pips 06_1631
GTP_COMMON_MID_LEFT.GTPE2.IN_USE origin:063-gtp-common-conf 00_1584
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563
GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735
GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735
GTP_COMMON_MID_LEFT.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 00_1516
GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512
GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512
GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806
GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436
GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437
GTP_COMMON_MID_LEFT.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442
GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467
GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451
GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452
GTP_COMMON_MID_LEFT.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804
GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805
GTP_COMMON_MID_LEFT.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786
GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771
GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779
GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780
GTP_COMMON_MID_LEFT.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790
GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806
GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780
GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790

556
artix7/segbits_gtp_common_mid_right.db
View File

@ -1,4 +1,3 @@
GTP_COMMON_MID_RIGHT.ENABLE_DRP 00_1613 01_1613
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 02_1614 03_1617 03_1622
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 02_1614 02_1622 03_1616
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX 02_1615 03_1617
@ -167,8 +166,6 @@ GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 06_1623 07_161
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 06_1620 07_1617
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 06_1623 07_1616
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 06_1620 07_1616
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[0] 01_1581
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[1] 00_1582
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKCM_CFG 00_1580
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKRCV_TRST 00_1576
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.IN_USE 00_1578
@ -177,103 +174,150 @@ GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKRCV_TRST 01_1576
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.IN_USE 00_1579
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT 07_1629
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT 06_1627
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[0] 00_1640
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[1] 01_1640
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[2] 00_1641
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[3] 01_1641
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[4] 00_1642
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[5] 01_1642
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[6] 00_1643
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[7] 01_1643
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[8] 00_1644
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[9] 01_1644
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[10] 00_1645
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[11] 01_1645
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[12] 00_1646
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[13] 01_1646
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[14] 00_1647
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[15] 01_1647
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[16] 00_1648
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[17] 01_1648
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[18] 00_1649
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[19] 01_1649
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[20] 00_1650
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[21] 01_1650
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[22] 00_1651
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[23] 01_1651
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[24] 00_1652
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[25] 01_1652
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[26] 00_1653
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[27] 01_1653
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[28] 00_1654
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[29] 01_1654
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[30] 00_1655
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[31] 01_1655
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[32] 00_1656
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[33] 01_1656
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[34] 00_1657
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[35] 01_1657
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[36] 00_1658
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[37] 01_1658
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[38] 00_1659
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[39] 01_1659
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[40] 00_1660
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[41] 01_1660
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[42] 00_1661
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[43] 01_1661
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[44] 00_1662
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[45] 01_1662
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[46] 00_1663
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[47] 01_1663
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[48] 00_1664
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[49] 01_1664
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[50] 00_1665
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[51] 01_1665
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[52] 00_1666
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[53] 01_1666
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[54] 00_1667
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[55] 01_1667
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[56] 00_1668
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[57] 01_1668
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[58] 00_1669
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[59] 01_1669
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[60] 00_1670
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[61] 01_1670
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[62] 00_1671
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[63] 01_1671
GTP_COMMON_MID_RIGHT.GTPE2.BOTH_GTREFCLK_USED 01_1439 01_1807
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[0] 00_1544
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[1] 01_1544
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[2] 00_1545
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[3] 01_1545
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[4] 00_1546
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[5] 01_1546
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[6] 00_1547
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[7] 01_1547
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[8] 00_1548
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[9] 01_1548
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[10] 00_1549
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[11] 01_1549
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[12] 00_1550
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[13] 01_1550
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[14] 00_1551
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[15] 01_1551
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[16] 00_1552
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[17] 01_1552
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[18] 00_1553
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[19] 01_1553
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[20] 00_1554
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[21] 01_1554
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[22] 00_1555
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[23] 01_1555
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[24] 00_1556
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[25] 01_1556
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[26] 00_1557
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[27] 01_1557
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[28] 00_1558
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[29] 01_1558
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[30] 00_1559
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[31] 01_1559
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[0] 00_1640
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[1] 01_1640
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[2] 00_1641
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[3] 01_1641
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[4] 00_1642
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[5] 01_1642
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[6] 00_1643
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[7] 01_1643
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[8] 00_1644
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[9] 01_1644
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[10] 00_1645
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[11] 01_1645
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[12] 00_1646
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[13] 01_1646
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[14] 00_1647
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[15] 01_1647
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[16] 00_1648
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[17] 01_1648
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[18] 00_1649
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[19] 01_1649
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[20] 00_1650
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[21] 01_1650
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[22] 00_1651
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[23] 01_1651
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[24] 00_1652
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[25] 01_1652
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[26] 00_1653
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[27] 01_1653
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[28] 00_1654
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[29] 01_1654
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[30] 00_1655
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[31] 01_1655
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[32] 00_1656
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[33] 01_1656
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[34] 00_1657
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[35] 01_1657
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[36] 00_1658
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[37] 01_1658
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[38] 00_1659
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[39] 01_1659
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[40] 00_1660
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[41] 01_1660
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[42] 00_1661
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[43] 01_1661
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[44] 00_1662
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[45] 01_1662
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[46] 00_1663
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[47] 01_1663
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[48] 00_1664
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[49] 01_1664
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[50] 00_1665
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[51] 01_1665
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[52] 00_1666
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[53] 01_1666
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[54] 00_1667
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[55] 01_1667
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[56] 00_1668
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[57] 01_1668
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[58] 00_1669
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[59] 01_1669
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[60] 00_1670
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[61] 01_1670
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[62] 00_1671
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[63] 01_1671
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BOTH_GTREFCLK_USED 01_1439 01_1807
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[0] 00_1544
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[1] 01_1544
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[2] 00_1545
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[3] 01_1545
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[4] 00_1546
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[5] 01_1546
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[6] 00_1547
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[7] 01_1547
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[8] 00_1548
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[9] 01_1548
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[10] 00_1549
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[11] 01_1549
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[12] 00_1550
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[13] 01_1550
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[14] 00_1551
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[15] 01_1551
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[16] 00_1552
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[17] 01_1552
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[18] 00_1553
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[19] 01_1553
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[20] 00_1554
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[21] 01_1554
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[22] 00_1555
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[23] 01_1555
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[24] 00_1556
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[25] 01_1556
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[26] 00_1557
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[27] 01_1557
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[28] 00_1558
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[29] 01_1558
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[30] 00_1559
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[31] 01_1559
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.ENABLE_DRP 00_1613 01_1613
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] 01_1581
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] 00_1582
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IN_USE 00_1584
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_DRPCLK 00_1516
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL0LOCKDETCLK 01_1512
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL1LOCKDETCLK 00_1512
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] 00_1560
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] 01_1560
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] 00_1561
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] 01_1561
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] 00_1562
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] 01_1562
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] 00_1563
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] 01_1563
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[0] 00_1488
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[1] 01_1488
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[2] 00_1489
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[3] 01_1489
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[4] 00_1490
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[5] 01_1490
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[6] 00_1491
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[7] 01_1491
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[8] 00_1492
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[9] 01_1492
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[10] 00_1493
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[11] 01_1493
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[12] 00_1494
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[13] 01_1494
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[14] 00_1495
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[15] 01_1495
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[0] 00_1728
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[1] 01_1728
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[2] 00_1729
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[3] 01_1729
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[4] 00_1730
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[5] 01_1730
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[6] 00_1731
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[7] 01_1731
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[8] 00_1732
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[9] 01_1732
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[10] 00_1733
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[11] 01_1733
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[12] 00_1734
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[13] 01_1734
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[14] 00_1735
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[15] 01_1735
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 06_1628
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 07_1627
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 07_1630
@ -282,181 +326,137 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 06_1629
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 07_1628
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 07_1631
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 06_1631
GTP_COMMON_MID_RIGHT.GTPE2.IN_USE 00_1584
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[0] 00_1560
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[1] 01_1560
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[2] 00_1561
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[3] 01_1561
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[4] 00_1562
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[5] 01_1562
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[6] 00_1563
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[7] 01_1563
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[0] 00_1488
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[1] 01_1488
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[2] 00_1489
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[3] 01_1489
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[4] 00_1490
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[5] 01_1490
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[6] 00_1491
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[7] 01_1491
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[8] 00_1492
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[9] 01_1492
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[10] 00_1493
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[11] 01_1493
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[12] 00_1494
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[13] 01_1494
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[14] 00_1495
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[15] 01_1495
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[0] 00_1728
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[1] 01_1728
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[2] 00_1729
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[3] 01_1729
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[4] 00_1730
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[5] 01_1730
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[6] 00_1731
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[7] 01_1731
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[8] 00_1732
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[9] 01_1732
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[10] 00_1733
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[11] 01_1733
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[12] 00_1734
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[13] 01_1734
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[14] 00_1735
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[15] 01_1735
GTP_COMMON_MID_RIGHT.GTPE2.ZINV_DRPCLK 00_1516
GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL0LOCKDETCLK 01_1512
GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL1LOCKDETCLK 00_1512
GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK0_USED 00_1438 00_1806
GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK1_USED 01_1438 01_1806
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[0] 00_1424
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[1] 01_1424
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[2] 00_1425
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[3] 01_1425
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[4] 00_1426
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[5] 01_1426
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[6] 00_1427
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[7] 01_1427
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[8] 00_1428
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[9] 01_1428
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[10] 00_1429
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[11] 01_1429
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[12] 00_1430
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[13] 01_1430
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[14] 00_1431
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[15] 01_1431
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[16] 00_1432
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[17] 01_1432
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[18] 00_1433
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[19] 01_1433
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[20] 00_1434
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[21] 01_1434
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[22] 00_1435
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[23] 01_1435
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[24] 00_1436
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[25] 01_1436
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[26] 00_1437
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_DMON_CFG[0] 00_1528
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[0] 00_1440
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[1] 01_1440
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[4] 00_1442
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV_45[0] 01_1443
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[0] 00_1456
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[1] 01_1456
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[2] 00_1457
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[3] 01_1457
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[4] 00_1458
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[5] 01_1458
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[6] 00_1459
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[7] 01_1459
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[8] 00_1460
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[9] 01_1460
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[10] 00_1461
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[11] 01_1461
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[12] 00_1462
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[13] 01_1462
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[14] 00_1463
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[15] 01_1463
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[16] 00_1464
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[17] 01_1464
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[18] 00_1465
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[19] 01_1465
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[20] 00_1466
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[21] 01_1466
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[22] 00_1467
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[23] 01_1467
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[0] 00_1448
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[1] 01_1448
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[2] 00_1449
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[3] 01_1449
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[4] 00_1450
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[5] 01_1450
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[6] 00_1451
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[7] 01_1451
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[8] 00_1452
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_REFCLK_DIV[4] 01_1446
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[0] 00_1792
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[1] 01_1792
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[2] 00_1793
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[3] 01_1793
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[4] 00_1794
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[5] 01_1794
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[6] 00_1795
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[7] 01_1795
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[8] 00_1796
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[9] 01_1796
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[10] 00_1797
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[11] 01_1797
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[12] 00_1798
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[13] 01_1798
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[14] 00_1799
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[15] 01_1799
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[16] 00_1800
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[17] 01_1800
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[18] 00_1801
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[19] 01_1801
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[20] 00_1802
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[21] 01_1802
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[22] 00_1803
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[23] 01_1803
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[24] 00_1804
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[25] 01_1804
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[26] 00_1805
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_DMON_CFG[0] 01_1528
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[0] 00_1784
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[1] 01_1784
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[4] 00_1786
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV_45[0] 01_1787
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[0] 00_1760
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[1] 01_1760
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[2] 00_1761
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[3] 01_1761
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[4] 00_1762
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[5] 01_1762
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[6] 00_1763
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[7] 01_1763
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[8] 00_1764
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[9] 01_1764
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[10] 00_1765
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[11] 01_1765
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[12] 00_1766
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[13] 01_1766
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[14] 00_1767
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[15] 01_1767
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[16] 00_1768
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[17] 01_1768
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[18] 00_1769
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[19] 01_1769
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[20] 00_1770
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[21] 01_1770
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[22] 00_1771
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[23] 01_1771
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[0] 00_1776
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[1] 01_1776
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[2] 00_1777
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[3] 01_1777
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[4] 00_1778
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[5] 01_1778
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[6] 00_1779
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[7] 01_1779
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[8] 00_1780
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_REFCLK_DIV[4] 01_1790
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK0_USED 00_1438 00_1806
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK1_USED 01_1438 01_1806
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[0] 00_1424
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[1] 01_1424
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[2] 00_1425
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[3] 01_1425
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[4] 00_1426
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[5] 01_1426
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[6] 00_1427
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[7] 01_1427
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[8] 00_1428
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[9] 01_1428
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[10] 00_1429
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[11] 01_1429
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[12] 00_1430
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[13] 01_1430
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[14] 00_1431
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[15] 01_1431
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[16] 00_1432
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[17] 01_1432
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[18] 00_1433
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[19] 01_1433
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[20] 00_1434
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[21] 01_1434
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[22] 00_1435
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[23] 01_1435
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[24] 00_1436
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[25] 01_1436
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[26] 00_1437
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_DMON_CFG[0] 00_1528
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[0] 00_1440
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[1] 01_1440
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[4] 00_1442
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV_45[0] 01_1443
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[0] 00_1456
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[1] 01_1456
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[2] 00_1457
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[3] 01_1457
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[4] 00_1458
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[5] 01_1458
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[6] 00_1459
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[7] 01_1459
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[8] 00_1460
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[9] 01_1460
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[10] 00_1461
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[11] 01_1461
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[12] 00_1462
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[13] 01_1462
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[14] 00_1463
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[15] 01_1463
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[16] 00_1464
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[17] 01_1464
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[18] 00_1465
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[19] 01_1465
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[20] 00_1466
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[21] 01_1466
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[22] 00_1467
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[23] 01_1467
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[0] 00_1448
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[1] 01_1448
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[2] 00_1449
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[3] 01_1449
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[4] 00_1450
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[5] 01_1450
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[6] 00_1451
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[7] 01_1451
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[8] 00_1452
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] 01_1446
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[0] 00_1792
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[1] 01_1792
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[2] 00_1793
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[3] 01_1793
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[4] 00_1794
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[5] 01_1794
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[6] 00_1795
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[7] 01_1795
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[8] 00_1796
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[9] 01_1796
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[10] 00_1797
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[11] 01_1797
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[12] 00_1798
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[13] 01_1798
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[14] 00_1799
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[15] 01_1799
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[16] 00_1800
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[17] 01_1800
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[18] 00_1801
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[19] 01_1801
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[20] 00_1802
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[21] 01_1802
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[22] 00_1803
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[23] 01_1803
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[24] 00_1804
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[25] 01_1804
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[26] 00_1805
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_DMON_CFG[0] 01_1528
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[0] 00_1784
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[1] 01_1784
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[4] 00_1786
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV_45[0] 01_1787
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[0] 00_1760
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[1] 01_1760
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[2] 00_1761
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[3] 01_1761
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[4] 00_1762
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[5] 01_1762
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[6] 00_1763
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[7] 01_1763
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[8] 00_1764
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[9] 01_1764
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[10] 00_1765
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[11] 01_1765
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[12] 00_1766
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[13] 01_1766
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[14] 00_1767
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[15] 01_1767
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[16] 00_1768
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[17] 01_1768
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[18] 00_1769
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[19] 01_1769
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[20] 00_1770
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[21] 01_1770
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[22] 00_1771
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[23] 01_1771
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[0] 00_1776
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[1] 01_1776
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[2] 00_1777
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[3] 01_1777
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[4] 00_1778
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[5] 01_1778
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[6] 00_1779
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[7] 01_1779
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[8] 00_1780
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] 01_1790

556
artix7/segbits_gtp_common_mid_right.origin_info.db
View File

@ -1,4 +1,3 @@
GTP_COMMON_MID_RIGHT.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 origin:065b-gtp-common-pips 02_1614 03_1617 03_1622
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 origin:065b-gtp-common-pips 02_1614 02_1622 03_1616
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX origin:065-gtp-common-pips 02_1615 03_1617
@ -167,8 +166,6 @@ GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 origin:065-gtp
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 origin:065-gtp-common-pips 06_1620 07_1617
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 origin:065-gtp-common-pips 06_1623 07_1616
GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 origin:065-gtp-common-pips 06_1620 07_1616
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 01_1581
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 00_1582
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 00_1580
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 00_1576
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 00_1578
@ -177,103 +174,150 @@ GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 01_15
GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 00_1579
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT origin:065-gtp-common-pips 07_1629
GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT origin:065-gtp-common-pips 06_1627
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671
GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671
GTP_COMMON_MID_RIGHT.GTPE2.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559
GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] origin:063-gtp-common-conf 01_1581
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] origin:063-gtp-common-conf 00_1582
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IN_USE origin:063-gtp-common-conf 00_1584
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_DRPCLK origin:063-gtp-common-conf 00_1516
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 origin:065-gtp-common-pips 06_1628
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 origin:065-gtp-common-pips 07_1627
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 origin:065-gtp-common-pips 07_1630
@ -282,181 +326,137 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 origin:
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 origin:065-gtp-common-pips 07_1628
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 origin:065-gtp-common-pips 07_1631
GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 origin:065-gtp-common-pips 06_1631
GTP_COMMON_MID_RIGHT.GTPE2.IN_USE origin:063-gtp-common-conf 00_1584
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563
GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735
GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735
GTP_COMMON_MID_RIGHT.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 00_1516
GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512
GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512
GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806
GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452
GTP_COMMON_MID_RIGHT.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780
GTP_COMMON_MID_RIGHT.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780
GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790

14
artix7/segbits_int_l.origin_info.db
View File

@ -1877,7 +1877,7 @@ INT_L.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08
INT_L.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
INT_L.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
INT_L.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
INT_L.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
INT_L.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
INT_L.EE4BEG1.LOGIC_OUTS_L1 origin:050-pip-seed 02_25 07_25
INT_L.EE4BEG1.LOGIC_OUTS_L5 origin:050-pip-seed 02_25 04_26
INT_L.EE4BEG1.LOGIC_OUTS_L9 origin:050-pip-seed 03_24 04_26
@ -2253,7 +2253,7 @@ INT_L.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36
INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53
@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03
INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@ -2887,7 +2887,7 @@ INT_L.SE6BEG3.LH0 origin:056-pip-rem 04_59 06_58
INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@ -3302,7 +3302,7 @@ INT_L.SW6BEG1.LOGIC_OUTS_L19 origin:050-pip-seed 06_28 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28
INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28
INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28
@ -3323,7 +3323,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 06_44 07_45
INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@ -3568,7 +3568,7 @@ INT_L.WW4BEG0.SW6END_N0_3 origin:050-pip-seed 04_01 05_00
INT_L.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01
INT_L.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
INT_L.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
INT_L.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
INT_L.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
INT_L.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
INT_L.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
INT_L.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01

12
artix7/segbits_int_r.origin_info.db
View File

@ -665,7 +665,7 @@ INT_R.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08
INT_R.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
INT_R.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
INT_R.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
INT_R.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
INT_R.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
INT_R.EE4BEG1.LOGIC_OUTS1 origin:050-pip-seed 02_25 07_25
INT_R.EE4BEG1.LOGIC_OUTS5 origin:050-pip-seed 02_25 04_26
INT_R.EE4BEG1.LOGIC_OUTS9 origin:050-pip-seed 03_24 04_26
@ -705,7 +705,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_R.EE4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_57 07_57
INT_R.EE4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_57 04_58
INT_R.EE4BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_56 04_58
@ -725,7 +725,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@ -3568,7 +3568,7 @@ INT_R.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01
INT_R.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00
INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS21 origin:050-pip-seed 06_48 07_49
INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49

4
artix7/segbits_liob33.db
View File

@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07
LIOB33.IOB_Y1.INTERMDISABLE.I 38_38
LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
LIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32
LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41
LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21
LIOB33.OUT_DIFF 39_59 39_61

4
artix7/segbits_liob33.origin_info.db
View File

@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35
LIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33
@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32
LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63
@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63
LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40
LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17
LIOB33.OUT_DIFF origin:030-iob 39_59 39_61

4
artix7/segbits_riob33.db
View File

@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
RIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32
RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41
RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21
RIOB33.OUT_DIFF 39_59 39_61

4
artix7/segbits_riob33.origin_info.db
View File

@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35
RIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33
@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32
RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63
@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63
RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40
RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17
RIOB33.OUT_DIFF origin:030-iob 39_59 39_61

4
artix7/xc7a100t/tilegrid.json
View File

@ -176660,7 +176660,7 @@
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00421980",
"frames": 42,
"frames": 32,
"offset": 0,
"words": 101
}
@ -176690,7 +176690,7 @@
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00021980",
"frames": 42,
"frames": 32,
"offset": 0,
"words": 101
}

8
artix7/xc7a200t/tilegrid.json
View File

@ -382173,7 +382173,7 @@
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00441200",
"frames": 42,
"frames": 32,
"offset": 0,
"words": 101
}
@ -382203,7 +382203,7 @@
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00021200",
"frames": 42,
"frames": 32,
"offset": 0,
"words": 101
}
@ -382233,7 +382233,7 @@
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00442480",
"frames": 42,
"frames": 32,
"offset": 0,
"words": 101
}
@ -382263,7 +382263,7 @@
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00022480",
"frames": 42,
"frames": 32,
"offset": 0,
"words": 101
}

2
artix7/xc7a50t/tilegrid.json
View File

@ -91864,7 +91864,7 @@
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00021280",
"frames": 42,
"frames": 32,
"offset": 0,
"words": 101
}

1736
kintex7/ppips_pcie_bot.db Normal file
View File

File diff suppressed because it is too large Load Diff

120
kintex7/ppips_pcie_int_interface_l.db Normal file
View File

@ -0,0 +1,120 @@
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L_DELAY0 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L0 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L_DELAY1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L1 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L_DELAY2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L2 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L_DELAY3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L3 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L_DELAY4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L4 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L_DELAY5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L5 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L_DELAY6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L6 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L_DELAY7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L7 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L_DELAY8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L8 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L_DELAY9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L9 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L_DELAY10 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L10 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L_DELAY11 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L11 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L_DELAY12 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L12 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L_DELAY13 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L13 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_DELAY14 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L14 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L15 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L16 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L17 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L18 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L_DELAY19 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L19 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L_DELAY20 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L20 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L_DELAY21 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L21 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L_DELAY22 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L22 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L_DELAY23 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L23 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L_DELAY24 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L24 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L_DELAY25 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L25 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L_DELAY26 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L26 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L_DELAY27 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L27 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L_DELAY28 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L28 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L_DELAY29 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L29 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L_DELAY30 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L30 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L_DELAY31 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L31 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L32 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L33 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L_DELAY34 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L34 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L_DELAY35 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L35 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L_DELAY36 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L36 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L_DELAY37 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L37 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L_DELAY38 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L38 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L_DELAY39 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L39 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L_DELAY40 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L40 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L_DELAY41 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L41 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L_DELAY42 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L42 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L_DELAY43 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L43 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L_DELAY44 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L44 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L_DELAY45 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L45 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L_DELAY46 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L46 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L_DELAY47 always
PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L47 always

120
kintex7/ppips_pcie_int_interface_r.db Normal file
View File

@ -0,0 +1,120 @@
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX_DELAY0 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX0 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX_DELAY1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX1 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX_DELAY2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX2 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX_DELAY3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX3 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX_DELAY4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX4 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX_DELAY5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX5 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX_DELAY6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX6 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX_DELAY7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX7 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX_DELAY8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX8 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX_DELAY9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX9 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX_DELAY10 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX10 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX_DELAY11 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX11 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX_DELAY12 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX12 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX_DELAY13 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX13 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX_DELAY14 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX14 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX_DELAY15 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX15 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX_DELAY16 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX16 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX_DELAY17 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX17 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX_DELAY18 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX18 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX19 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX20 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX21 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX22 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX23 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX24 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX25 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX_DELAY26 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX26 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX_DELAY27 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX27 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX_DELAY28 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX28 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX_DELAY29 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX29 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX_DELAY30 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX30 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX_DELAY31 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX31 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX32 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX_DELAY33 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX33 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX_DELAY34 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX34 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX_DELAY35 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX35 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX_DELAY36 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX36 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX_DELAY37 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX37 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX_DELAY38 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX38 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX_DELAY39 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX39 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX_DELAY40 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX40 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX_DELAY41 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX41 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX_DELAY42 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX42 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX_DELAY43 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX43 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX_DELAY44 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX44 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX_DELAY45 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX45 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX_DELAY46 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX46 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX_DELAY47 always
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX47 always

441
kintex7/ppips_pcie_top.db Normal file
View File

@ -0,0 +1,441 @@
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_0.PCIE_TOP_TRNRD59 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_1.PCIE_TOP_TRNRD63 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_2.PCIE_TOP_TRNRD67 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_3.PCIE_TOP_TRNRD71 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_4.PCIE_TOP_TRNRD75 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_0.PCIE_TOP_MIMRXWDATA20 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_1.PCIE_TOP_MIMRXWDATA24 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_2.PCIE_TOP_MIMRXWADDR2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_3.PCIE_TOP_TRNRD83 always
PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_4.PCIE_TOP_TRNRD79 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_0.PCIE_TOP_TRNRD60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_1.PCIE_TOP_TRNRD64 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_2.PCIE_TOP_TRNRD68 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_3.PCIE_TOP_TRNRD72 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TOP_TRNRD76 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_0.PCIE_TOP_MIMRXWADDR12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TOP_TRNRD91 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_2.PCIE_TOP_MIMRXWDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_3.PCIE_TOP_TRNRD84 always
PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_4.PCIE_TOP_TRNTDSTRDY3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_0.PCIE_TOP_TRNRD61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_1.PCIE_TOP_TRNRD65 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_2.PCIE_TOP_TRNRD69 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TOP_TRNRD73 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_4.PCIE_TOP_TRNRD77 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_0.PCIE_TOP_TRNRD95 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TOP_MIMRXWDATA12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_2.PCIE_TOP_TRNRD87 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_3.PCIE_TOP_TRNRD85 always
PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_4.PCIE_TOP_TRNRD80 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_0.PCIE_TOP_TRNRD62 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_1.PCIE_TOP_TRNRD66 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_2.PCIE_TOP_TRNRD70 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_3.PCIE_TOP_TRNRD74 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TOP_TRNRD78 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TOP_MIMRXRADDR10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TOP_TRNRD92 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_2.PCIE_TOP_TRNRD88 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_3.PCIE_TOP_MIMRXWDATA9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_4.PCIE_TOP_TRNRD81 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_0.PCIE_TOP_TRNRDLLPDATA32 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TOP_TRNRDLLPDATA36 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_2.PCIE_TOP_TRNRDLLPDATA40 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TOP_TRNRDLLPDATA44 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_4.PCIE_TOP_TRNRDLLPDATA48 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_0.PCIE_TOP_TRNRD96 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TOP_TRNRD93 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_2.PCIE_TOP_TRNRD89 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TOP_TRNRD86 always
PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_4.PCIE_TOP_TRNRD82 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_0.PCIE_TOP_TRNRDLLPDATA33 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TOP_TRNRDLLPDATA37 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_2.PCIE_TOP_TRNRDLLPDATA41 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TOP_TRNRDLLPDATA45 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TOP_TRNRDLLPDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TOP_TRNRD97 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_1.PCIE_TOP_MIMRXWDATA49 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_2.PCIE_TOP_MIMRXRADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TOP_TRNRDLLPDATA56 always
PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TOP_TRNRDLLPDATA52 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_0.PCIE_TOP_PIPETXMARGIN2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TOP_TRNRDLLPDATA38 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_2.PCIE_TOP_TRNRDLLPDATA42 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TOP_TRNRDLLPDATA46 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_4.PCIE_TOP_TRNRDLLPDATA50 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_0.PCIE_TOP_TRNRD98 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_1.PCIE_TOP_TRNRD94 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_2.PCIE_TOP_TRNRD90 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_3.PCIE_TOP_TRNRDLLPDATA57 always
PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_4.PCIE_TOP_TRNRDLLPDATA53 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_0.PCIE_TOP_TRNRDLLPDATA34 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TOP_TRNRDLLPDATA39 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_2.PCIE_TOP_TRNRDLLPDATA43 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TOP_TRNRDLLPDATA47 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TOP_TRNRDLLPDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TOP_PL2SUSPENDOK always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_1.PCIE_TOP_MIMRXWDATA51 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_2.PCIE_TOP_TRNRDLLPDATA60 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_3.PCIE_TOP_TRNRDLLPDATA58 always
PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_4.PCIE_TOP_TRNRDLLPDATA54 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_0.PCIE_TOP_TRNRDLLPDATA35 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TOP_CFGPMRCVENTERL23N always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_2.PCIE_TOP_CFGPMCSRPMEEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TOP_CFGTRANSACTIONADDR0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TOP_CFGTRANSACTIONADDR4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TOP_MIMRXRADDR9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_1.PCIE_TOP_MIMRXWDATA8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TOP_TRNRDLLPDATA61 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_3.PCIE_TOP_MIMRXWDATA19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_4.PCIE_TOP_MIMRXWDATA29 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_0.PCIE_TOP_CFGPCIELINKSTATE1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_1.PCIE_TOP_CFGPMRCVREQACKN always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_2.PCIE_TOP_CFGPMCSRPMESTATUS always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_3.PCIE_TOP_CFGTRANSACTIONADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TOP_CFGTRANSACTIONADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_0.PCIE_TOP_MIMRXWDATA4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_1.PCIE_TOP_MIMRXWADDR5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_2.PCIE_TOP_MIMRXWDATA17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_3.PCIE_TOP_TRNRDLLPDATA59 always
PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_4.PCIE_TOP_MIMRXWDATA13 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_0.PCIE_TOP_CFGPCIELINKSTATE2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_2.PCIE_TOP_CFGTRANSACTION always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_3.PCIE_TOP_CFGTRANSACTIONADDR2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_4.PCIE_TOP_CFGTRANSACTIONADDR6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_0.PCIE_TOP_MIMRXRADDR11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_1.PCIE_TOP_TRNRDLLPSRCRDY0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_2.PCIE_TOP_TRNRDLLPDATA62 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_3.PCIE_TOP_MIMRXWDATA25 always
PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_4.PCIE_TOP_MIMRXWDATA15 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_0.PCIE_TOP_CFGPMRCVASREQL1N always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_2.PCIE_TOP_CFGTRANSACTIONTYPE always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_3.PCIE_TOP_CFGTRANSACTIONADDR3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_4.PCIE_TOP_CFGCOMMANDIOENABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_0.PCIE_TOP_MIMRXWDATA0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_1.PCIE_TOP_MIMRXRADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_2.PCIE_TOP_TRNRDLLPDATA63 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_3.PCIE_TOP_CFGMGMTDO20 always
PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_4.PCIE_TOP_MIMRXWDATA35 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_0.PCIE_TOP_CFGPMRCVENTERL1N always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_1.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_2.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_0.PCIE_TOP_PL2RECOVERY always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_1.PCIE_TOP_MIMRXREN always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_2.PCIE_TOP_MIMRXRADDR2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_3.PCIE_TOP_CFGMGMTDO21 always
PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_4.PCIE_TOP_TRNRDLLPDATA55 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_0.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_1.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_2.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_0.PCIE_TOP_MIMRXWDATA1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_1.PCIE_TOP_MIMRXWDATA26 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_2.PCIE_TOP_MIMRXRADDR0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_3.PCIE_TOP_CFGMGMTDO22 always
PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_4.PCIE_TOP_CFGMGMTDO24 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_0.PCIE_TOP_CFGLINKCONTROLRCB always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_1.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_4.PCIE_TOP_CFGDEVCONTROL2IDOREQEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_0.PCIE_TOP_DBGVECA18 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_1.PCIE_TOP_TRNRDLLPSRCRDY1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_2.PCIE_TOP_MIMRXWDATA28 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_3.PCIE_TOP_MIMRXWDATA23 always
PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_4.PCIE_TOP_CFGMGMTDO25 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_0.PCIE_TOP_CFGLINKCONTROLLINKDISABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_1.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_3.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_4.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_0.PCIE_TOP_MIMRXWDATA22 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_1.PCIE_TOP_MIMRXWADDR1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_2.PCIE_TOP_MIMRXWDATA3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_3.PCIE_TOP_CFGMGMTDO23 always
PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_4.PCIE_TOP_CFGMGMTDO26 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_0.PCIE_TOP_PIPETXMARGIN1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_1.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_2.PCIE_TOP_CFGVCTCVCMAP3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_3.PCIE_TOP_DRPRDY always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_4.PCIE_TOP_DRPDO3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_0.PCIE_TOP_MIMRXWDATA6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_1.PCIE_TOP_LL2TFCINIT1SEQ always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_2.PCIE_TOP_CFGMGMTDO17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_3.PCIE_TOP_CFGMGMTDO28 always
PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_4.PCIE_TOP_CFGMGMTDO27 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_0.PCIE_TOP_CFGLINKCONTROLRETRAINLINK always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_1.PCIE_TOP_CFGVCTCVCMAP0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_2.PCIE_TOP_CFGVCTCVCMAP4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_3.PCIE_TOP_DRPDO0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_4.PCIE_TOP_DRPDO4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_0.PCIE_TOP_MIMRXRADDR8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_1.PCIE_TOP_MIMRXWDATA34 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_2.PCIE_TOP_CFGMGMTDO18 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_3.PCIE_TOP_CFGMGMTDO29 always
PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_4.PCIE_TOP_CFGCOMMANDMEMENABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_0.PCIE_TOP_PIPETXMARGIN0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_1.PCIE_TOP_CFGVCTCVCMAP1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_2.PCIE_TOP_CFGVCTCVCMAP5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_3.PCIE_TOP_DRPDO1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_4.PCIE_TOP_DRPDO5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_0.PCIE_TOP_MIMRXWDATA2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_1.PCIE_TOP_MIMRXWEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_2.PCIE_TOP_MIMRXWDATA30 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_3.PCIE_TOP_CFGMGMTDO30 always
PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_4.PCIE_TOP_MIMRXWDATA11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_1.PCIE_TOP_CFGVCTCVCMAP2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_2.PCIE_TOP_CFGVCTCVCMAP6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_3.PCIE_TOP_DRPDO2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_4.PCIE_TOP_DRPDO6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_0.PCIE_TOP_DBGVECA19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_1.PCIE_TOP_MIMRXWDATA10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_2.PCIE_TOP_CFGMGMTDO19 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_3.PCIE_TOP_MIMRXWDATA21 always
PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_4.PCIE_TOP_MIMRXWDATA27 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_0.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_1.PCIE_TOP_DRPDO11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_2.PCIE_TOP_DRPDO15 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_3.PCIE_TOP_DBGVECA3 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_4.PCIE_TOP_DBGVECA7 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_0.PCIE_TOP_DBGVECA20 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_1.PCIE_TOP_LL2TFCINIT2SEQ always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_2.PCIE_TOP_DBGVECA14 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_3.PCIE_TOP_DBGVECA12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_4.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_0.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_1.PCIE_TOP_DRPDO12 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_2.PCIE_TOP_DBGVECA0 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_3.PCIE_TOP_DBGVECA4 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_4.PCIE_TOP_DBGVECA8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_0.PCIE_TOP_DBGVECA21 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_1.PCIE_TOP_CFGMGMTDO16 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_2.PCIE_TOP_MIMRXWDATA31 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_3.PCIE_TOP_DBGVECA13 always
PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_4.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_1.PCIE_TOP_DRPDO13 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_2.PCIE_TOP_DBGVECA1 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_3.PCIE_TOP_DBGVECA5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_4.PCIE_TOP_DBGVECA9 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_0.PCIE_TOP_DBGVECB10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_1.PCIE_TOP_DBGVECA16 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_2.PCIE_TOP_MIMRXWDATA33 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_3.PCIE_TOP_MIMRXWDATA5 always
PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_4.PCIE_TOP_DBGVECA11 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_0.PCIE_TOP_PLDBGVEC8 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_1.PCIE_TOP_DRPDO14 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_2.PCIE_TOP_DBGVECA2 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_3.PCIE_TOP_DBGVECA6 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_4.PCIE_TOP_DBGVECA10 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_1.PCIE_TOP_DBGVECA17 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_2.PCIE_TOP_DBGVECA15 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_3.PCIE_TOP_MIMRXWDATA7 always
PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_4.PCIE_TOP_CFGDEVCONTROL2LTREN always
PCIE_TOP.PCIE_TOP_CFGERRLOCKEDN.PCIE_IMUX17_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRNORECOVERYN.PCIE_IMUX18_R_2 always
PCIE_TOP.PCIE_TOP_CFGINTERRUPTN.PCIE_IMUX19_R_4 always
PCIE_TOP.PCIE_TOP_LL2SENDPMACK.PCIE_IMUX2_L_4 always
PCIE_TOP.PCIE_TOP_LL2SUSPENDNOW.PCIE_IMUX16_R_3 always
PCIE_TOP.PCIE_TOP_LL2TLPRCV.PCIE_IMUX2_L_3 always
PCIE_TOP.PCIE_TOP_PIPERX0CHANISALIGNED.PCIE_IMUX33_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0PHYSTATUS.PCIE_IMUX37_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0VALID.PCIE_IMUX36_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX4CHANISALIGNED.PCIE_IMUX33_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4PHYSTATUS.PCIE_IMUX37_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4VALID.PCIE_IMUX36_R_0 always
PCIE_TOP.PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK.PCIE_IMUX18_R_3 always
PCIE_TOP.PCIE_TOP_TL2PPMSUSPENDREQ.PCIE_IMUX17_R_3 always
PCIE_TOP.PCIE_TOP_TRNTDLLPSRCRDY.PCIE_IMUX1_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID0.PCIE_IMUX11_L_1 always
PCIE_TOP.PCIE_TOP_CFGDEVID1.PCIE_IMUX8_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID2.PCIE_IMUX9_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID3.PCIE_IMUX10_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID4.PCIE_IMUX11_L_2 always
PCIE_TOP.PCIE_TOP_CFGDEVID5.PCIE_IMUX8_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID6.PCIE_IMUX9_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID7.PCIE_IMUX10_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID8.PCIE_IMUX11_L_3 always
PCIE_TOP.PCIE_TOP_CFGDEVID9.PCIE_IMUX8_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID10.PCIE_IMUX9_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID11.PCIE_IMUX10_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID12.PCIE_IMUX11_L_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID13.PCIE_IMUX21_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID14.PCIE_IMUX22_R_4 always
PCIE_TOP.PCIE_TOP_CFGDEVID15.PCIE_IMUX23_R_4 always
PCIE_TOP.PCIE_TOP_CFGDSN57.PCIE_IMUX8_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN58.PCIE_IMUX9_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN59.PCIE_IMUX10_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN60.PCIE_IMUX11_L_0 always
PCIE_TOP.PCIE_TOP_CFGDSN61.PCIE_IMUX8_L_1 always
PCIE_TOP.PCIE_TOP_CFGDSN62.PCIE_IMUX9_L_1 always
PCIE_TOP.PCIE_TOP_CFGDSN63.PCIE_IMUX10_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG0.PCIE_IMUX19_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG1.PCIE_IMUX20_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG2.PCIE_IMUX20_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG3.PCIE_IMUX21_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG4.PCIE_IMUX22_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG5.PCIE_IMUX23_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG6.PCIE_IMUX13_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG7.PCIE_IMUX14_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG8.PCIE_IMUX15_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG9.PCIE_IMUX16_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG10.PCIE_IMUX24_R_3 always
PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG11.PCIE_IMUX21_R_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER26.PCIE_IMUX4_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER27.PCIE_IMUX5_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER28.PCIE_IMUX6_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER29.PCIE_IMUX7_L_0 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER30.PCIE_IMUX4_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER31.PCIE_IMUX5_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER32.PCIE_IMUX6_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER33.PCIE_IMUX7_L_1 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER34.PCIE_IMUX4_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER35.PCIE_IMUX5_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER36.PCIE_IMUX6_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER37.PCIE_IMUX7_L_2 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER38.PCIE_IMUX4_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER39.PCIE_IMUX5_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER40.PCIE_IMUX6_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER41.PCIE_IMUX7_L_3 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER42.PCIE_IMUX4_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER43.PCIE_IMUX5_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER44.PCIE_IMUX6_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER45.PCIE_IMUX7_L_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER46.PCIE_IMUX17_R_4 always
PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER47.PCIE_IMUX18_R_4 always
PCIE_TOP.PCIE_TOP_CFGINTERRUPTDI0.PCIE_IMUX20_R_4 always
PCIE_TOP.PCIE_TOP_CFGVENDID0.PCIE_IMUX24_R_4 always
PCIE_TOP.PCIE_TOP_DBGMODE0.PCIE_IMUX25_R_4 always
PCIE_TOP.PCIE_TOP_DRPADDR7.PCIE_IMUX12_L_0 always
PCIE_TOP.PCIE_TOP_DRPADDR8.PCIE_IMUX13_L_0 always
PCIE_TOP.PCIE_TOP_DRPDI0.PCIE_IMUX12_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI1.PCIE_IMUX13_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI2.PCIE_IMUX14_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI3.PCIE_IMUX15_L_1 always
PCIE_TOP.PCIE_TOP_DRPDI4.PCIE_IMUX12_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI5.PCIE_IMUX13_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI6.PCIE_IMUX14_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI7.PCIE_IMUX15_L_2 always
PCIE_TOP.PCIE_TOP_DRPDI8.PCIE_IMUX12_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI9.PCIE_IMUX13_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI10.PCIE_IMUX14_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI11.PCIE_IMUX15_L_3 always
PCIE_TOP.PCIE_TOP_DRPDI12.PCIE_IMUX12_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI13.PCIE_IMUX13_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI14.PCIE_IMUX14_L_4 always
PCIE_TOP.PCIE_TOP_DRPDI15.PCIE_IMUX15_L_4 always
PCIE_TOP.PCIE_TOP_LL2SENDASREQL1.PCIE_IMUX1_L_4 always
PCIE_TOP.PCIE_TOP_LL2SENDENTERL1.PCIE_IMUX3_L_3 always
PCIE_TOP.PCIE_TOP_LL2SENDENTERL23.PCIE_IMUX0_L_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA20.PCIE_IMUX0_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA21.PCIE_IMUX1_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA22.PCIE_IMUX2_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA23.PCIE_IMUX3_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA24.PCIE_IMUX0_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA25.PCIE_IMUX1_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA26.PCIE_IMUX2_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA27.PCIE_IMUX3_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA28.PCIE_IMUX0_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA29.PCIE_IMUX1_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA30.PCIE_IMUX2_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA31.PCIE_IMUX3_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA32.PCIE_IMUX0_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA33.PCIE_IMUX1_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA34.PCIE_IMUX2_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA35.PCIE_IMUX3_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA36.PCIE_IMUX0_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA37.PCIE_IMUX1_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA38.PCIE_IMUX2_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA39.PCIE_IMUX3_R_4 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA40.PCIE_IMUX4_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA41.PCIE_IMUX5_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA42.PCIE_IMUX6_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA43.PCIE_IMUX7_R_3 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA44.PCIE_IMUX4_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA45.PCIE_IMUX5_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA46.PCIE_IMUX6_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA47.PCIE_IMUX7_R_2 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA48.PCIE_IMUX4_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA49.PCIE_IMUX5_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA50.PCIE_IMUX6_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA51.PCIE_IMUX7_R_1 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA52.PCIE_IMUX4_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA53.PCIE_IMUX5_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA54.PCIE_IMUX6_R_0 always
PCIE_TOP.PCIE_TOP_MIMRXRDATA55.PCIE_IMUX7_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX0CHARISK0.PCIE_IMUX16_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA0.PCIE_IMUX37_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA1.PCIE_IMUX36_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA2.PCIE_IMUX33_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA3.PCIE_IMUX32_L_1 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA4.PCIE_IMUX39_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA5.PCIE_IMUX38_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA6.PCIE_IMUX35_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX0DATA7.PCIE_IMUX34_L_0 always
PCIE_TOP.PCIE_TOP_PIPERX4CHARISK0.PCIE_IMUX16_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA0.PCIE_IMUX37_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA1.PCIE_IMUX36_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA2.PCIE_IMUX33_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA3.PCIE_IMUX32_R_1 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA4.PCIE_IMUX39_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA5.PCIE_IMUX38_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA6.PCIE_IMUX35_R_0 always
PCIE_TOP.PCIE_TOP_PIPERX4DATA7.PCIE_IMUX34_R_0 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE0.PCIE_IMUX3_L_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE1.PCIE_IMUX8_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE2.PCIE_IMUX9_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE3.PCIE_IMUX10_R_4 always
PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE4.PCIE_IMUX11_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD8.PCIE_IMUX8_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD9.PCIE_IMUX9_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD10.PCIE_IMUX10_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD11.PCIE_IMUX11_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD12.PCIE_IMUX8_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD13.PCIE_IMUX9_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD14.PCIE_IMUX10_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD15.PCIE_IMUX11_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD16.PCIE_IMUX8_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD17.PCIE_IMUX9_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD18.PCIE_IMUX10_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD19.PCIE_IMUX11_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD20.PCIE_IMUX8_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD21.PCIE_IMUX9_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD22.PCIE_IMUX10_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD23.PCIE_IMUX11_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD24.PCIE_IMUX4_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD25.PCIE_IMUX5_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD26.PCIE_IMUX6_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD27.PCIE_IMUX7_R_4 always
PCIE_TOP.PCIE_TOP_TRNTD28.PCIE_IMUX12_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD29.PCIE_IMUX13_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD30.PCIE_IMUX14_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD31.PCIE_IMUX15_R_3 always
PCIE_TOP.PCIE_TOP_TRNTD32.PCIE_IMUX12_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD33.PCIE_IMUX13_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD34.PCIE_IMUX14_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD35.PCIE_IMUX15_R_2 always
PCIE_TOP.PCIE_TOP_TRNTD36.PCIE_IMUX12_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD37.PCIE_IMUX13_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD38.PCIE_IMUX14_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD39.PCIE_IMUX15_R_1 always
PCIE_TOP.PCIE_TOP_TRNTD40.PCIE_IMUX12_R_0 always
PCIE_TOP.PCIE_TOP_TRNTD41.PCIE_IMUX13_R_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA19.PCIE_IMUX0_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA20.PCIE_IMUX1_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA21.PCIE_IMUX2_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA22.PCIE_IMUX3_L_0 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA23.PCIE_IMUX0_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA24.PCIE_IMUX1_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA25.PCIE_IMUX2_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA26.PCIE_IMUX3_L_1 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA27.PCIE_IMUX0_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA28.PCIE_IMUX1_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA29.PCIE_IMUX2_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA30.PCIE_IMUX3_L_2 always
PCIE_TOP.PCIE_TOP_TRNTDLLPDATA31.PCIE_IMUX0_L_3 always

756
kintex7/segbits_cmt_top_l_lower_b.db
View File

@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_L_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94
CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389
CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388
CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387
CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386
CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385
CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384
CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395
CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394
CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393
CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN 28_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] 29_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] 28_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] 29_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] 28_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] 29_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] 28_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] 29_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] 28_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] 29_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] 28_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST 29_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808

756
kintex7/segbits_cmt_top_l_lower_b.origin_info.db
View File

@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_L_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

686
kintex7/segbits_cmt_top_l_upper_t.db
View File

@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] 28_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] 29_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] 28_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] 29_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] 28_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] 29_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] 28_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] 29_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] 28_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] 29_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST 28_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247

686
kintex7/segbits_cmt_top_l_upper_t.origin_info.db
View File

@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

756
kintex7/segbits_cmt_top_r_lower_b.db
View File

@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_R_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94
CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389
CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388
CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387
CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386
CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385
CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384
CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395
CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394
CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393
CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN 28_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] 29_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] 28_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] 29_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] 28_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] 29_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] 28_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] 29_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] 28_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] 29_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] 28_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST 29_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808

756
kintex7/segbits_cmt_top_r_lower_b.origin_info.db
View File

@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_R_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

686
kintex7/segbits_cmt_top_r_upper_t.db
View File

@ -21,346 +21,346 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] 28_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] 29_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] 28_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] 29_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] 28_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] 29_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] 28_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] 29_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] 28_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] 29_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST 28_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247

686
kintex7/segbits_cmt_top_r_upper_t.origin_info.db
View File

@ -21,346 +21,346 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

12
kintex7/segbits_int_l.origin_info.db
View File

@ -301,7 +301,7 @@ INT_L.FAN_ALT0.FAN_BOUNCE4 origin:050-pip-seed !22_00 20_00 23_00 24_00 25_00
INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@ -393,7 +393,7 @@ INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@ -1917,7 +1917,7 @@ INT_L.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@ -2491,7 +2491,7 @@ INT_L.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_L.NR1BEG0.LOGIC_OUTS_L0 origin:050-pip-seed 11_07 14_07
@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03
INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@ -3623,7 +3623,7 @@ INT_L.WW4BEG3.LOGIC_OUTS_L21 origin:050-pip-seed 06_48 07_49
INT_L.WW4BEG3.LV_L18 origin:056-pip-rem 05_48 07_49
INT_L.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
INT_L.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
INT_L.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_L.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
INT_L.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_L.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_L.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49

10
kintex7/segbits_int_r.origin_info.db
View File

@ -329,7 +329,7 @@ INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@ -685,7 +685,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -2273,7 +2273,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@ -3344,7 +3344,7 @@ INT_R.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61

4
kintex7/segbits_liob33.db
View File

@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07
LIOB33.IOB_Y1.INTERMDISABLE.I 38_38
LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
LIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32
LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41
LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21
LIOB33.OUT_DIFF 39_59 39_61

4
kintex7/segbits_liob33.origin_info.db
View File

@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35
LIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33
@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32
LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63
@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63
LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40
LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17
LIOB33.OUT_DIFF origin:030-iob 39_59 39_61

4
kintex7/segbits_riob33.db
View File

@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
RIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32
RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41
RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41
RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21
RIOB33.OUT_DIFF 39_59 39_61

4
kintex7/segbits_riob33.origin_info.db
View File

@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35
RIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33
@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32
RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63
@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63
RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40
RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41
RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17
RIOB33.OUT_DIFF origin:030-iob 39_59 39_61

756
zynq7/segbits_cmt_top_l_lower_b.db
View File

@ -23,381 +23,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_L_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94
CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389
CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388
CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387
CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386
CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385
CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384
CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395
CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394
CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393
CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN 28_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018
CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] 29_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] 28_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] 29_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] 28_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] 29_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] 28_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] 29_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] 28_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] 29_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] 28_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST 29_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808

756
zynq7/segbits_cmt_top_l_lower_b.origin_info.db
View File

@ -23,381 +23,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_L_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979
CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809
CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703
CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

686
zynq7/segbits_cmt_top_l_upper_t.db
View File

@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] 28_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] 29_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] 28_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] 29_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] 28_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] 29_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] 28_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] 29_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] 28_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] 29_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST 28_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247

686
zynq7/segbits_cmt_top_l_upper_t.origin_info.db
View File

@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246
CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

Some files were not shown because too many files have changed in this diff Show More