Fischer Moseley
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df2dbf4ec6
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update makefile to reflect new paths
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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f5caca613a
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simplify uart/ether APIs, improve lazy loading
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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ab58af0bfc
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add video_sprite_ether example
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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cef5e9318b
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flip i and j, and see the light
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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15aa5f469f
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add ethernet_tx_tb
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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2c461ed08d
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add working ethernet_tx testbench
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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9c5ea31d14
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enforce consistent naming of lut_mem module
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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54b97fd120
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add working ethernet verilog autogeneration woot woot :)
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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1d2171faad
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update pyproject.toml to get verilog files from all subdirs
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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2013e74f0f
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update help message with consistent version number
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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b3d402c1f5
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refactor python/hdl structure
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7f9012b542
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tidy examples
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7cd8a2cfa5
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tidy up mac stack
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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6210e3cc39
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add working python api for ethernet tx/rx
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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8e139bba3a
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add working l2 mac in hardware - need to fix ethertype to get scapy to play nice
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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c507f795f1
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add ethernet_tx/rx, semi-working in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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0bb3f9c74a
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clean up mac_tx, working in simulation
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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64a582c786
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add working mac tx
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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dab6e3f272
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add working mac testbench - also found a problem in VCD logging
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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cfddb67652
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add warnings for unrecognized parameters in configuration
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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28f40f2b7b
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add working l2 send in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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a2d14116de
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add trigger_mode register to logic analyzer core
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2023-04-18 23:14:41 -04:00 |
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Fischer Moseley
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6869ae631e
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docs hotfix during beta testing
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2023-04-18 17:28:01 -04:00 |
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Fischer Moseley
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0268572779
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update tutorial_1
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2023-04-18 13:55:40 -04:00 |
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Fischer Moseley
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af5d3a9b4b
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initial commit tutorial 2
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2023-04-18 12:42:39 -04:00 |
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Fischer Moseley
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c1894dac73
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add signal to vcd export to signal when triggered
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2023-04-18 01:22:01 -04:00 |
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Fischer Moseley
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357b7eed94
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refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
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2023-04-18 01:06:39 -04:00 |
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Fischer Moseley
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5172cab555
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update todo
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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870d299c74
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add docs and add trigger config for logic analyzer
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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3400ea63c8
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squash data duplication bug
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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320638508d
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unconfused myself, add manta as dependency to more parts of CI
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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07624d83ee
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move back to iverilog 13 compatability
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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ca814df63e
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forgot a semicolon in the makefile
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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925fd915be
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update simulation syntax for iverilog 11 compat
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1aa067b435
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update logic_analyzer_tb to use only generated HDL
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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102bdee410
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update makefile to match positional args from PATH'd binaries
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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f6f9096895
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add batch read/write UART for speedo mode
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9cc2357ea4
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update command line positional args
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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7c1e4fc2c0
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add logic analyzer playback module auto-generation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9d8836bda3
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add prototype simulation replay
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1c74d4a714
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add running the logic analyzer to the python API
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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7bec8b15c8
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fix bug that removed stop requests
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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a2ad90a66a
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modify sim and generator, seems to work in simulation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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518f49cc29
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rewrite logic analyzer fsm
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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bdca8e01e7
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add boilerplate for new modules - just gotta rewrite the fsm
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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4d2c3d08e6
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fix line ending bug on windows
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2023-04-13 19:48:47 -04:00 |
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Fischer Moseley
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276069bd79
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abort windows CI due to lab-bc being weird on windows server
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2023-04-13 18:52:58 -04:00 |
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Fischer Moseley
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282262c0fc
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update windows CI builds again
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2023-04-13 18:48:13 -04:00 |
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Fischer Moseley
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2d647dce20
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update windows CI builds again
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2023-04-13 18:45:11 -04:00 |
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Fischer Moseley
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45da8ef4aa
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update windows CI builds again
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2023-04-13 18:43:16 -04:00 |