c85cc4d357
tweak lut_ram example
2023-03-23 18:24:29 -04:00
edd50168e2
refactor IO core read/write to be less ugly
2023-03-17 20:12:57 -04:00
d46e833529
can now successfully autogenerate and build io cores
2023-03-16 12:13:46 -04:00
2c51aa9a9a
paritally imnplement io core autogeneration
2023-03-16 09:38:17 -04:00
4540aebf6d
add some fixes for macos serial prots
2023-03-14 16:24:56 -04:00
aa2ba43e8f
rename lut mem to lut ram, add to manta generator
2023-03-14 16:24:56 -04:00
8630da53d8
hack manta source files together
2023-03-14 16:24:56 -04:00
f5f7f91bdc
fix LogicAnalyzerCore instantiation from file
2023-03-14 16:24:56 -04:00
334aa8c005
refactor __init__.py to be object-oriented
2023-03-14 16:24:56 -04:00
e022696b31
add working example for macOS bug
2023-03-14 16:24:56 -04:00
70e2bd10e7
rename, slightly patch bridge_tx
2023-03-14 16:24:56 -04:00
3124430064
tidy up a little, convert things to verilog
2023-03-14 16:24:56 -04:00
3ff4298e24
works (kinda) on hardware
2023-03-14 16:24:56 -04:00
3728a5263d
add icestick builds / iCE40 to CI ( #1 )
...
* initial commit
* fix yaml file
* add yosys deps to CI
* fix indentation in ice40 CI builds
* update ice40 CI
* try using oss cad suite instead of compiling from source
* fix pathing directory
* ensure jobs are sequential
* ensure we're in the same shell
* move source files to same action
* update icestick project structure to match the a7's
* update build script for ice40 to match updated proj structure
* update CI to match previous
* update CI path
* update build script naming
---------
Co-authored-by: fischerm <fischerm@EECS-DIGITAL-55.MIT.EDU>
2023-02-23 18:52:22 -05:00
218b2ffd20
initial commit for sd card example
2023-02-15 11:48:58 -05:00
02fc53cbf7
package for PyPI
2023-02-14 17:14:39 -05:00
ce6a6590c7
fix one last bit of naming
2023-02-09 15:33:19 -05:00
ae89e9a778
rename files, remove reference to ILA
2023-02-09 15:30:25 -05:00
5f3dc9dd5b
fix width issue
2023-02-09 15:10:09 -05:00
566a3624d8
remove legacy code, now feature complete with new scripts
2023-02-05 15:49:23 -05:00
e48f60e03a
make downlink core export as just one verilog file
2023-02-05 10:22:54 -05:00
af3df749b5
merge + refactor
2023-02-04 18:53:52 -05:00
d2bcbe2418
import from openILA
2023-02-04 12:43:00 -05:00
Fischer Moseley
Fischer Moseley