make downlink core export as just one verilog file
This commit is contained in:
Fischer Moseley
parent
f5c2af06d0
commit
e48f60e03a
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@ -1,2 +1,4 @@
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*.log
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*.bit
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*.vcd
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*.out
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@ -0,0 +1,612 @@
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`default_nettype none
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`timescale 1ns / 1ps
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module fifo (
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input wire clk,
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input wire rst,
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input wire [WIDTH - 1:0] data_in,
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input wire input_ready,
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input wire request_output,
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output logic [WIDTH - 1:0] data_out,
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output logic output_valid,
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output logic [AW:0] size,
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output logic empty,
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output logic full
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);
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parameter WIDTH = 8;
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parameter DEPTH = 4096;
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localparam AW = $clog2(DEPTH);
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logic [AW:0] write_pointer;
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logic [AW:0] read_pointer;
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logic empty_int;
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assign empty_int = (write_pointer[AW] == read_pointer[AW]);
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logic full_or_empty;
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assign full_or_empty = (write_pointer[AW-1:0] == read_pointer[AW-1:0]);
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assign full = full_or_empty & !empty_int;
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assign empty = full_or_empty & empty_int;
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assign size = write_pointer - read_pointer;
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logic output_valid_pip_0;
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logic output_valid_pip_1;
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always @(posedge clk) begin
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if (input_ready && ~full)
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write_pointer <= write_pointer + 1'd1;
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if (request_output && ~empty)
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read_pointer <= read_pointer + 1'd1;
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output_valid_pip_0 <= request_output;
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output_valid_pip_1 <= output_valid_pip_0;
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output_valid <= output_valid_pip_1;
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if (rst) begin
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read_pointer <= 0;
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write_pointer <= 0;
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end
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end
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xilinx_true_dual_port_read_first_2_clock_ram #(
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.RAM_WIDTH(WIDTH),
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.RAM_DEPTH(DEPTH),
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.RAM_PERFORMANCE("HIGH_PERFORMANCE")
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) buffer (
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// write port
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.clka(clk),
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.rsta(rst),
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.ena(1),
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.addra(write_pointer),
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.dina(data_in),
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.wea(input_ready),
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.regcea(1),
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.douta(),
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// read port
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.clkb(clk),
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.rstb(rst),
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.enb(1),
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.addrb(read_pointer),
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.dinb(),
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.web(0),
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.regceb(1),
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.doutb(data_out));
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endmodule
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`default_nettype wire
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`default_nettype none
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`timescale 1ns / 1ps
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/*
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This ILA was autogenerated on 05/02/2023 10:10:20 by fischerm
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If this breaks or if you've got dank formal verification memes,
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please contact fischerm [at] mit.edu.
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*/
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`define IDLE 0
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`define ARM 1
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`define FILL 2
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`define DOWNLINK 3
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`define ARM_BYTE 8'b00110000
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module ila (
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input wire clk,
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input wire rst,
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/* Begin autogenerated probe definitions */
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input wire larry,
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input wire curly,
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input wire moe,
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input wire [2:0] shemp,
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/* End autogenerated probe definitions */
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input wire rxd,
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output logic txd);
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/* Begin autogenerated parameters */
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localparam SAMPLE_WIDTH = 6;
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localparam SAMPLE_DEPTH = 4096;
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localparam DATA_WIDTH = 8;
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localparam BAUDRATE = 115200;
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localparam CLK_FREQ_HZ = 100000000;
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logic trigger;
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assign trigger = (larry && curly && ~moe);
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logic [SAMPLE_WIDTH - 1 : 0] concat;
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assign concat = {larry, curly, moe, shemp};;
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/* End autogenerated parameters */
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// FIFO
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logic [7:0] fifo_data_in;
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logic fifo_input_ready;
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logic fifo_request_output;
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logic [7:0] fifo_data_out;
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logic fifo_output_valid;
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logic [11:0] fifo_size;
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logic fifo_empty;
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logic fifo_full;
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fifo #(
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.WIDTH(SAMPLE_WIDTH),
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.DEPTH(SAMPLE_DEPTH)
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) fifo (
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.clk(clk),
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.rst(rst),
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.data_in(fifo_data_in),
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.input_ready(fifo_input_ready),
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.request_output(fifo_request_output),
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.data_out(fifo_data_out),
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.output_valid(fifo_output_valid),
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.size(fifo_size),
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.empty(fifo_empty),
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.full(fifo_full));
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// Serial interface
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logic tx_start;
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logic [7:0] tx_data;
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logic tx_busy;
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logic [7:0] rx_data;
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logic rx_ready;
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logic rx_busy;
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uart_tx #(
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.DATA_WIDTH(DATA_WIDTH),
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.CLK_FREQ_HZ(CLK_FREQ_HZ),
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.BAUDRATE(BAUDRATE))
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tx (
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.clk(clk),
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.rst(rst),
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.start(tx_start),
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.data(tx_data),
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.busy(tx_busy),
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.txd(txd));
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uart_rx #(
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.DATA_WIDTH(DATA_WIDTH),
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.CLK_FREQ_HZ(CLK_FREQ_HZ),
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.BAUDRATE(BAUDRATE))
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rx (
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.clk(clk),
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.rst(rst),
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.rxd(rxd),
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.data(rx_data),
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.ready(rx_ready),
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.busy(rx_busy));
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/* State Machine */
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/*
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IDLE:
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- literally nothing is happening. the FIFO isn't being written to or read from. it should be empty.
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- an arm command over serial is what brings us into the ARM state
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ARM:
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- popping things onto FIFO. if the fifo is halfway full, we pop them off too.
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- meeting the trigger condition is what moves us into the filing state
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FILL:
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- popping things onto FIFO, until it's full. once it is full, we move into the downlinking state
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DOWNLINK:
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- popping thing off of the FIFO until it's empty. once it's empty, we move back into the IDLE state
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*/
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/* Downlink State Machine Controller */
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/*
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- ila enters the downlink state
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- set fifo_output_request high for a clock cycle
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- when fifo_output_valid goes high, send fifo_data_out across the line
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- do nothing until tx_busy goes low
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- goto step 2
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*/
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logic [1:0] state;
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logic [2:0] downlink_fsm_state;
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always_ff @(posedge clk) begin
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if(rst) begin
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state <= `IDLE;
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downlink_fsm_state <= 0;
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tx_data <= 0;
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tx_start <= 0;
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end
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else begin
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case (state)
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`IDLE : begin
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fifo_input_ready <= 0;
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fifo_request_output <= 0;
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if (rx_ready && rx_data == `ARM_BYTE) state <= `ARM;
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end
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`ARM : begin
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// place samples into FIFO
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fifo_input_ready <= 1;
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fifo_data_in <= concat;
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// remove old samples if we're more than halfway full
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fifo_request_output <= (fifo_size >= SAMPLE_DEPTH / 2);
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if(trigger) state <= `FILL;
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end
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`FILL : begin
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// place samples into FIFO
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fifo_input_ready <= 1;
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fifo_data_in <= concat;
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// don't pop anything out the FIFO
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fifo_request_output <= 0;
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if(fifo_size == SAMPLE_DEPTH - 1) state <= `DOWNLINK;
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end
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`DOWNLINK : begin
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// place no samples into FIFO
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fifo_input_ready <= 0;
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case (downlink_fsm_state)
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0 : begin
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if (~fifo_empty) begin
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fifo_request_output <= 1;
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downlink_fsm_state <= 1;
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end
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else state <= `IDLE;
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end
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1 : begin
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fifo_request_output <= 0;
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if (fifo_output_valid) begin
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tx_data <= fifo_data_out;
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tx_start <= 1;
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downlink_fsm_state <= 2;
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end
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end
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2 : begin
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tx_start <= 0;
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if (~tx_busy && ~tx_start) downlink_fsm_state <= 0;
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end
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endcase
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end
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endcase
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end
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end
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endmodule
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`default_nettype wire`default_nettype none
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`timescale 1ns / 1ps
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module uart_tx(
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input wire clk,
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input wire rst,
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input wire [DATA_WIDTH-1:0] data,
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input wire start,
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output logic busy,
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output logic txd
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);
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// Just going to stick to 8N1 for now, we'll come back and
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// parameterize this later.
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parameter DATA_WIDTH = 8;
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parameter CLK_FREQ_HZ = 100_000_000;
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parameter BAUDRATE = 115200;
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localparam PRESCALER = CLK_FREQ_HZ / BAUDRATE;
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logic [$clog2(PRESCALER) - 1:0] baud_counter;
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logic [$clog2(DATA_WIDTH + 2):0] bit_index;
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logic [DATA_WIDTH - 1:0] data_buf;
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// make secondary logic for baudrate
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always_ff @(posedge clk) begin
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if(rst) baud_counter <= 0;
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else begin
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baud_counter <= (baud_counter == PRESCALER - 1) ? 0 : baud_counter + 1;
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end
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end
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always_ff @(posedge clk) begin
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// reset logic
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if(rst) begin
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bit_index <= 0;
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busy <= 0;
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txd <= 1; // idle high
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end
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// enter transmitting state logic
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// don't allow new requests to interrupt current
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// transfers
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if(start && ~busy) begin
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busy <= 1;
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data_buf <= data;
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end
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// transmitting state logic
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else if(baud_counter == 0 && busy) begin
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if (bit_index == 0) begin
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txd <= 0;
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bit_index <= bit_index + 1;
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end
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else if ((bit_index < DATA_WIDTH + 1) && (bit_index > 0)) begin
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txd <= data_buf[bit_index - 1];
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bit_index <= bit_index + 1;
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end
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else if (bit_index == DATA_WIDTH + 1) begin
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txd <= 1;
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bit_index <= bit_index + 1;
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end
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else if (bit_index >= DATA_WIDTH + 1) begin
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busy <= 0;
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bit_index <= 0;
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end
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end
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end
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endmodule
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`default_nettype wire
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// Xilinx True Dual Port RAM, Read First, Dual Clock
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// This code implements a parameterizable true dual port memory (both ports can read and write).
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// The behavior of this RAM is when data is written, the prior memory contents at the write
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// address are presented on the output port. If the output data is
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// not needed during writes or the last read value is desired to be retained,
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// it is suggested to use a no change RAM as it is more power efficient.
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// If a reset or enable is not necessary, it may be tied off or removed from the code.
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module xilinx_true_dual_port_read_first_2_clock_ram #(
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parameter RAM_WIDTH = 18, // Specify RAM data width
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parameter RAM_DEPTH = 1024, // Specify RAM depth (number of entries)
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parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
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parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
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) (
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input [clogb2(RAM_DEPTH-1)-1:0] addra, // Port A address bus, width determined from RAM_DEPTH
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input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Port B address bus, width determined from RAM_DEPTH
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input [RAM_WIDTH-1:0] dina, // Port A RAM input data
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input [RAM_WIDTH-1:0] dinb, // Port B RAM input data
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input clka, // Port A clock
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input clkb, // Port B clock
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input wea, // Port A write enable
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input web, // Port B write enable
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input ena, // Port A RAM Enable, for additional power savings, disable port when not in use
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input enb, // Port B RAM Enable, for additional power savings, disable port when not in use
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input rsta, // Port A output reset (does not affect memory contents)
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input rstb, // Port B output reset (does not affect memory contents)
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input regcea, // Port A output register enable
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input regceb, // Port B output register enable
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output [RAM_WIDTH-1:0] douta, // Port A RAM output data
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output [RAM_WIDTH-1:0] doutb // Port B RAM output data
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);
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reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
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reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
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reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
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//this loop below allows for rendering with iverilog simulations!
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/*
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integer idx;
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for(idx = 0; idx < RAM_DEPTH; idx = idx+1) begin: cats
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wire [RAM_WIDTH-1:0] tmp;
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assign tmp = BRAM[idx];
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end
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*/
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// The following code either initializes the memory values to a specified file or to all zeros to match hardware
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generate
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if (INIT_FILE != "") begin: use_init_file
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initial
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$readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
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end else begin: init_bram_to_zero
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integer ram_index;
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initial
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for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
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BRAM[ram_index] = {RAM_WIDTH{1'b0}};
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end
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endgenerate
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integer idx;
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// initial begin
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// for (idx = 0; idx < RAM_DEPTH; idx = idx + 1) begin
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// $dumpvars(0, BRAM[idx]);
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// end
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// end
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always @(posedge clka)
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if (ena) begin
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if (wea)
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BRAM[addra] <= dina;
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ram_data_a <= BRAM[addra];
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end
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always @(posedge clkb)
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if (enb) begin
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if (web)
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BRAM[addrb] <= dinb;
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ram_data_b <= BRAM[addrb];
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end
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// The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register)
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generate
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if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register
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// The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
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assign douta = ram_data_a;
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assign doutb = ram_data_b;
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end else begin: output_register
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// The following is a 2 clock cycle read latency with improve clock-to-out timing
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reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}};
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reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}};
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always @(posedge clka)
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if (rsta)
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douta_reg <= {RAM_WIDTH{1'b0}};
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else if (regcea)
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douta_reg <= ram_data_a;
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always @(posedge clkb)
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if (rstb)
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doutb_reg <= {RAM_WIDTH{1'b0}};
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else if (regceb)
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doutb_reg <= ram_data_b;
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assign douta = douta_reg;
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assign doutb = doutb_reg;
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end
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endgenerate
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// The following function calculates the address width based on specified RAM depth
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function integer clogb2;
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input integer depth;
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for (clogb2=0; depth>0; clogb2=clogb2+1)
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depth = depth >> 1;
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endfunction
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endmodule
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||||
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// The following is an instantiation template for xilinx_true_dual_port_read_first_2_clock_ram
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||||
/*
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// Xilinx True Dual Port RAM, Read First, Dual Clock
|
||||
xilinx_true_dual_port_read_first_2_clock_ram #(
|
||||
.RAM_WIDTH(18), // Specify RAM data width
|
||||
.RAM_DEPTH(1024), // Specify RAM depth (number of entries)
|
||||
.RAM_PERFORMANCE("HIGH_PERFORMANCE"), // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
|
||||
.INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not)
|
||||
) your_instance_name (
|
||||
.addra(addra), // Port A address bus, width determined from RAM_DEPTH
|
||||
.addrb(addrb), // Port B address bus, width determined from RAM_DEPTH
|
||||
.dina(dina), // Port A RAM input data, width determined from RAM_WIDTH
|
||||
.dinb(dinb), // Port B RAM input data, width determined from RAM_WIDTH
|
||||
.clka(clka), // Port A clock
|
||||
.clkb(clkb), // Port B clock
|
||||
.wea(wea), // Port A write enable
|
||||
.web(web), // Port B write enable
|
||||
.ena(ena), // Port A RAM Enable, for additional power savings, disable port when not in use
|
||||
.enb(enb), // Port B RAM Enable, for additional power savings, disable port when not in use
|
||||
.rsta(rsta), // Port A output reset (does not affect memory contents)
|
||||
.rstb(rstb), // Port B output reset (does not affect memory contents)
|
||||
.regcea(regcea), // Port A output register enable
|
||||
.regceb(regceb), // Port B output register enable
|
||||
.douta(douta), // Port A RAM output data, width determined from RAM_WIDTH
|
||||
.doutb(doutb) // Port B RAM output data, width determined from RAM_WIDTH
|
||||
);
|
||||
*/
|
||||
|
||||
|
||||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module uart_rx(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire rxd,
|
||||
|
||||
output logic [DATA_WIDTH - 1:0] data,
|
||||
output logic ready,
|
||||
output logic busy
|
||||
);
|
||||
|
||||
// Just going to stick to 8N1 for now, we'll come back and
|
||||
// parameterize this later.
|
||||
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter CLK_FREQ_HZ = 100_000_000;
|
||||
parameter BAUDRATE = 115200;
|
||||
|
||||
localparam PRESCALER = CLK_FREQ_HZ / BAUDRATE;
|
||||
|
||||
logic [$clog2(PRESCALER) - 1:0] baud_counter;
|
||||
logic [$clog2(DATA_WIDTH + 2):0] bit_index;
|
||||
logic [DATA_WIDTH + 2 : 0] data_buf;
|
||||
|
||||
logic prev_rxd;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
prev_rxd <= rxd;
|
||||
ready <= 0;
|
||||
baud_counter <= (baud_counter == PRESCALER - 1) ? 0 : baud_counter + 1;
|
||||
|
||||
// reset logic
|
||||
if(rst) begin
|
||||
bit_index <= 0;
|
||||
data <= 0;
|
||||
busy <= 0;
|
||||
baud_counter <= 0;
|
||||
end
|
||||
|
||||
// start receiving if we see a falling edge, and not already busy
|
||||
else if (prev_rxd && ~rxd && ~busy) begin
|
||||
busy <= 1;
|
||||
data_buf <= 0;
|
||||
baud_counter <= 0;
|
||||
end
|
||||
|
||||
// if we're actually receiving
|
||||
else if (busy) begin
|
||||
if (baud_counter == PRESCALER / 2) begin
|
||||
data_buf[bit_index] <= rxd;
|
||||
bit_index <= bit_index + 1;
|
||||
|
||||
if (bit_index == DATA_WIDTH + 1) begin
|
||||
busy <= 0;
|
||||
bit_index <= 0;
|
||||
|
||||
|
||||
if (rxd && ~data_buf[0]) begin
|
||||
data <= data_buf[DATA_WIDTH : 1];
|
||||
ready <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
|
@ -1,227 +0,0 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
This ILA was autogenerated on 03/02/2023 23:13:51 by fischerm
|
||||
|
||||
If this breaks or if you've got dank formal verification memes,
|
||||
please contact fischerm [at] mit.edu.
|
||||
*/
|
||||
|
||||
`define IDLE 0
|
||||
`define ARM 1
|
||||
`define FILL 2
|
||||
`define DOWNLINK 3
|
||||
|
||||
`define ARM_BYTE 8'b00110000
|
||||
|
||||
module ila (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/* Begin autogenerated probe definitions */
|
||||
input wire larry,
|
||||
input wire curly,
|
||||
input wire moe,
|
||||
input wire [2:0] shemp,
|
||||
/* End autogenerated probe definitions */
|
||||
|
||||
input wire rxd,
|
||||
output logic txd);
|
||||
|
||||
/* Begin autogenerated parameters */
|
||||
localparam SAMPLE_WIDTH = 6;
|
||||
localparam SAMPLE_DEPTH = 4096;
|
||||
|
||||
localparam DATA_WIDTH = 8;
|
||||
localparam BAUDRATE = 115200;
|
||||
localparam CLK_FREQ_HZ = 100000000;
|
||||
|
||||
logic trigger;
|
||||
assign trigger = (larry && curly && ~moe);
|
||||
|
||||
logic [SAMPLE_WIDTH - 1 : 0] concat;
|
||||
assign concat = {larry, curly, moe, shemp};;
|
||||
/* End autogenerated parameters */
|
||||
|
||||
|
||||
// FIFO
|
||||
logic [7:0] fifo_data_in;
|
||||
logic fifo_input_ready;
|
||||
|
||||
logic fifo_request_output;
|
||||
logic [7:0] fifo_data_out;
|
||||
logic fifo_output_valid;
|
||||
|
||||
logic [11:0] fifo_size;
|
||||
logic fifo_empty;
|
||||
logic fifo_full;
|
||||
|
||||
fifo #(
|
||||
.WIDTH(SAMPLE_WIDTH),
|
||||
.DEPTH(SAMPLE_DEPTH)
|
||||
) fifo (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
.data_in(fifo_data_in),
|
||||
.input_ready(fifo_input_ready),
|
||||
|
||||
.request_output(fifo_request_output),
|
||||
.data_out(fifo_data_out),
|
||||
.output_valid(fifo_output_valid),
|
||||
|
||||
.size(fifo_size),
|
||||
.empty(fifo_empty),
|
||||
.full(fifo_full));
|
||||
|
||||
// Serial interface
|
||||
logic tx_start;
|
||||
logic [7:0] tx_data;
|
||||
logic tx_busy;
|
||||
|
||||
logic [7:0] rx_data;
|
||||
logic rx_ready;
|
||||
logic rx_busy;
|
||||
|
||||
|
||||
uart_tx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CLK_FREQ_HZ(CLK_FREQ_HZ),
|
||||
.BAUDRATE(BAUDRATE))
|
||||
tx (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.start(tx_start),
|
||||
.data(tx_data),
|
||||
|
||||
.busy(tx_busy),
|
||||
.txd(txd));
|
||||
|
||||
uart_rx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CLK_FREQ_HZ(CLK_FREQ_HZ),
|
||||
.BAUDRATE(BAUDRATE))
|
||||
rx (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.rxd(rxd),
|
||||
|
||||
.data(rx_data),
|
||||
.ready(rx_ready),
|
||||
.busy(rx_busy));
|
||||
|
||||
|
||||
/* State Machine */
|
||||
/*
|
||||
|
||||
IDLE:
|
||||
- literally nothing is happening. the FIFO isn't being written to or read from. it should be empty.
|
||||
- an arm command over serial is what brings us into the ARM state
|
||||
|
||||
ARM:
|
||||
- popping things onto FIFO. if the fifo is halfway full, we pop them off too.
|
||||
- meeting the trigger condition is what moves us into the filing state
|
||||
|
||||
FILL:
|
||||
- popping things onto FIFO, until it's full. once it is full, we move into the downlinking state
|
||||
|
||||
DOWNLINK:
|
||||
- popping thing off of the FIFO until it's empty. once it's empty, we move back into the IDLE state
|
||||
*/
|
||||
|
||||
/* Downlink State Machine Controller */
|
||||
/*
|
||||
|
||||
- ila enters the downlink state
|
||||
- set fifo_output_request high for a clock cycle
|
||||
- when fifo_output_valid goes high, send fifo_data_out across the line
|
||||
- do nothing until tx_busy goes low
|
||||
- goto step 2
|
||||
|
||||
*/
|
||||
|
||||
logic [1:0] state;
|
||||
logic [2:0] downlink_fsm_state;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(rst) begin
|
||||
state <= `IDLE;
|
||||
downlink_fsm_state <= 0;
|
||||
tx_data <= 0;
|
||||
tx_start <= 0;
|
||||
end
|
||||
else begin
|
||||
|
||||
case (state)
|
||||
`IDLE : begin
|
||||
fifo_input_ready <= 0;
|
||||
fifo_request_output <= 0;
|
||||
|
||||
if (rx_ready && rx_data == `ARM_BYTE) state <= `ARM;
|
||||
|
||||
end
|
||||
|
||||
`ARM : begin
|
||||
// place samples into FIFO
|
||||
fifo_input_ready <= 1;
|
||||
fifo_data_in <= concat;
|
||||
|
||||
// remove old samples if we're more than halfway full
|
||||
fifo_request_output <= (fifo_size >= SAMPLE_DEPTH / 2);
|
||||
|
||||
if(trigger) state <= `FILL;
|
||||
end
|
||||
|
||||
`FILL : begin
|
||||
// place samples into FIFO
|
||||
fifo_input_ready <= 1;
|
||||
fifo_data_in <= concat;
|
||||
|
||||
// don't pop anything out the FIFO
|
||||
fifo_request_output <= 0;
|
||||
|
||||
if(fifo_size == SAMPLE_DEPTH - 1) state <= `DOWNLINK;
|
||||
end
|
||||
|
||||
`DOWNLINK : begin
|
||||
// place no samples into FIFO
|
||||
fifo_input_ready <= 0;
|
||||
|
||||
|
||||
case (downlink_fsm_state)
|
||||
0 : begin
|
||||
if (~fifo_empty) begin
|
||||
fifo_request_output <= 1;
|
||||
downlink_fsm_state <= 1;
|
||||
end
|
||||
|
||||
else state <= `IDLE;
|
||||
end
|
||||
|
||||
1 : begin
|
||||
fifo_request_output <= 0;
|
||||
|
||||
if (fifo_output_valid) begin
|
||||
tx_data <= fifo_data_out;
|
||||
tx_start <= 1;
|
||||
downlink_fsm_state <= 2;
|
||||
end
|
||||
end
|
||||
|
||||
2 : begin
|
||||
tx_start <= 0;
|
||||
|
||||
if (~tx_busy && ~tx_start) downlink_fsm_state <= 0;
|
||||
end
|
||||
endcase
|
||||
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`default_nettype wire
|
||||
324
manta
324
manta
|
|
@ -1,324 +0,0 @@
|
|||
#!/usr/bin/python3
|
||||
from sys import argv
|
||||
import os
|
||||
import json
|
||||
import yaml
|
||||
from datetime import datetime
|
||||
import serial
|
||||
|
||||
debug = True
|
||||
version = '0.0.0'
|
||||
downlink_template = ''
|
||||
|
||||
def load_config(path):
|
||||
"""Take path to configuration file, and retun the configuration as a python list/dict object."""
|
||||
extension = path.split('.')[-1]
|
||||
|
||||
if 'json' in extension:
|
||||
with open(path, 'r') as f:
|
||||
config = json.load(f)
|
||||
|
||||
return config
|
||||
|
||||
elif 'yaml' in extension or 'yml' in extension:
|
||||
with open(path, 'r') as f:
|
||||
config = yaml.safe_load(f)
|
||||
|
||||
return config
|
||||
|
||||
else:
|
||||
raise ValueError('Unable to recognize configuration file extension.')
|
||||
|
||||
def check_config(config):
|
||||
"""Takes a list/dict python object representing a core configuration and throws an error if it is misconfigured."""
|
||||
|
||||
assert 'downlink' in config or 'uplink' in config, 'No downlink or uplink specified.'
|
||||
|
||||
if 'downlink' in config:
|
||||
|
||||
dl = config['downlink']
|
||||
assert dl['sample_depth'], 'Downlink core specified, but sample_depth not specified.'
|
||||
assert dl['clock_freq'], 'Downlink core specified, but clock_freq not specified.'
|
||||
assert dl['probes'] and len(dl['probes']) > 0, 'Downlink core specified, but no probes specified.'
|
||||
assert dl['triggers'] and len(dl['triggers']) > 0, 'Downlink core specified, but no triggers specified.'
|
||||
|
||||
# confirm core clock is sufficiently fast
|
||||
prescaler = dl['clock_freq'] // config['uart']['baudrate']
|
||||
assert prescaler >= 2
|
||||
|
||||
# confirm actual baudrate and target baudrate are within 5%
|
||||
actual_baudrate = config['downlink']['clock_freq'] / prescaler
|
||||
baudrate_error = abs(actual_baudrate - config['uart']['baudrate']) / config['uart']['baudrate']
|
||||
assert baudrate_error <= 0.05, f'Unable to match target baudrate! Actual baudrate differs from target by {round(100*baudrate_error, 2)}%'
|
||||
|
||||
if debug:
|
||||
print(f'UART interface on debug core will the following configuration:')
|
||||
print(f' - target_baudrate: {config["uart"]["baudrate"]}')
|
||||
print(f' - prescaler: {prescaler}')
|
||||
print(f' - actual_baudrate: {round(actual_baudrate, 2)}')
|
||||
|
||||
if 'uplink' in config:
|
||||
raise NotImplementedError('Cannot check configuration validity for uplinks just yet!')
|
||||
|
||||
if 'uart' in config:
|
||||
uart = config['uart']
|
||||
|
||||
# confirm number of data bits is valid
|
||||
assert 'data' in uart, 'Number of data bits in UART interface not specified.'
|
||||
assert uart['data'] in [8, 7, 6, 5], 'Invalid number of data bits.'
|
||||
|
||||
# confirm number of stop bits is valid
|
||||
assert uart['stop'] in [1, 1.5, 2], 'Invalid number of stop bits.'
|
||||
|
||||
# confirm parity is valid
|
||||
assert uart['parity'] in ['none', 'even', 'odd', 'mark', 'space'], 'Invalid parity setting.'
|
||||
|
||||
def gen_downlink_core(config):
|
||||
buf = downlink_template
|
||||
dl = config['downlink']
|
||||
|
||||
# add timestamp
|
||||
timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S")
|
||||
buf = buf.replace('@TIMESTAMP', timestamp)
|
||||
|
||||
# add user
|
||||
user = os.environ.get('USER', os.environ.get('USERNAME'))
|
||||
buf = buf.replace('@USER', user)
|
||||
|
||||
# add trigger
|
||||
trigger = [f'({trigger})' for trigger in dl['triggers']]
|
||||
trigger = ' || '.join(trigger)
|
||||
buf = buf.replace('@TRIGGER', trigger)
|
||||
|
||||
# add concat
|
||||
concat = [name for name in dl['probes']]
|
||||
concat = ', '.join(concat)
|
||||
concat = '{' + concat + '};'
|
||||
buf = buf.replace('@CONCAT', concat)
|
||||
|
||||
# add probes
|
||||
probe_verilog = []
|
||||
for name, width in dl['probes'].items():
|
||||
if width == 1:
|
||||
probe_verilog.append(f'input wire {name},')
|
||||
|
||||
else:
|
||||
probe_verilog.append(f'input wire [{width-1}:0] {name},')
|
||||
|
||||
probe_verilog = '\n\t'.join(probe_verilog)
|
||||
buf = buf.replace('@PROBES', probe_verilog)
|
||||
|
||||
# add sample width
|
||||
sample_width = sum([width for name, width in dl['probes'].items()])
|
||||
buf = buf.replace('@SAMPLE_WIDTH', sample_width)
|
||||
|
||||
# add sample depth
|
||||
buf = buf.replace('@SAMPLE_DEPTH', dl['sample_depth'])
|
||||
|
||||
# uart config
|
||||
buf = buf.replace('@DATA_WIDTH', str(config['uart']['data']))
|
||||
buf = buf.replace('@BAUDRATE', str(config['uart']['baudrate']))
|
||||
buf = buf.replace('@CLK_FREQ_HZ', str(config['uart']['clock_freq']))
|
||||
|
||||
return buf
|
||||
|
||||
def print_help():
|
||||
help = f"""
|
||||
Manta v{version} - An In-Situ Debugging Tool for Programmable Hardware
|
||||
|
||||
Supported commands:
|
||||
gen [config file] generate the core specified in the config file
|
||||
run [config file] run the core specified in the config file
|
||||
terminal [config file] present a minicom-like serial terminal with the UART settings in the config file
|
||||
ports list all available serial ports
|
||||
help display this help message
|
||||
ray display a splash screen (hehe...splash screen)
|
||||
"""
|
||||
print(help)
|
||||
|
||||
def print_ray():
|
||||
color_ray = f"""
|
||||
\033[96m (\.-./)
|
||||
\033[96m / \\
|
||||
\033[96m .' : '.
|
||||
\033[96m _.-'` ' `'-._ \033[34;49;1m | Manta v{version} \033[00m
|
||||
\033[96m .-' : '-. \033[34;49;3m | An In-Situ Debugging Tool for Programmable Hardware\033[00m
|
||||
\033[96m ,'_.._ . _.._', \033[34;49m | https://github.com/fischermoseley/manta\033[00m
|
||||
\033[96m '` `'-. ' .-'`
|
||||
\033[96m '. : .' \033[34;49;3m | fischerm [at] mit.edu\033[00m
|
||||
\033[96m \_. ._/
|
||||
\033[96m \ |^|
|
||||
\033[96m | | ;
|
||||
\033[96m \\'.___.' /
|
||||
\033[96m '-....-' \033[00m"""
|
||||
print(color_ray)
|
||||
|
||||
def setup_serial(ser, config):
|
||||
ser.baudrate = config['uart']['baudrate']
|
||||
ser.port = config['uart']['port']
|
||||
ser.timeout = config['uart']['timeout']
|
||||
|
||||
# setup number of data bits
|
||||
if config['uart']['data'] == 8:
|
||||
ser.bytesize = serial.EIGHTBITS
|
||||
|
||||
elif config['uart']['data'] == 7:
|
||||
ser.bytesize = serial.SEVENBITS
|
||||
|
||||
elif config['uart']['data'] == 6:
|
||||
ser.bytesize = serial.SIXBITS
|
||||
|
||||
elif config['uart']['data'] == 5:
|
||||
ser.bytesize = serial.FIVEBITS
|
||||
|
||||
else:
|
||||
raise ValueError("Invalid number of data bits in UART configuration.")
|
||||
|
||||
# setup number of stop bits
|
||||
if config['uart']['stop'] == 1:
|
||||
ser.stopbits = serial.STOPBITS_ONE
|
||||
|
||||
elif config['uart']['stop'] == 1.5:
|
||||
ser.stopbits = serial.STOPBITS_ONE_POINT_FIVE
|
||||
|
||||
elif config['uart']['stop'] == 2:
|
||||
ser.stopbits = serial.STOPBITS_TWO
|
||||
|
||||
else:
|
||||
raise ValueError("Invalid number of stop bits in UART configuration.")
|
||||
|
||||
# setup parity
|
||||
if config['uart']['parity'] == 'none':
|
||||
ser.parity = serial.PARITY_NONE
|
||||
|
||||
elif config['uart']['parity'] == 'even':
|
||||
ser.parity = serial.PARITY_EVEN
|
||||
|
||||
elif config['uart']['parity'] == 'odd':
|
||||
ser.parity = serial.PARITY_ODD
|
||||
|
||||
elif config['uart']['parity'] == 'mark':
|
||||
ser.parity = serial.PARITY_MARK
|
||||
|
||||
elif config['uart']['parity'] == 'space':
|
||||
ser.parity = serial.PARITY_SPACE
|
||||
|
||||
else:
|
||||
raise ValueError("Invalid parity setting in UART configuration.")
|
||||
|
||||
def read_serial(config):
|
||||
# obtain bytestream from FPGA
|
||||
with serial.Serial() as ser:
|
||||
setup_serial(ser, config)
|
||||
ser.open()
|
||||
ser.flushInput()
|
||||
ser.write(b'\x30')
|
||||
data = ser.read(4096)
|
||||
|
||||
return data
|
||||
|
||||
def part_select(data, width):
|
||||
top, bottom = width
|
||||
|
||||
assert top >= bottom
|
||||
|
||||
mask = 2**(top - bottom + 1) - 1
|
||||
return (data >> bottom) & mask
|
||||
|
||||
def make_widths(config):
|
||||
# {probe0, probe1, probe2}
|
||||
# [12, 1, 3] should produce
|
||||
# [ (11,0) , (12, 12), (15,13) ]
|
||||
|
||||
widths = list(config['probes'].values())
|
||||
|
||||
parts = []
|
||||
for i, width in enumerate(widths):
|
||||
if (i == 0):
|
||||
parts.append( (width - 1, 0) )
|
||||
|
||||
else:
|
||||
parts.append( ((parts[i-1][1] + width) , (parts[i-1][1] + 1)) )
|
||||
|
||||
# reversing this list is a little bit of a hack, should fix/document
|
||||
return parts[::-1]
|
||||
|
||||
def export_waveform(config, data, path):
|
||||
extension = path.split('.')[-1]
|
||||
|
||||
if extension == 'vcd':
|
||||
from vcd import VCDWriter
|
||||
vcd_file = open(path, 'w')
|
||||
timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S")
|
||||
|
||||
with VCDWriter(vcd_file, timescale='10 ns', date=timestamp, version = 'manta') as writer:
|
||||
|
||||
# add probes to vcd file
|
||||
vcd_probes = []
|
||||
for name, width in config['probes'].items():
|
||||
probe = writer.register_var('ila', name, 'wire', size = width)
|
||||
vcd_probes.append(probe)
|
||||
|
||||
# calculate bit widths for part selecting
|
||||
widths = make_widths(config)
|
||||
|
||||
# slice data, and dump to vcd file
|
||||
for timestamp, value in enumerate(data):
|
||||
for probe_num, probe in enumerate(vcd_probes):
|
||||
val = part_select(value, widths[probe_num])
|
||||
writer.change(probe, timestamp, val)
|
||||
|
||||
vcd_file.close()
|
||||
|
||||
else:
|
||||
raise NotImplementedError('More file formats to come!')
|
||||
|
||||
if __name__ == '__main__':
|
||||
# print help menu if no args passed or help menu requested
|
||||
if len(argv) == 1 or argv[1] == 'help':
|
||||
print_help()
|
||||
exit()
|
||||
|
||||
# open minicom-like serial terminal with given config
|
||||
elif argv[1] == 'terminal':
|
||||
assert len(argv) == 3, 'Not enough (or too many) config files specified.'
|
||||
|
||||
# TODO: make this work with a looser config file - it should work even if we just have a uart definition
|
||||
config = load_config(argv[2])
|
||||
check_config(config)
|
||||
|
||||
raise NotImplementedError('Miniterm console is still under development!')
|
||||
|
||||
# list available serial ports
|
||||
elif argv[1] == 'ports':
|
||||
import serial.tools.list_ports
|
||||
|
||||
for info in serial.tools.list_ports.comports():
|
||||
print(info)
|
||||
|
||||
# show splash screen
|
||||
elif argv[1] == 'ray':
|
||||
print_ray()
|
||||
exit()
|
||||
|
||||
# generate the specified core
|
||||
elif argv[1] == 'gen':
|
||||
assert len(argv) == 4, 'Wrong number of arguments, only a config file and output file must both be specified.'
|
||||
config = load_config(argv[2])
|
||||
check_config(config)
|
||||
|
||||
with open(argv[3], 'w') as f:
|
||||
f.write(gen_downlink_core(config))
|
||||
|
||||
# run the specified core
|
||||
elif argv[1] == 'run':
|
||||
assert len(argv) == 4, 'Wrong number of arguments, only a config file and output file must both be specified.'
|
||||
config = load_config(argv[2])
|
||||
check_config(config)
|
||||
|
||||
data = read_serial(config)
|
||||
export_waveform(config, data, argv[3])
|
||||
|
||||
else:
|
||||
print('Option not recognized.')
|
||||
print_help()
|
||||
24
manta.py
24
manta.py
|
|
@ -5,9 +5,25 @@ import yaml
|
|||
from datetime import datetime
|
||||
import serial
|
||||
|
||||
|
||||
debug = True
|
||||
version = '0.0.0'
|
||||
downlink_template = ''
|
||||
|
||||
|
||||
def load_source_files(path):
|
||||
"""concatenates the list of files provided into a single string"""
|
||||
source_files = [f for f in os.listdir(path) if os.path.isfile(os.path.join(path, f))]
|
||||
source_files = [f for f in source_files if f.split('.')[-1] in ['sv', 'v']]
|
||||
|
||||
buf = ""
|
||||
for source_file in source_files:
|
||||
with open(path + source_file, 'r') as f:
|
||||
buf += f.read()
|
||||
|
||||
return buf
|
||||
|
||||
|
||||
downlink_template = load_source_files('src/')
|
||||
|
||||
def load_config(path):
|
||||
"""Take path to configuration file, and retun the configuration as a python list/dict object."""
|
||||
|
|
@ -109,15 +125,15 @@ def gen_downlink_core(config):
|
|||
|
||||
# add sample width
|
||||
sample_width = sum([width for name, width in dl['probes'].items()])
|
||||
buf = buf.replace('@SAMPLE_WIDTH', sample_width)
|
||||
buf = buf.replace('@SAMPLE_WIDTH', str(sample_width))
|
||||
|
||||
# add sample depth
|
||||
buf = buf.replace('@SAMPLE_DEPTH', dl['sample_depth'])
|
||||
buf = buf.replace('@SAMPLE_DEPTH', str(dl['sample_depth']))
|
||||
|
||||
# uart config
|
||||
buf = buf.replace('@DATA_WIDTH', str(config['uart']['data']))
|
||||
buf = buf.replace('@BAUDRATE', str(config['uart']['baudrate']))
|
||||
buf = buf.replace('@CLK_FREQ_HZ', str(config['uart']['clock_freq']))
|
||||
buf = buf.replace('@CLK_FREQ_HZ', str(dl['clock_freq']))
|
||||
|
||||
return buf
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue