remove legacy code, now feature complete with new scripts
This commit is contained in:
Fischer Moseley
parent
030a841f53
commit
566a3624d8
5
build.py
5
build.py
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@ -1,5 +0,0 @@
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import os
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os.system('echo "#!/usr/bin/python3" > manta')
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os.system("cat manta.py >> manta")
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os.system("chmod +x manta")
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@ -26,21 +26,21 @@ outfile = f"{of}/out.bit"
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logfile = f"{of}/build.log"
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synthrpt = [
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"report_timing",
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"report_timing_summary",
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"report_utilization",
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]
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"report_timing",
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"report_timing_summary",
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"report_utilization",
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]
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placerpt = synthrpt.copy()
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placerpt.extend(['report_clock_utilization'])
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placerpt.extend(["report_clock_utilization"])
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routerpt = [
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'report_drc',
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'report_power',
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'report_route_status',
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'report_timing',
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'report_timing_summary',
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]
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"report_drc",
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"report_power",
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"report_route_status",
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"report_timing",
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"report_timing_summary",
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]
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usagestr = f"""
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{progname}: build SystemVerilog code remotely for 2022 6.205 labs
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@ -54,190 +54,248 @@ options:
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-o: set the output products directory (default is {of})
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"""
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def debuglog(s):
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if verbose: print(s)
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if verbose:
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print(s)
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def usage():
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print(usagestr)
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sys.exit(1)
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print(usagestr)
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sys.exit(1)
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def getargs():
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global diagnostics
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global quiet
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global machine
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global logfile
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global outfile
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global projectdir
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global of
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global verbose
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global diagnostics
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global quiet
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global machine
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global logfile
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global outfile
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global projectdir
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global of
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global verbose
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try:
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opts, args = getopt.getopt(sys.argv[1:], "dm:o:p:qv")
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except getopt.GetoptError as err:
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print(err)
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usage()
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try:
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opts, args = getopt.getopt(sys.argv[1:], "dm:o:p:qv")
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except getopt.GetoptError as err:
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print(err)
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usage()
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if args: usage()
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for o, v in opts:
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if o == '-d': diagnostics = True
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elif o == '-q': quiet = True
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elif o == '-m': machine = v
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elif o == '-p': projectdir = v
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elif o == '-o': of = v
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elif o == '-v': verbose = True
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else:
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print(f"unrecognized option {o}")
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usage()
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if args:
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usage()
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for o, v in opts:
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if o == "-d":
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diagnostics = True
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elif o == "-q":
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quiet = True
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elif o == "-m":
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machine = v
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elif o == "-p":
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projectdir = v
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elif o == "-o":
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of = v
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elif o == "-v":
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verbose = True
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else:
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print(f"unrecognized option {o}")
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usage()
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outfile = f"{of}/out.bit"
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logfile = f"{of}/build.log"
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outfile = f"{of}/out.bit"
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logfile = f"{of}/build.log"
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def make_posix(path):
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return str(pathlib.Path(path).as_posix())
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return str(pathlib.Path(path).as_posix())
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def regfiles():
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ftt = {}
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debuglog(f"projectdir is {projectdir}")
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for dirpath, subdirs, files in os.walk(projectdir):
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if 'src' not in dirpath and 'xdc' not in dirpath and 'data' not in dirpath and 'ip' not in dirpath:
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continue
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if dirpath.startswith("./"): dirpath = dirpath[2:]
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for file in files:
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fpath = os.path.join(dirpath, file)
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debuglog(f"considering {fpath}")
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fpath = make_posix(fpath)
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ftt = {}
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debuglog(f"projectdir is {projectdir}")
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for dirpath, subdirs, files in os.walk(projectdir):
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if (
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"src" not in dirpath
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and "xdc" not in dirpath
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and "data" not in dirpath
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and "ip" not in dirpath
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):
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continue
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if dirpath.startswith("./"):
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dirpath = dirpath[2:]
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for file in files:
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fpath = os.path.join(dirpath, file)
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debuglog(f"considering {fpath}")
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fpath = make_posix(fpath)
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if file.lower().endswith('.v'): ftt[fpath] = 'source'
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elif file.lower().endswith('.sv'): ftt[fpath] = 'source'
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elif file.lower().endswith('.vh'): ftt[fpath] = 'source'
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elif file.lower().endswith('.svh'): ftt[fpath] = 'source'
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elif file.lower().endswith('.xdc'): ftt[fpath] = 'xdc'
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elif file.lower().endswith('.mem'): ftt[fpath] = 'mem'
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elif file.lower().endswith('.xci'): ftt[fpath] = 'ip'
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elif file.lower().endswith('.prj'): ftt[fpath] = 'mig'
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if file.lower().endswith(".v"):
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ftt[fpath] = "source"
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elif file.lower().endswith(".sv"):
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ftt[fpath] = "source"
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elif file.lower().endswith(".vh"):
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ftt[fpath] = "source"
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elif file.lower().endswith(".svh"):
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ftt[fpath] = "source"
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elif file.lower().endswith(".xdc"):
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ftt[fpath] = "xdc"
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elif file.lower().endswith(".mem"):
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ftt[fpath] = "mem"
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elif file.lower().endswith(".xci"):
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ftt[fpath] = "ip"
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elif file.lower().endswith(".prj"):
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ftt[fpath] = "mig"
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debuglog(f"elaborated file list {ftt}")
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return ftt
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debuglog(f"elaborated file list {ftt}")
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return ftt
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# messages are newline delineated per lab-bs.1
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# utilize this to cheat a little bit
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def spqsend(p, msg):
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debuglog(f"writing {len(msg)} bytes over the wire")
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debuglog(f"full message: {msg}")
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p.stdin.write(msg + b'\n')
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p.stdin.flush()
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debuglog(f"writing {len(msg)} bytes over the wire")
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debuglog(f"full message: {msg}")
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p.stdin.write(msg + b"\n")
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p.stdin.flush()
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def spsend(p, msg):
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debuglog(f"running {msg}")
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p.stdin.write((msg + '\n').encode())
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p.stdin.flush()
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debuglog(f"running {msg}")
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p.stdin.write((msg + "\n").encode())
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p.stdin.flush()
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def sprecv(p):
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l = p.stdout.readline().decode()
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debuglog(f"got {l}")
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return l
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l = p.stdout.readline().decode()
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debuglog(f"got {l}")
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return l
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def xsprecv(p):
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l = sprecv(p)
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if (l.startswith("ERR")):
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print("received unexpected server error!")
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print(l)
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sys.exit(1)
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return l
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l = sprecv(p)
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if l.startswith("ERR"):
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print("received unexpected server error!")
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print(l)
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sys.exit(1)
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return l
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def spstart(xargv):
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debuglog(f"spawning {xargv}")
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p = subprocess.PIPE
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return subprocess.Popen(xargv, stdin=p, stdout=p, stderr=p)
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debuglog(f"spawning {xargv}")
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p = subprocess.PIPE
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return subprocess.Popen(xargv, stdin=p, stdout=p, stderr=p)
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def copyfiles(p, ftt):
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for f, t in ftt.items():
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fsize = os.path.getsize(f)
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with open(f, 'rb') as fd:
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spsend(p, f"write {f} {fsize}")
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time.sleep(0.1) #?
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spqsend(p, fd.read())
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xsprecv(p)
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for f, t in ftt.items():
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fsize = os.path.getsize(f)
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with open(f, "rb") as fd:
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spsend(p, f"write {f} {fsize}")
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time.sleep(0.1) # ?
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spqsend(p, fd.read())
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xsprecv(p)
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spsend(p, f"type {f} {t}")
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xsprecv(p)
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spsend(p, f"type {f} {t}")
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xsprecv(p)
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# size message returns ... %zu bytes
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def readfile(p, file, targetfile):
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spsend(p, f"size {file}")
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size = int(xsprecv(p).split()[-2])
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spsend(p, f"read {file}")
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spsend(p, f"size {file}")
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size = int(xsprecv(p).split()[-2])
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spsend(p, f"read {file}")
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with open(targetfile, "wb+") as fd:
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fd.write(p.stdout.read(size))
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xsprecv(p)
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with open(targetfile, 'wb+') as fd:
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fd.write(p.stdout.read(size))
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xsprecv(p)
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def build(p):
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cmd = "build"
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if diagnostics: cmd += " -d"
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if quiet: cmd += " -q"
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cmd += f" obj"
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cmd = "build"
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if diagnostics:
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cmd += " -d"
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if quiet:
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cmd += " -q"
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cmd += f" obj"
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print(f"Output target will be {outfile}")
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print(f"Output target will be {outfile}")
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spsend(p, cmd)
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print("Building your code ... (this may take a while, be patient)")
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result = sprecv(p)
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spsend(p, cmd)
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print("Building your code ... (this may take a while, be patient)")
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result = sprecv(p)
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if result.startswith("ERR"): print("Something went wrong!")
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else:
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readfile(p, "obj/out.bit", outfile)
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print(f"Build succeeded, output at {outfile}")
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readfile(p, "obj/build.log", logfile)
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print(f"Log file available at {logfile}")
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if result.startswith("ERR"):
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print("Something went wrong!")
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else:
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readfile(p, "obj/out.bit", outfile)
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print(f"Build succeeded, output at {outfile}")
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readfile(p, "obj/build.log", logfile)
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print(f"Log file available at {logfile}")
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if diagnostics:
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for rpt in synthrpt:
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readfile(p, f"obj/synthrpt_{rpt}.rpt", f"{of}/synthrpt_{rpt}.rpt")
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for rpt in placerpt:
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readfile(p, f"obj/placerpt_{rpt}.rpt", f"{of}/placerpt_{rpt}.rpt")
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for rpt in routerpt:
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readfile(p, f"obj/routerpt_{rpt}.rpt", f"{of}/routerpt_{rpt}.rpt")
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print(f"Diagnostics available in {of}")
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if (diagnostics):
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for rpt in synthrpt:
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readfile(p, f"obj/synthrpt_{rpt}.rpt", f"{of}/synthrpt_{rpt}.rpt")
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for rpt in placerpt:
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readfile(p, f"obj/placerpt_{rpt}.rpt", f"{of}/placerpt_{rpt}.rpt")
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for rpt in routerpt:
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readfile(p, f"obj/routerpt_{rpt}.rpt", f"{of}/routerpt_{rpt}.rpt")
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print(f"Diagnostics available in {of}")
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def main():
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global p
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getargs()
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ftt = regfiles()
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global p
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getargs()
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ftt = regfiles()
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if not os.path.isdir(of):
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print(f"output path {of} does not exist! create it or use -o?")
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usage()
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if platform.system() == 'Darwin' or platform.system() == 'Linux':
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xargv = ['ssh', '-p', f"{port}", '-o', "StrictHostKeyChecking=no", '-o', 'UserKnownHostsFile=/dev/null']
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if not os.path.isdir(of):
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print(f"output path {of} does not exist! create it or use -o?")
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usage()
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elif platform.system() == 'Windows':
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xargv = ['ssh', '-p', f"{port}", '-o', "StrictHostKeyChecking=no", '-o', 'UserKnownHostsFile=nul']
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if platform.system() == "Darwin" or platform.system() == "Linux":
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xargv = [
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"ssh",
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"-p",
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f"{port}",
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"-o",
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"StrictHostKeyChecking=no",
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"-o",
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"UserKnownHostsFile=/dev/null",
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]
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else:
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raise RuntimeError('Your OS is not recognized, unsure of how to format SSH command.')
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xargv.append(f"{user}@{machine}")
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p = spstart(xargv)
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elif platform.system() == "Windows":
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xargv = [
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"ssh",
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"-p",
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f"{port}",
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"-o",
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"StrictHostKeyChecking=no",
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"-o",
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"UserKnownHostsFile=nul",
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]
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else:
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raise RuntimeError(
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"Your OS is not recognized, unsure of how to format SSH command."
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)
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xargv.append(f"{user}@{machine}")
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p = spstart(xargv)
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spsend(p, "help")
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result = xsprecv(p)
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debuglog(result)
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copyfiles(p, ftt)
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build(p)
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spsend(p, "exit")
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p.wait()
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spsend(p, "help")
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result = xsprecv(p)
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debuglog(result)
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copyfiles(p, ftt)
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build(p)
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spsend(p, "exit")
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p.wait()
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if __name__ == "__main__":
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try: main()
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except (Exception, KeyboardInterrupt) as e:
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if p:
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debuglog("killing ssh")
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os.kill(p.pid, signal.SIGINT)
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p.wait()
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raise e
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try:
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main()
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except (Exception, KeyboardInterrupt) as e:
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if p:
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debuglog("killing ssh")
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os.kill(p.pid, signal.SIGINT)
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p.wait()
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raise e
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|
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71
gen_ila.py
71
gen_ila.py
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@ -1,71 +0,0 @@
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import json
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import yaml
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from datetime import datetime
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import os
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# this works by taking a template file, parsing it for hooks, and then dropping in our spicy bits of verilog in those hooks.
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# might update this later to just properly instantiate an ILA for us and we do this with parameters, but
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# the fundamental thing i care about is that systemverilog does not live in this file.
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fpath = 'ila.json' # will update for argv soon!
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with open(fpath, 'r') as f:
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config = json.load(f)
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# make sure file is okay
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assert config["probes"]
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assert config["triggers"]
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assert config["uart"] or config["ethernet"] # <- i have ideas hehe
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def splice(source, find, replace):
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# find all instances of find in the source, and replace with replace
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#assert source.count(find) == 1
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return source.replace(find, replace)
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with open('src/ila_template.sv', 'r') as t:
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ila_template = t.read()
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# add timestamp and user
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timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S")
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ila_template = splice(ila_template, '@TIMESTAMP', timestamp);
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user = os.environ.get('USER', os.environ.get('USERNAME'))
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ila_template = splice(ila_template, '@USER', user);
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# add trigger
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trigger = [f'({trigger})' for trigger in config['triggers']]
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trigger = ' || '.join(trigger)
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ila_template = splice(ila_template, '@TRIGGER', trigger);
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# add concat
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concat = [name for name in config['probes']]
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concat = ', '.join(concat)
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concat = '{' + concat + '};'
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ila_template = splice(ila_template, '@CONCAT', concat);
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# add probes to ila module definition
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probe_verilog = []
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for name, width in config['probes'].items():
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if width == 1:
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probe_verilog.append(f'input wire {name},')
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else:
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probe_verilog.append(f'input wire [{width-1}:0] {name},')
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probe_verilog = '\n\t'.join(probe_verilog)
|
||||
ila_template = splice(ila_template, '@PROBES', probe_verilog);
|
||||
|
||||
# add sample width and depth
|
||||
sample_width = sum([width for name, width in config['probes'].items()])
|
||||
ila_template = splice(ila_template, '@SAMPLE_WIDTH', str(sample_width))
|
||||
ila_template = splice(ila_template, '@SAMPLE_DEPTH', str(config['sample_depth']));
|
||||
|
||||
# add UART configuration
|
||||
ila_template = splice(ila_template, '@DATA_WIDTH', str(int(config['uart']['data'])));
|
||||
ila_template = splice(ila_template, '@BAUDRATE', str(config['uart']['baudrate']));
|
||||
ila_template = splice(ila_template, '@CLK_FREQ_HZ', str(int(config['clock_freq'])));
|
||||
|
||||
# write output file
|
||||
with open('src/ila.sv', 'w') as i:
|
||||
i.write(ila_template)
|
||||
4
manta.py
4
manta.py
|
|
@ -278,7 +278,7 @@ def make_widths(config):
|
|||
# [12, 1, 3] should produce
|
||||
# [ (11,0) , (12, 12), (15,13) ]
|
||||
|
||||
widths = list(config["probes"].values())
|
||||
widths = list(config["downlink"]["probes"].values())
|
||||
|
||||
parts = []
|
||||
for i, width in enumerate(widths):
|
||||
|
|
@ -306,7 +306,7 @@ def export_waveform(config, data, path):
|
|||
) as writer:
|
||||
# add probes to vcd file
|
||||
vcd_probes = []
|
||||
for name, width in config["probes"].items():
|
||||
for name, width in config["downlink"]["probes"].items():
|
||||
probe = writer.register_var("ila", name, "wire", size=width)
|
||||
vcd_probes.append(probe)
|
||||
|
||||
|
|
|
|||
159
run_ila.py
159
run_ila.py
|
|
@ -1,159 +0,0 @@
|
|||
from sys import argv
|
||||
import json
|
||||
import serial
|
||||
from vcd import VCDWriter
|
||||
from datetime import datetime
|
||||
|
||||
def check_config(config):
|
||||
"""Check that configuration is okay"""
|
||||
assert config["probes"]
|
||||
assert config["triggers"]
|
||||
assert config["uart"]
|
||||
|
||||
def setup_serial(ser, config):
|
||||
ser.baudrate = config['uart']['baudrate']
|
||||
ser.port = config['uart']['port']
|
||||
ser.timeout = config['uart']['timeout']
|
||||
|
||||
# setup number of data bits
|
||||
if config['uart']['data'] == 8:
|
||||
ser.bytesize = serial.EIGHTBITS
|
||||
|
||||
elif config['uart']['data'] == 7:
|
||||
ser.bytesize = serial.SEVENBITS
|
||||
|
||||
elif config['uart']['data'] == 6:
|
||||
ser.bytesize = serial.SIXBITS
|
||||
|
||||
elif config['uart']['data'] == 5:
|
||||
ser.bytesize = serial.FIVEBITS
|
||||
|
||||
else:
|
||||
raise ValueError("Invalid number of data bits in UART configuration.")
|
||||
|
||||
# setup number of stop bits
|
||||
if config['uart']['stop'] == 1:
|
||||
ser.stopbits = serial.STOPBITS_ONE
|
||||
|
||||
elif config['uart']['stop'] == 1.5:
|
||||
ser.stopbits = serial.STOPBITS_ONE_POINT_FIVE
|
||||
|
||||
elif config['uart']['stop'] == 2:
|
||||
ser.stopbits = serial.STOPBITS_TWO
|
||||
|
||||
else:
|
||||
raise ValueError("Invalid number of stop bits in UART configuration.")
|
||||
|
||||
# setup parity
|
||||
if config['uart']['parity'] == 'none':
|
||||
ser.parity = serial.PARITY_NONE
|
||||
|
||||
elif config['uart']['parity'] == 'even':
|
||||
ser.parity = serial.PARITY_EVEN
|
||||
|
||||
elif config['uart']['parity'] == 'odd':
|
||||
ser.parity = serial.PARITY_ODD
|
||||
|
||||
elif config['uart']['parity'] == 'mark':
|
||||
ser.parity = serial.PARITY_MARK
|
||||
|
||||
elif config['uart']['parity'] == 'space':
|
||||
ser.parity = serial.PARITY_SPACE
|
||||
|
||||
else:
|
||||
raise ValueError("Invalid parity setting in UART configuration.")
|
||||
|
||||
def part_select(data, width):
|
||||
top, bottom = width
|
||||
|
||||
assert top >= bottom
|
||||
|
||||
mask = 2**(top - bottom + 1) - 1
|
||||
return (data >> bottom) & mask
|
||||
|
||||
def make_widths(config):
|
||||
# {probe0, probe1, probe2}
|
||||
# [12, 1, 3] should produce
|
||||
# [ (11,0) , (12, 12), (15,13) ]
|
||||
|
||||
widths = list(config['probes'].values())
|
||||
|
||||
parts = []
|
||||
for i, width in enumerate(widths):
|
||||
if (i == 0):
|
||||
parts.append( (width - 1, 0) )
|
||||
|
||||
else:
|
||||
parts.append( ((parts[i-1][1] + width) , (parts[i-1][1] + 1)) )
|
||||
|
||||
# reversing this list is a little bit of a hack, should fix/document
|
||||
return parts[::-1]
|
||||
|
||||
|
||||
## Main Program
|
||||
|
||||
# parse args
|
||||
if len(argv) == 1 or argv[1] == '-h':
|
||||
print("""
|
||||
run_ila.py: interface with the ILA on the FPGA, setting triggers and downlinking waveform data.
|
||||
usage: python3 run_ila.py [config input file] [vcd output file]
|
||||
options:
|
||||
-h: print this help menu
|
||||
-l: list all available serial devices
|
||||
|
||||
example: python3 run_ila.py ila.json ila.vcd
|
||||
""")
|
||||
exit()
|
||||
|
||||
elif argv[1] == '-l':
|
||||
import serial.tools.list_ports
|
||||
|
||||
for info in serial.tools.list_ports.comports():
|
||||
print(info)
|
||||
|
||||
elif len(argv) == 2:
|
||||
config_fpath = argv[1]
|
||||
vcd_fpath = 'ila.vcd'
|
||||
|
||||
|
||||
elif len(argv) == 3:
|
||||
config_fpath = argv[1]
|
||||
vcd_fpath = argv[2]
|
||||
|
||||
else:
|
||||
exit()
|
||||
|
||||
# read config
|
||||
with open(config_fpath, 'r') as f:
|
||||
config = json.load(f)
|
||||
|
||||
# obtain bytestream from FPGA
|
||||
with serial.Serial() as ser:
|
||||
setup_serial(ser, config)
|
||||
ser.open()
|
||||
ser.flushInput()
|
||||
ser.write(b'\x30')
|
||||
data = ser.read(4096)
|
||||
|
||||
# export VCD
|
||||
vcd_file = open(vcd_fpath, 'w')
|
||||
timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S")
|
||||
|
||||
with VCDWriter(vcd_file, timescale='10 ns', date=timestamp, version = 'openILA') as writer:
|
||||
|
||||
# add probes to vcd file
|
||||
vcd_probes = []
|
||||
for name, width in config['probes'].items():
|
||||
probe = writer.register_var('ila', name, 'wire', size = width)
|
||||
vcd_probes.append(probe)
|
||||
|
||||
# calculate bit widths for part selecting
|
||||
widths = make_widths(config)
|
||||
|
||||
# slice data, and dump to vcd file
|
||||
for timestamp, value in enumerate(data):
|
||||
for probe_num, probe in enumerate(vcd_probes):
|
||||
val = part_select(value, widths[probe_num])
|
||||
writer.change(probe, timestamp, val)
|
||||
|
||||
vcd_file.close()
|
||||
Loading…
Reference in New Issue