Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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978937e4bc
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modify example design naming convention
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2024-05-12 10:25:00 -07:00 |
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Fischer Moseley
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4ae061ffdc
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add missing .gitignore
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2024-03-07 09:21:40 -08:00 |
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Fischer Moseley
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04cfa41190
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add logic analyzer/io core ethernet example
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2024-03-07 09:18:30 -08:00 |
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Fischer Moseley
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60066ccdca
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add examples for the Nexys4DDR, bump version to 1.0.0
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2024-03-06 23:07:20 -08:00 |
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Fischer Moseley
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05b9b450e8
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add logic analyzer icestick example
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2024-03-06 22:05:24 -08:00 |
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Fischer Moseley
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21afbad7c4
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add icestick IO core example
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2024-03-06 21:47:03 -08:00 |
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Fischer Moseley
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bc616fd3bf
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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Fischer Moseley
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c38c0f561a
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add automated test to read from output probe
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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b4fb79bc8e
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add write/readback tests, seems to pass
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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060583d8fc
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add working io_core autogeneration
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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78a7cce83a
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add logic_analyzer_uart example
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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44a8c57dc5
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swap to zipcpu uart_rx
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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3af6f6ff0c
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add block_mem_uart example
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f5ef2bbb49
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remove more API calls that don't exist anymore
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2023-09-02 11:39:16 -04:00 |
Fischer Moseley
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4b9d941bc5
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fix API call that doesn't exist anymore, thanks Joe :)
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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c37a6e5e90
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move icestick build steps to makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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0044ae5884
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merge nexys makefile targets
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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7e707e1fc1
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manually specify vivado path in makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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d580419a5b
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remove lut_mem, clean up examples
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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8b9abd1b0b
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update examples, which appear to build :cowboy:
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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0840786914
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enforce consistent folder naming
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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112bd43963
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remove mention of wdata/rdata
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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adf355c633
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make examples build
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f5caca613a
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simplify uart/ether APIs, improve lazy loading
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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ab58af0bfc
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add video_sprite_ether example
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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15aa5f469f
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add ethernet_tx_tb
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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9c5ea31d14
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enforce consistent naming of lut_mem module
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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54b97fd120
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add working ethernet verilog autogeneration woot woot :)
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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b3d402c1f5
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refactor python/hdl structure
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7f9012b542
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tidy examples
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7cd8a2cfa5
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tidy up mac stack
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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6210e3cc39
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add working python api for ethernet tx/rx
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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8e139bba3a
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add working l2 mac in hardware - need to fix ethertype to get scapy to play nice
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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c507f795f1
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add ethernet_tx/rx, semi-working in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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0bb3f9c74a
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clean up mac_tx, working in simulation
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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64a582c786
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add working mac tx
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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dab6e3f272
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add working mac testbench - also found a problem in VCD logging
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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28f40f2b7b
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add working l2 send in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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357b7eed94
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refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
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2023-04-18 01:06:39 -04:00 |
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Fischer Moseley
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870d299c74
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add docs and add trigger config for logic analyzer
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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102bdee410
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update makefile to match positional args from PATH'd binaries
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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f6f9096895
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add batch read/write UART for speedo mode
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9cc2357ea4
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update command line positional args
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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7c1e4fc2c0
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add logic analyzer playback module auto-generation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9d8836bda3
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add prototype simulation replay
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1c74d4a714
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add running the logic analyzer to the python API
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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d8eeb65b8f
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fix pipelining in video_sprite exmaple
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2023-04-13 18:00:22 -04:00 |
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Fischer Moseley
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153ae7e3df
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video sprite example working! kinda frankensteined tho
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2023-04-13 17:02:55 -04:00 |
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Fischer Moseley
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d3213c6369
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update docs site outline
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2023-04-12 20:55:09 -04:00 |