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modify example design naming convention

This commit is contained in:
Fischer Moseley 2024-05-12 10:25:00 -07:00
parent 6c25f6e8d3
commit 978937e4bc
39 changed files with 0 additions and 0 deletions
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examples/verilog/icestick/io_core_uart/.gitignore → examples/verilog/icestick/uart_io_core/.gitignore vendored
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examples/verilog/icestick/io_core_uart/blinky.py → examples/verilog/icestick/uart_io_core/blinky.py
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examples/verilog/icestick/io_core_uart/build.sh → examples/verilog/icestick/uart_io_core/build.sh
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examples/verilog/icestick/io_core_uart/manta.yaml → examples/verilog/icestick/uart_io_core/manta.yaml
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examples/verilog/icestick/io_core_uart/top_level.pcf → examples/verilog/icestick/uart_io_core/top_level.pcf
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examples/verilog/icestick/io_core_uart/top_level.sv → examples/verilog/icestick/uart_io_core/top_level.sv
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examples/verilog/icestick/logic_analyzer_uart/.gitignore → examples/verilog/icestick/uart_logic_analyzer/.gitignore vendored
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examples/verilog/icestick/logic_analyzer_uart/build.sh → examples/verilog/icestick/uart_logic_analyzer/build.sh
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examples/verilog/icestick/logic_analyzer_uart/manta.yaml → examples/verilog/icestick/uart_logic_analyzer/manta.yaml
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examples/verilog/icestick/logic_analyzer_uart/top_level.pcf → examples/verilog/icestick/uart_logic_analyzer/top_level.pcf
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examples/verilog/icestick/logic_analyzer_uart/top_level.sv → examples/verilog/icestick/uart_logic_analyzer/top_level.sv
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/.gitignore vendored
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examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.sh → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.sh
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examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.tcl → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/build.tcl
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/divider.sv
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/manta.yaml → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/manta.yaml
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/test.py → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/test.py
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.sv
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.xdc → examples/verilog/nexys_a7/ether_logic_analyzer_io_core/top_level.xdc
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examples/verilog/nexys_a7/host_to_fpga_mem_uart/.gitignore → examples/verilog/nexys_a7/uart_host_to_fpga_mem/.gitignore vendored
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examples/verilog/nexys_a7/io_core_uart/build.sh → examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.sh
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examples/verilog/nexys_a7/io_core_uart/build.tcl → examples/verilog/nexys_a7/uart_host_to_fpga_mem/build.tcl
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examples/verilog/nexys_a7/host_to_fpga_mem_uart/manta.yaml → examples/verilog/nexys_a7/uart_host_to_fpga_mem/manta.yaml
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examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.sv → examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.sv
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examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc → examples/verilog/nexys_a7/uart_host_to_fpga_mem/top_level.xdc
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examples/verilog/nexys_a7/host_to_fpga_mem_uart/write.py → examples/verilog/nexys_a7/uart_host_to_fpga_mem/write.py
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examples/verilog/nexys_a7/io_core_uart/.gitignore → examples/verilog/nexys_a7/uart_io_core/.gitignore vendored
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examples/verilog/nexys_a7/io_core_uart/blinky.py → examples/verilog/nexys_a7/uart_io_core/blinky.py
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.sh → examples/verilog/nexys_a7/uart_io_core/build.sh
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examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.tcl → examples/verilog/nexys_a7/uart_io_core/build.tcl
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examples/verilog/nexys_a7/io_core_uart/manta.yaml → examples/verilog/nexys_a7/uart_io_core/manta.yaml
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examples/verilog/nexys_a7/io_core_uart/top_level.sv → examples/verilog/nexys_a7/uart_io_core/top_level.sv
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examples/verilog/nexys_a7/io_core_uart/top_level.xdc → examples/verilog/nexys_a7/uart_io_core/top_level.xdc
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examples/verilog/nexys_a7/logic_analyzer_uart/.gitignore → examples/verilog/nexys_a7/uart_logic_analyzer/.gitignore vendored
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examples/verilog/nexys_a7/logic_analyzer_uart/build.sh → examples/verilog/nexys_a7/uart_logic_analyzer/build.sh
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examples/verilog/nexys_a7/logic_analyzer_uart/build.tcl → examples/verilog/nexys_a7/uart_logic_analyzer/build.tcl
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examples/verilog/nexys_a7/logic_analyzer_uart/manta.yaml → examples/verilog/nexys_a7/uart_logic_analyzer/manta.yaml
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examples/verilog/nexys_a7/logic_analyzer_uart/top_level.sv → examples/verilog/nexys_a7/uart_logic_analyzer/top_level.sv
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examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc → examples/verilog/nexys_a7/uart_logic_analyzer/top_level.xdc
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