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472 Commits 9 Branches 4 Tags 14 MiB
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472 Commits

Author SHA1 Message Date
carabsc 4d9eeefc4d
Merge c3fe68d73d into 9ac3181502 2024-11-18 05:55:44 +00:00
Fischer Moseley 9ac3181502 examples: fix typos 2024-11-07 09:50:55 -07:00
Carlos Azevedo c3fe68d73d Create trigger blocks only for defined triggers. 
Adds YAML option 'trigger_pruned' support for the logic analyser to prevent the creation of trigger
blocks for probes not listed as triggers. This pruning allows much higher fmax for the designs.
 2024-11-06 03:01:48 +00:00
Fischer Moseley 599384ecc2 logic_analyzer: add and use clock_freq property 2024-10-12 14:37:14 -07:00
Fischer Moseley 3fab791329 readme: add codecov badge 2024-10-08 10:59:02 -07:00
Fischer Moseley dc0f79374a ci: install dev dependencies to obtain mkdocstrings 2024-10-08 10:48:01 -07:00
Fischer Moseley 746d4cf1d5 logic_analyzer: fix missing import 2024-10-08 11:42:10 -06:00
Fischer Moseley 4b7c03e722 logic_analyzer: pass interface when constructing LogicAnalyzerCapture 2024-10-08 11:42:10 -06:00
Fischer Moseley 583d9e0d83 logic_analyzer: tidy some formatting/typos from rebase 2024-10-08 11:42:10 -06:00
Fischer Moseley cfbf372862 uart: remove flaky nexys4ddr baudrate mismatch test case 2024-10-08 11:42:10 -06:00
Fischer Moseley d450221ed8 tests: fix test_config_export 2024-10-08 11:42:10 -06:00
Fischer Moseley 9d2ec45689 uart: add stall_interval parameter and tests 2024-10-08 11:42:10 -06:00
Fischer Moseley 1c1c514a39 logic_analyzer: only set triggers if extra info provided in config 2024-10-08 11:42:10 -06:00
Fischer Moseley 0cb58c169e logic_analyzer: add set_triggers method, simplify trigger validation 2024-10-08 11:42:10 -06:00
Fischer Moseley cf62dd07bb logic_analyzer: default to immediate instead of single-shot, add intelligence to to_config() 2024-10-08 11:42:10 -06:00
Fischer Moseley 586cdb9817 docs: wordsmithing 2024-10-08 11:42:10 -06:00
Fischer Moseley 6b426306be doc: reference use cases/examples in index.md 2024-10-08 11:42:10 -06:00
Fischer Moseley 9153270adc meta: formatting 2024-10-08 11:42:10 -06:00
Fischer Moseley 2b4d8b56ec docs: update Ethernet Interface 2024-10-08 11:42:10 -06:00
Fischer Moseley 3148aa0055 docs: update UART Interface 2024-10-08 11:42:10 -06:00
Fischer Moseley b83cb0b0a2 docs: update layout and references for LogicAnalyzerCore docs 2024-10-08 11:42:10 -06:00
Fischer Moseley b4ef5502c1 docs: update memory_core 2024-10-08 11:42:10 -06:00
Fischer Moseley 2c124200da docs: autogenerate Python API docs, update IO core docs 2024-10-08 11:42:10 -06:00
Fischer Moseley 4adda3639a docs: document amaranth-based flow 2024-10-08 11:42:10 -06:00
Fischer Moseley 0806deeb97 ethernet: move LiteEth core connections from Signals to IOPorts 2024-10-08 11:42:10 -06:00
Fischer Moseley 9f2dffb069 examples: make verilog/amaranth versions of uart_logic_analyzer match 2024-10-08 11:42:10 -06:00
Fischer Moseley 1e7d4e92e7 tests: fix bug where base_addr was not passed but not used 2024-10-08 11:42:10 -06:00
Fischer Moseley 1b6127eb70 meta: fix circular imports 2024-10-08 11:42:10 -06:00
Fischer Moseley c38e6b5b40 docs: condense a few pages 2024-10-08 11:42:10 -06:00
Fischer Moseley daedb91ff2 meta: sort imports with ruff 2024-10-08 11:42:10 -06:00
Fischer Moseley b1caec9c57 meta: switch from black to ruff 2024-10-08 11:42:10 -06:00
Fischer Moseley ecfbdaa86b cli: remove JSON loader, add test for instantiation generation 2024-10-08 11:42:10 -06:00
Fischer Moseley fa80a49145 deps: load liteeth from PyPI 2024-10-08 11:42:10 -06:00
Fischer Moseley b31a655d58 tests: include building examples in test suite 2024-10-08 11:42:10 -06:00
Fischer Moseley 6eae490061 formatting 2024-10-08 11:42:10 -06:00
Fischer Moseley 8f45546b5a manta: fix code generation from config file, update tests 2024-10-08 11:42:10 -06:00
Fischer Moseley 3ba93efd2f meta: expose Amaranth API via __all__ 2024-10-08 11:42:10 -06:00
Fischer Moseley 0d15abe4d1 ethernet: update __init__ away from config dict 2024-10-08 11:42:10 -06:00
Fischer Moseley 0bdfd9a5f7 tests: fix mem_core_hw 2024-10-08 11:42:10 -06:00
Fischer Moseley 165c6e46ca tests: fix logic_analyzer_sim 2024-10-08 11:42:10 -06:00
Fischer Moseley 55884a11df ci: check formatting with black 2024-10-08 11:42:10 -06:00
Fischer Moseley a01b6981e2 tests: refactor to use Amaranth-native API 2024-10-08 11:42:10 -06:00
Fischer Moseley b20d7c7822 logic analyzer: move __init__ away from config dict 2024-10-08 11:42:10 -06:00
Fischer Moseley 743f434652 meta: add boilerplate for Amaranth-native API 2024-10-08 11:42:10 -06:00
Fischer Moseley d582dc24c8 uart: update length checking to accomodate extra newlines 2024-10-08 11:42:10 -06:00
Fischer Moseley ed2dfd141b add newline every 32 read requests 2024-10-08 11:42:10 -06:00
Fischer Moseley 080af6c5ee logic_analyzer: find nearest integer timestep in VCD export 2024-10-07 13:39:39 -06:00
Fischer Moseley 49e8d340ba logic_analyzer: obtain clock frequency in capture_vcd from self 2024-10-07 13:39:39 -06:00
Carlos Azevedo ebcb11fdba VCD time step is calculated from the frequency of the clock provided to Manta. The value changes are also timed accurately, instead of expressed in 10 ns intervals always. 2024-10-07 13:39:39 -06:00
Fischer Moseley 929312181e ci: clone entire repo when building docs 2024-10-06 13:11:32 -06:00