luke
/
manta
mirror of https://github.com/fischermoseley/manta.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

examples: fix typos

This commit is contained in:
Fischer Moseley 2024-11-07 09:50:55 -07:00
parent 599384ecc2
commit 9ac3181502
4 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
examples/amaranth/uart_io_core.py
View File

@ -13,7 +13,7 @@ class UARTIOCoreExample(Elaboratable):
# Create Manta instance
self.manta = Manta()
# Configure it to communicate over Ethernet
# Configure it to communicate over UART
self.manta.interface = UARTInterface(
port=port,
baudrate=2000000,

2
examples/amaranth/uart_logic_analyzer.py
View File

@ -13,7 +13,7 @@ class UARTLogicAnalyzerExample(Elaboratable):
# Create Manta instance
self.manta = Manta()
# Configure it to communicate over Ethernet
# Configure it to communicate over UART
self.manta.interface = UARTInterface(
port=port,
baudrate=2000000,

2
examples/amaranth/uart_memory_core.py
View File

@ -11,7 +11,7 @@ class UARTMemoryCoreExample(Elaboratable):
# Create Manta instance
self.manta = Manta()
# Configure it to communicate over Ethernet
# Configure it to communicate over UART
self.manta.interface = UARTInterface(
port=port,
baudrate=2000000,

4
examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml
View File

@ -31,6 +31,6 @@ ethernet:
refclk_freq: 50e6
clk_freq: 50e6
fpga_ip_addr: "192.168.0.110"
host_ip_addr: "192.168.0.100"
fpga_ip_addr: "10.0.0.2"
host_ip_addr: "10.0.0.1"
udp_port: 2000