logic_analyzer: add and use clock_freq property

src/manta/ethernet/__init__.py

@@ -150,6 +150,10 @@ class EthernetInterface(Elaboratable):
         """
         return [io[2] for io in self._phy_io]
 
+    @property
+    def clock_freq(self):
+        return self._clk_freq
+
     def _binarize_ip_addr(self, ip_addr):
         octets = [bin(int(o))[2:].zfill(8) for o in ip_addr.split(".")]
         return int("".join(octets), 2)

src/manta/logic_analyzer/__init__.py

@@ -292,7 +292,7 @@ class LogicAnalyzerCore(MantaCore):
         self._fsm.stop_capture()
 
         print(" -> Setting triggers...")
-        self._trig_blk.set_triggers(self.triggers)
+        self._trig_blk.set_triggers(self._triggers)
 
         print(" -> Setting trigger mode...")
         self._fsm.write_register("trigger_mode", self._trigger_mode)

src/manta/logic_analyzer/capture.py

@@ -104,7 +104,7 @@ class LogicAnalyzerCapture:
         """
 
         # Compute the timescale from the frequency of the provided clock
-        half_period = 1 / (2 * self._interface._clock_freq)
+        half_period = 1 / (2 * self._interface.clock_freq)
         exponent = math.floor(math.log10(half_period))
         exponent_eng = (exponent // 3) * 3
 

src/manta/uart/__init__.py

@@ -189,6 +189,10 @@ class UARTInterface(Elaboratable):
         """
         return [self.rx, self.tx]
 
+    @property
+    def clock_freq(self):
+        return self._clock_freq
+
     def read(self, addrs):
         """
         Read the data stored in a set of address on Manta's internal memory.