Create trigger blocks only for defined triggers.
Adds YAML option 'trigger_pruned' support for the logic analyser to prevent the creation of trigger blocks for probes not listed as triggers. This pruning allows much higher fmax for the designs.
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@ -1,7 +1,7 @@
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from amaranth import *
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from manta.logic_analyzer.capture import LogicAnalyzerCapture
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from manta.logic_analyzer.fsm import LogicAnalyzerFSM, TriggerModes
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from manta.logic_analyzer.fsm import LogicAnalyzerFSM, TriggerModes, TriggerPrune
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from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock
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from manta.memory_core import MemoryCore
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from manta.utils import *
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@ -39,6 +39,7 @@ class LogicAnalyzerCore(MantaCore):
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self._trigger_location = sample_depth // 2
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self._trigger_mode = TriggerModes.IMMEDIATE
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self._triggers = []
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self._trigger_pruned = TriggerPrune.FALSE
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# Bus Input/Output
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self.bus_i = Signal(InternalBus())
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@ -58,6 +59,7 @@ class LogicAnalyzerCore(MantaCore):
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"type": "logic_analyzer",
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"sample_depth": self._sample_depth,
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"probes": {p.name: len(p) for p in self._probes},
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"trigger_pruned": self._trigger_pruned,
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}
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if self._trigger_mode == TriggerModes.INCREMENTAL:
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@ -81,6 +83,7 @@ class LogicAnalyzerCore(MantaCore):
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"triggers",
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"trigger_location",
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"trigger_mode",
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"trigger_pruned",
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]
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for option in config:
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if option not in valid_options:
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@ -116,12 +119,13 @@ class LogicAnalyzerCore(MantaCore):
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core = cls(sample_depth, probes)
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# If any trigger-related configuration was provided, set the triggers with it
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keys = ["trigger_mode", "triggers", "trigger_location"]
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keys = ["trigger_mode", "triggers", "trigger_location", "trigger_pruned"]
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if any([key in config for key in keys]):
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core.set_triggers(
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trigger_mode=config.get("trigger_mode"),
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triggers=triggers,
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trigger_location=config.get("trigger_location"),
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trigger_pruned=config.get("trigger_pruned"),
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)
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return core
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@ -137,6 +141,7 @@ class LogicAnalyzerCore(MantaCore):
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probes=self._probes,
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base_addr=self._fsm.max_addr + 1,
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interface=self.interface,
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trig_names=[n[0] for n in self._triggers] if self._trigger_pruned else None,
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)
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self._sample_mem = MemoryCore(
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@ -215,7 +220,7 @@ class LogicAnalyzerCore(MantaCore):
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else:
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raise ValueError(f"Unable to interpret trigger condition '{trigger}'.")
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def set_triggers(self, trigger_mode=None, triggers=None, trigger_location=None):
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def set_triggers(self, trigger_mode=None, triggers=None, trigger_location=None, trigger_pruned=None):
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"""
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Args:
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trigger_mode (TriggerMode | str):
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@ -223,6 +228,8 @@ class LogicAnalyzerCore(MantaCore):
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triggers (Optional[Sequence[Sequence[str | int]]]):
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trigger_location (Optional[int]):
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trigger_pruned (Optional[TriggerPrune]):
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"""
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# Obtain trigger mode
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if isinstance(trigger_mode, TriggerModes):
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@ -234,6 +241,11 @@ class LogicAnalyzerCore(MantaCore):
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else:
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raise ValueError(f"Unrecognized trigger mode {trigger_mode} provided.")
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# Obtain trigger pruning
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if not isinstance(trigger_pruned, bool) and (trigger_pruned != None):
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raise ValueError(f"Unrecognized trigger pruning {trigger_pruned} provided.")
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self._trigger_pruned = trigger_pruned or TriggerPrune.FALSE
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# Peform checks based on trigger mode
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if mode == TriggerModes.IMMEDIATE:
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# Warn on triggers
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@ -275,7 +287,7 @@ class LogicAnalyzerCore(MantaCore):
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# Validate triggers
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self._validate_triggers(triggers)
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self.trigger_mode = mode
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self._trigger_mode = mode
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self._triggers = triggers
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self._trigger_location = trigger_location or self._sample_depth // 2
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@ -1,5 +1,5 @@
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from amaranth import *
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from amaranth.lib.enum import IntEnum
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from amaranth.lib.enum import IntEnum, Flag
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from manta.io_core import IOCore
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@ -18,6 +18,11 @@ class TriggerModes(IntEnum):
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IMMEDIATE = 2
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class TriggerPrune(Flag):
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TRUE = True
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FALSE = False
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class LogicAnalyzerFSM(Elaboratable):
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"""
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A module containing the state machine for a LogicAnalyzerCore. Primarily
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@ -12,10 +12,14 @@ class LogicAnalyzerTriggerBlock(Elaboratable):
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the triggers to be reprogrammed without reflashing the FPGA.
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"""
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def __init__(self, probes, base_addr, interface):
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def __init__(self, probes, base_addr, interface, trig_names):
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# Instantiate a bunch of trigger blocks
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self._trig_names = trig_names
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self._probes = probes
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self._triggers = [LogicAnalyzerTrigger(p) for p in self._probes]
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if trig_names is None:
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self._triggers = [LogicAnalyzerTrigger(p) for p in self._probes]
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else:
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self._triggers = [LogicAnalyzerTrigger(p) for p in self._probes if p.name in trig_names]
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# Make IO core for everything
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ops = [t.op for t in self._triggers]
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@ -37,9 +41,14 @@ class LogicAnalyzerTriggerBlock(Elaboratable):
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def set_triggers(self, triggers):
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# Reset all triggers to disabled with no argument
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for p in self._probes:
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self.registers.set_probe(p.name + "_op", Operations.DISABLE)
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self.registers.set_probe(p.name + "_arg", 0)
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if self._trig_names is None:
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for p in self._probes:
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self.registers.set_probe(p.name + "_op", Operations.DISABLE)
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self.registers.set_probe(p.name + "_arg", 0)
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else:
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for n in self._trig_names:
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self.registers.set_probe(n + "_op", Operations.DISABLE)
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self.registers.set_probe(n + "_arg", 0)
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# Set triggers
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for trigger in triggers:
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