Promote the unsigned values to long to get a good comparison and on a
machine where an unsigned is the same size as a long (32 bit) assert
that the unsigned values are constrained to fit into a long. It's unlikely
the values needed to create invalid results would ever happen, but this
patch makes sure it doesn't go undetected.
This is caused by a bug in some simple pattern matching the VHDL target does to try
and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in
this case). This patch just restricts the kinds of if-statements we use this
optimisation for.
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Conflicts:
tgt-vhdl/cast.cc
tgt-vhdl/display.cc
tgt-vhdl/vhdl_syntax.cc
tgt-vhdl/vhdl_target.h
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
Conflicts:
tgt-vhdl/process.cc
tgt-vhdl/stmt.cc
tgt-vhdl/vhdl_target.h
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but we may as well get
rid of the warnings we can. It also does not recognize that an
assert(0) or assert(false) ends a routine so it complains about
no return at end of function or variables not being defined.
This patch adds code to generate process-local variables
for scopes of type IVL_SCT_BLOCK. This also handles using
the correct assignment operator (:=) for the local VHDL
variables.
The patch for pr2516774 exposed a bug which caused
always3.1.8A to fail. This patch corrects that.
The test to decide when to use a sensitivity list
rather than an explicit wait statement wasn't tight enough.
This patch is a fix for pr2516774.
The idea is to generate a local variable inside
a function whenever an argument is assigned to. The
variable has an initial value of the argument value
and is used in its place for the remainder of the
function. This patch also handles the case where the
argument is assigned to inside a while loop.
This patch generates VHDL sensitivity lists for sequential
as well as combinatorial processes which do not contain
a wait statement. Otherwise it falls back on the original
wait-on/until behaviour.
This should make the generated VHDL more acceptable to
synthesisers.
This patch generates a sensitivity list for combinatorial
VHDL processes if they don't contain a wait statement, and
a wait-on statement if they do contain another wait statement.
This should help synthesisers correctly identifier
level-sensitive latches.
In particular this improves the code generated for flip-flops
so the output can be synthesised with certain tools (e.g. Synopsis).
See the comments above draw_synthesisable_wait for more details.
Previously only the X/Z state of the label expression was
considered to be a don't care. This patch adds that
functionality to the conditional expression as well.
This patch adds support for concatenation/repetition, signals and
part and bit select of signals for casez/x expression labels.
These along with the original constants can be mixed in almost any
order. Only constant selects are currently supported.
This patch optimises away straight line sequences like:
wait for 0 ns;
wait for X ns;
to:
wait for X ns;
This tidies up the output a bit.
It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
This changes the assignment statement generator so that
each VHDL declaration "knows" which type of assignment
statement can/should be used on (i.e. signals must be
assigned with <=). This will help us catch cases when
we try to use, for example, := with signals. This occurs
in pr2362211 where we try to assign to a signal within
a function (where only := can be used).
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between
reg [0:0] a;
and
reg a;
This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
The VHDL converter erroneously treated a casez and casex exactly
the same. In reality a casez compares a 'x' value (it is not a
don't care). It also adds support for a full don't care case by
just returning True for the condition.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. This patch set covers the tgt-vhdl
directory, and was tested by Nick.
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
Martin Whitaker
Cary R
Maciej Suminski
Nick Gasson
Larry Doolittle
Stephen Williams