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OpenRAM
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4,128 Commits 4 Branches 63 Tags 78 MiB
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230 Commits

Author SHA1 Message Date
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 7195d81736 Adjust WL and GND for contacted via2 spacing. 2022-04-19 10:32:37 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 68d0a56423 Fix WL to gnd spacing for grounded wordlines. 2022-04-04 16:02:47 -07:00
mrg 111533f0b0 Move power pins to horizontal or vertical layer in all cells. 2022-03-31 16:36:19 -07:00
mrg 83e5848728 Change FreePDK and SCMOS 2rw cell to share gnd power rail. 2022-03-30 13:48:53 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg 67b51ff7f5 Move vdd pin in freepdk45 sense amp from dout 2022-03-06 12:20:54 -08:00
mrg 9b90a44d4a Move output in freepdk45 sense amp down to prevent router conflict with supply 2022-02-25 16:20:47 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg d8d8636d0f Comment out calibre in freepdk45 2021-11-22 15:54:22 -08:00
mrg 48e35588f4 Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg 779d6ad2b2 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 43bbd2e722 Fixed incorrect via2 spacing rule in tech file. 2021-11-22 11:33:27 -08:00
mrg 8f296810be Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg 5d33db0ee4 Add write driver to well connect list 2021-11-22 11:33:27 -08:00
mrg 2e846cb22f Fix regexes for cells without well taps 2021-11-22 11:33:27 -08:00
mrg acc9b2d223 Connect pwell and bulk when no tap 2021-11-22 11:33:27 -08:00
mrg 141b42dc0e Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 7d7ffe76e0 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
Hunter Nichols bd57a043d7 Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation. 2021-09-20 16:51:02 -07:00
mrg f2882782e7 Use calibre by default until klayout LVS is clean. 2021-09-20 11:05:49 -07:00
mrg 10753a0802 Change via2 to 65nm to be compatible with Calibre FreePDK45 deck 2021-09-16 15:42:02 -07:00
mrg 0a91bd01c8 Fix DRC and LVS scripts 2021-09-16 15:37:26 -07:00
mrg 8081bea708 Shrink 70nm contacts to 65nm 2021-09-16 15:28:39 -07:00
mrg c5f372c264 Fix via2 to match incorrect FreePDK45 rules 2021-09-15 11:58:31 -07:00
mrg f3d1c6edc3 klayout DRC/LVS working 2021-09-15 11:33:39 -07:00
mrg 554b3f4ca7 Initial klayout DRC/LVS options 2021-09-07 16:51:16 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols de2dae4030 Changed unit capacitance from CACTI estimation to PTM estimation. 2021-08-25 15:23:12 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
mrg c117238fa7 Initial klayout DRC/LVS options 2021-08-03 14:41:09 -07:00
Hunter Nichols 1b89533d7b Added unit r and c values with m2 minwidth incorporated to match CACTI params 2021-08-01 00:23:59 -07:00
mrg e391186581 Update klayout tech files 2021-07-28 11:42:56 -07:00
Hunter Nichols 54cbef1aff Replaced cacti tech params with already existing params. Added an existence check in design_rules. 2021-07-27 14:31:22 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols a312639ef8 Added tech params for on-resistance and load capacitances 2021-07-21 11:00:32 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
mrg 9720e5af29 Remove default array row/col multiple 2021-06-29 11:28:19 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 8ee6d3be6c Added more data for regression modules. 2021-06-21 17:21:00 -07:00
Jesse Cirimelli-Low 8346ad736e add dimension contraints to other tech files 2021-06-18 14:36:15 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols 7a60eabdfe Add more freepdk45 data from regression model. 2021-06-09 13:31:38 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00