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OpenRAM
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1,884 Commits 4 Branches 63 Tags 78 MiB
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63 Commits

Author SHA1 Message Date
mrg f5804e1cbf Flatten bitcell array for LVS symmetries. 2019-07-16 11:53:20 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
mrg 0fbfa924f7 Add other SCMOS dummy cells 2019-07-03 14:28:12 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
mrg 5c4df2410e Fix dummy row LVS issue 2019-06-14 15:06:04 -07:00
mrg 3c3456596a Add replica row with dummy cells. 2019-06-14 14:38:55 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus e071e53090 Add comments on gds units in tech files. 2019-04-30 10:13:13 -07:00
Matt Guthaus d23aa9a1bd Use local setup.tcl and flatten bitcell arrays. 2019-04-26 14:12:51 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 222b07ad7a Well contact cleanup for SCMOS TSMC 0.35 2019-04-26 10:19:11 -07:00
Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen 2019-04-26 09:17:52 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Hunter Nichols 543e0a1b9a Merge branch 'dev' into multiport_characterization 2019-02-04 23:54:16 -08:00
Matt Guthaus 3ffcf63e00 Rename LICENSE file to README for github license detection 2019-01-30 13:09:26 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus be7384c017 Remove file named LICENSE since it is in the README for the tech files 2019-01-25 15:58:49 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Matt Guthaus bfca51f734 Fix flatten work-around code to have new circuit names 2019-01-18 09:51:52 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 5d59863efc Fix p_en_bar at top level. Change default scn4m period to 10ns. 2018-11-27 14:44:55 -08:00
Matt Guthaus 58e41a998f Replace write driver with human readable sp file. 2018-11-27 11:49:08 -08:00
Matt Guthaus b5e05ee7a9 Replace write driver with human readable sp file. 2018-11-27 11:42:58 -08:00
Hunter Nichols 80bc5b49c1 Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell. 2018-11-14 11:00:37 -08:00
Hunter Nichols 8b6a28b6fd Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell. 2018-11-13 22:24:18 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections 2018-11-05 16:38:46 -08:00
Matt Guthaus 86ef618efd Update SCN4M_SUBM Magic tech file. 2018-11-05 13:31:53 -08:00
Matt Guthaus 3c5dc70ede Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd. 2018-11-05 10:59:08 -08:00
Hunter Nichols f05865b307 Fixed drc issues with replica bitline test. 2018-11-02 17:16:41 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00