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Replace write driver with human readable sp file.

This commit is contained in:
Matt Guthaus 2018-11-27 11:49:08 -08:00
parent b5e05ee7a9
commit 58e41a998f
2 changed files with 35 additions and 33 deletions
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45
technology/scn3me_subm/sp_lib/write_driver.sp vendored
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@ -2,34 +2,35 @@
.SUBCKT write_driver din bl br en vdd gnd
**** Inverter to conver Data_in to data_in_bar ******
M_1 din_bar din gnd gnd n W='1.2*1u' L=0.6u
M_2 din_bar din vdd vdd p W='2.1*1u' L=0.6u
* din_bar = inv(din)
M_1 din_bar din gnd gnd n W=1.2u L=0.6u
M_2 din_bar din vdd vdd p W=2.1u L=0.6u
**** 2input nand gate follwed by inverter to drive BL ******
M_3 din_bar_gated en net_7 gnd n W='2.1*1u' L=0.6u
M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u
M_5 din_bar_gated en vdd vdd p W='2.1*1u' L=0.6u
M_6 din_bar_gated din vdd vdd p W='2.1*1u' L=0.6u
M_7 net_1 din_bar_gated vdd vdd p W='2.1*1u' L=0.6u
M_8 net_1 din_bar_gated gnd gnd n W='1.2*1u' L=0.6u
* din_bar_gated = nand(en, din)
M_3 din_bar_gated en net_7 gnd n W=2.1u L=0.6u
M_4 net_7 din gnd gnd n W=2.1u L=0.6u
M_5 din_bar_gated en vdd vdd p W=2.1u L=0.6u
M_6 din_bar_gated din vdd vdd p W=2.1u L=0.6u
* din_bar_gated_bar = inv(din_bar_gated)
M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=2.1u L=0.6u
M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=1.2u L=0.6u
**** 2input nand gate follwed by inverter to drive BR******
M_9 din_gated en vdd vdd p W='2.1*1u' L=0.6u
M_10 din_gated en net_8 gnd n W='2.1*1u' L=0.6u
M_11 net_8 din_bar gnd gnd n W='2.1*1u' L=0.6u
M_12 din_gated din_bar vdd vdd p W='2.1*1u' L=0.6u
M_13 net_6 din_gated vdd vdd p W='2.1*1u' L=0.6u
M_14 net_6 din_gated gnd gnd n W='1.2*1u' L=0.6u
* din_gated = nand(en, din_bar)
M_9 din_gated en vdd vdd p W=2.1u L=0.6u
M_10 din_gated en net_8 gnd n W=2.1u L=0.6u
M_11 net_8 din_bar gnd gnd n W=2.1u L=0.6u
M_12 din_gated din_bar vdd vdd p W=2.1u L=0.6u
* din_gated_bar = inv(din_gated)
M_13 din_gated_bar din_gated vdd vdd p W=2.1u L=0.6u
M_14 din_gated_bar din_gated gnd gnd n W=1.2u L=0.6u
************************************************
M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u
M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u
M_17 net_5 en gnd gnd n W='3.6*1u' L=0.6u
* pull down with en enable
M_15 bl din_gated_bar net_5 gnd n W=3.6u L=0.6u
M_16 br din_bar_gated_bar net_5 gnd n W=3.6u L=0.6u
M_17 net_5 en gnd gnd n W=3.6u L=0.6u

23
technology/scn4m_subm/sp_lib/write_driver.sp vendored
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@ -2,33 +2,34 @@
.SUBCKT write_driver din bl br en vdd gnd
**** Inverter to conver Data_in to data_in_bar ******
* din_bar = inv(din)
M_1 din_bar din gnd gnd n W=0.8u L=0.4u
M_2 din_bar din vdd vdd p W=1.4u L=0.4u
**** 2input nand gate follwed by inverter to drive BL ******
* din_bar_gated = nand(en, din)
M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u
M_4 net_7 din gnd gnd n W=1.4u L=0.4u
M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u
M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u
M_7 net_1 din_bar_gated vdd vdd p W=1.4u L=0.4u
M_8 net_1 din_bar_gated gnd gnd n W=0.8u L=0.4u
* din_bar_gated_bar = inv(din_bar_gated)
M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u
M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u
**** 2input nand gate follwed by inverter to drive BR******
* din_gated = nand(en, din_bar)
M_9 din_gated en vdd vdd p W=1.4u L=0.4u
M_10 din_gated en net_8 gnd n W=1.4u L=0.4u
M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u
M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u
M_13 net_6 din_gated vdd vdd p W=1.4u L=0.4u
M_14 net_6 din_gated gnd gnd n W=0.8u L=0.4u
* din_gated_bar = inv(din_gated)
M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u
M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u
************************************************
M_15 bl net_6 net_5 gnd n W=2.4u L=0.4u
M_16 br net_1 net_5 gnd n W=2.4u L=0.4u
* pull down with en enable
M_15 bl din_gated_bar net_5 gnd n W=2.4u L=0.4u
M_16 br din_bar_gated_bar net_5 gnd n W=2.4u L=0.4u
M_17 net_5 en gnd gnd n W=2.4u L=0.4u