jsowash
3bcb79d9d5
Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value.
2019-07-24 15:01:20 -07:00
Matt Guthaus
3df8abd38c
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
Matt Guthaus
07401fc6ea
Make control bus routing offset consistent
2019-07-23 09:39:28 -07:00
jsowash
2b29e505e0
Reversed order of wmask bits in functional.py since python lists go left to right. Made # of en bits equal to num_masks.
2019-07-22 12:44:35 -07:00
jsowash
0a5461201a
Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used.
2019-07-19 14:58:37 -07:00
jsowash
45cb159d7f
Connected wmask in the spice netlist.
2019-07-19 13:17:55 -07:00
jsowash
082decba18
Temporarily made the functional tests write/read only all 0's or 1's
2019-07-18 15:26:38 -07:00
jsowash
5f37067da7
Turned write_mask_array into write_mask_and_array with flip flops from sram_base
2019-07-18 15:24:41 -07:00
Matt Guthaus
864639d96e
Remove old replica bitline.
2019-07-18 15:19:40 -07:00
jsowash
720739a192
Skipping test 22_sram_wmask_func_test and changed a typo of write_driver to write_mask
2019-07-17 11:04:17 -07:00
Hunter Nichols
9696401f34
Added graph exclusions to replica column to reduce s_en paths.
2019-07-16 23:47:34 -07:00
mrg
8ca656959b
Change direction of RBL bitline pins
2019-07-16 15:09:46 -07:00
mrg
b546ecce2c
Check 2 ports only for layout.
2019-07-16 14:11:54 -07:00
mrg
12fa36317e
Cleanup unit test. Fix s_en control bug for r-only.
2019-07-16 13:51:31 -07:00
mrg
2f55911604
Simplify column decoder placement.
2019-07-16 11:55:25 -07:00
mrg
bea07c2319
SRAM with RBL integration in array.
2019-07-16 09:04:58 -07:00
jsowash
ea2f786dcf
Redefined write_size inrecompute_sizes() to take the new word_size()
2019-07-15 14:41:26 -07:00
mrg
e550d6ff10
Port name maps between bank and replica array working.
2019-07-15 11:29:29 -07:00
mrg
2271946eef
Fix replica array pin names
2019-07-12 14:39:56 -07:00
mrg
d72691f6c2
Make mirror optional argument
2019-07-12 11:14:47 -07:00
mrg
a189b325ed
Merge remote-tracking branch 'origin/dev' into rbl_revamp
2019-07-12 11:10:07 -07:00
mrg
17d144b5b5
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
jsowash
dfa2b29b8f
Begin adding wmask netlist and spice tests.
2019-07-12 10:34:29 -07:00
mrg
043018e8ba
Functional tests working with new RBL.
2019-07-12 08:42:36 -07:00
mrg
0b13225913
Single banks working with new RBL
2019-07-11 14:47:27 -07:00
mrg
b841fd7ce3
Replica bitcell array with arbitrary RBLs working
2019-07-10 15:56:51 -07:00
mrg
9dab0be737
Single bank working with replica array.
2019-07-05 13:44:29 -07:00
mrg
b9d993c88b
Add dummy bitcell module.
...
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
2019-07-05 12:58:52 -07:00
jsowash
f29631695c
Finished merge
2019-07-05 11:43:31 -07:00
mrg
f542613d78
Correct wordline_driver enable to en, not en_bar.
2019-07-05 10:31:05 -07:00
mrg
bfe4213fce
Port address added to entire SRAM.
2019-07-05 09:44:42 -07:00
mrg
4c6556f1bc
Add port address module
2019-07-05 09:04:48 -07:00
mrg
c0f9cdbc12
Create port address module
2019-07-05 09:03:52 -07:00
mrg
dd62269e0b
Some cleanup
2019-07-05 08:18:58 -07:00
jsowash
02a0cd71ac
fixed merge conflict
2019-07-04 11:14:32 -07:00
jsowash
125112b562
Added wmask flip flop. Need work on placement still.
2019-07-04 10:34:14 -07:00
mrg
3176ae9d50
Fix pnand2 height in bank select. Unsure how it passed before.
2019-07-03 15:12:22 -07:00
Matt Guthaus
0cb86b8ba2
Exclude new precharge in graph build
2019-07-03 14:46:20 -07:00
mrg
8b0b2e2817
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
mrg
bc4a3ee2b7
New port_data module works in SCMOS
2019-07-03 13:17:12 -07:00
jsowash
474ac67af5
Added optional write_size and wmask.
2019-07-03 10:14:15 -07:00
mrg
244604fb0d
Data port module working by itself.
2019-07-02 15:35:53 -07:00
mrg
2abe859df1
Fix shared bank offset.
2019-07-01 16:29:59 -07:00
jsowash
67c6cdf3bb
Fixed error where word_size was compared to num_words and added write_size to control_logic.py
2019-07-01 15:51:40 -07:00
jsowash
242771f710
Merge branch 'dev' into add_wmask
2019-06-28 15:44:27 -07:00
jsowash
1f76afd294
Begin wmask functionality. Added wmask to verilog file and config parameters.
2019-06-28 15:43:09 -07:00
Hunter Nichols
ce7e320505
Undid change to add bitcell as input to array mod.
2019-06-25 18:26:13 -07:00
Hunter Nichols
4e08e2da87
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
Hunter Nichols
33c17ac41c
Moved manual delay chain declarations from tech files to options.
2019-06-25 15:45:02 -07:00
mrg
4523a7b9f6
Replica bitcell array working
2019-06-19 16:03:21 -07:00
jsowash
Matt Guthaus
jsowash
jsowash
jsowash
jsowash
Hunter Nichols
jsowash