OpenRAM/compiler/modules
jsowash 3bcb79d9d5 Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value. 2019-07-24 15:01:20 -07:00
..
bank.py Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
bank_select.py Fix pnand2 height in bank select. Unsure how it passed before. 2019-07-03 15:12:22 -07:00
bitcell_array.py Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
control_logic.py Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value. 2019-07-24 15:01:20 -07:00
delay_chain.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
dff_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_buf.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_buf_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_inv.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dff_inv_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
dummy_array.py Replica bitcell array working 2019-06-19 16:03:21 -07:00
hierarchical_decoder.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
hierarchical_predecode.py Fix space before comment 2019-06-14 08:43:41 -07:00
hierarchical_predecode2x4.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
hierarchical_predecode3x8.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
multibank.py Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
port_address.py Port address added to entire SRAM. 2019-07-05 09:44:42 -07:00
port_data.py Reversed order of wmask bits in functional.py since python lists go left to right. Made # of en bits equal to num_masks. 2019-07-22 12:44:35 -07:00
precharge_array.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
replica_bitcell_array.py Replica bitcell array working 2019-06-19 16:03:21 -07:00
replica_bitline.py Undid change to add bitcell as input to array mod. 2019-06-25 18:26:13 -07:00
replica_column.py Replica bitcell array working 2019-06-19 16:03:21 -07:00
sense_amp.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
sense_amp_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
single_level_column_mux_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
tri_gate.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
tri_gate_array.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
wordline_driver.py Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
write_driver.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
write_driver_array.py Reversed order of wmask bits in functional.py since python lists go left to right. Made # of en bits equal to num_masks. 2019-07-22 12:44:35 -07:00
write_mask_and_array.py Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00