mirror of https://github.com/VLSIDA/OpenRAM.git
Turned write_mask_array into write_mask_and_array with flip flops from sram_base
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parent
917a69723f
commit
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@ -14,7 +14,7 @@ from vector import vector
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from globals import OPTS
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class write_mask_array(design.design):
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class write_mask_and_array(design.design):
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"""
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Array of tristate drivers to write to the bitlines through the column mux.
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Dynamically generated write driver array of all bitlines.
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@ -40,7 +40,7 @@ class write_mask_array(design.design):
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_write_mask_array()
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# self.create_write_mask_array()
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self.create_and2_array()
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@ -67,7 +67,7 @@ class write_mask_array(design.design):
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def add_modules(self):
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self.wmask = factory.create(module_type="dff_buf")
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self.add_mod(self.wmask)
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#self.add_mod(self.wmask)
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dff_height = self.wmask.height
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self.and2 = factory.create(module_type="pand2",
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@ -76,17 +76,17 @@ class write_mask_array(design.design):
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self.add_mod(self.and2)
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def create_write_mask_array(self):
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self.wmask_insts = {}
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for bit in range(self.num_wmask):
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name = "write_mask_{}".format(bit)
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self.wmask_insts[bit] = self.add_inst(name=name,
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mod=self.wmask)
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self.connect_inst(["wmask_{}".format(bit),
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"bank_wmask_{}".format(bit),
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"bank_wmask_bar_{}".format(bit),
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"clk", "vdd", "gnd"])
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# def create_write_mask_array(self):
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# self.wmask_insts = {}
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# for bit in range(self.num_wmask):
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# name = "write_mask_{}".format(bit)
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# self.wmask_insts[bit] = self.add_inst(name=name,
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# mod=self.wmask)
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#
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# self.connect_inst(["wmask_{}".format(bit),
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# "bank_wmask_{}".format(bit),
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# "bank_wmask_bar_{}".format(bit),
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# "clk", "vdd", "gnd"])
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def create_and2_array(self):
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self.and2_insts = {}
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