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OpenRAM
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1637 Commits

Author SHA1 Message Date
Matt Guthaus e750ef22f5 Undo some control logic changes. 2019-07-26 21:41:27 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus 7eea63116f Control logic LVS clean 2019-07-26 15:50:10 -07:00
Matt Guthaus dce852d945 Restructure control logic for improved drive and timing. 2019-07-26 14:54:55 -07:00
Matt Guthaus 3327fa58c0 Add some signal names to functional test comments 2019-07-26 14:49:53 -07:00
Matt Guthaus 8ebc568e8b Minor cleanup. Skip more tests until analytical fixed. 2019-07-26 08:33:06 -07:00
Matt Guthaus 20d9c30a64 Use non-analytical models for now 2019-07-25 14:55:42 -07:00
Matt Guthaus 88c399bc6c Skip prune test for now 2019-07-25 14:49:11 -07:00
Matt Guthaus d5419f99f6 Skip model tests for now 2019-07-25 14:46:33 -07:00
Matt Guthaus c8c4d05bba Fix some regression fails. 2019-07-25 14:18:08 -07:00
Matt Guthaus 0bb41b8a5d Fix duplicate paths for timing checks 2019-07-25 13:25:58 -07:00
jsowash de485182bc Cleaned up comments about wmask. 2019-07-25 13:21:17 -07:00
jsowash 61ba23706c Removed comments for rw pen() and added a wmask func test. 2019-07-25 12:24:27 -07:00
Matt Guthaus 80df996720 Modify control logic for new RBL. 2019-07-25 11:19:16 -07:00
Matt Guthaus 5452ed69e7 Always have a precharge. 2019-07-25 10:31:39 -07:00
Matt Guthaus 54b312eaf9 Add return type 2019-07-24 17:00:38 -07:00
Matt Guthaus 2f03c594c5 Remove success initialization 2019-07-24 16:59:19 -07:00
Matt Guthaus cfc04064af Remove print. 2019-07-24 16:57:57 -07:00
Matt Guthaus fb60b51c72 Add check bits. Clean up logic. Move read/write bit check to next cycle. 2019-07-24 16:57:04 -07:00
jsowash c8bbee884b Removed layout related rw port's special pen. 2019-07-24 16:01:12 -07:00
jsowash 3bcb79d9d5 Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value. 2019-07-24 15:01:20 -07:00
Matt Guthaus fe0db68965 Refactor to share get_measurement_variant 2019-07-24 11:29:29 -07:00
Matt Guthaus 9cb96bda7d Mostly formatting. Added write measurements. 2019-07-24 10:57:33 -07:00
Matt Guthaus 3df8abd38c Clean up. Split class into own file. 2019-07-24 08:15:10 -07:00
jsowash 01493aab3e Added wmask valuesto functional test through add_wmask() 2019-07-23 15:58:54 -07:00
Matt Guthaus 07401fc6ea Make control bus routing offset consistent 2019-07-23 09:39:28 -07:00
jsowash ddf5148fa5 Removed code where if there was no write mask, word_size=write_size. Now it stays None. 2019-07-22 14:58:43 -07:00
jsowash ad0af54a9f Removed dupliction of addr_size. 2019-07-22 13:18:52 -07:00
jsowash 2b29e505e0 Reversed order of wmask bits in functional.py since python lists go left to right. Made # of en bits equal to num_masks. 2019-07-22 12:44:35 -07:00
jsowash 72e16f8fe6 Added ability to do partial writes to addresses that have already been written to. 2019-07-22 11:19:14 -07:00
jsowash a69d35b50a Removed write_size from parameters. 2019-07-21 15:53:05 -07:00
jsowash 0a5461201a Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
jsowash 45cb159d7f Connected wmask in the spice netlist. 2019-07-19 13:17:55 -07:00
jsowash 082decba18 Temporarily made the functional tests write/read only all 0's or 1's 2019-07-18 15:26:38 -07:00
jsowash 5f37067da7 Turned write_mask_array into write_mask_and_array with flip flops from sram_base 2019-07-18 15:24:41 -07:00
Matt Guthaus 864639d96e Remove old replica bitline. 2019-07-18 15:19:40 -07:00
Matt Guthaus a707c6fa50 Convert psram tests to only 2 port. 2019-07-18 14:49:54 -07:00
jsowash 917a69723f Fixed typo 2019-07-17 12:26:05 -07:00
jsowash 720739a192 Skipping test 22_sram_wmask_func_test and changed a typo of write_driver to write_mask 2019-07-17 11:04:17 -07:00
Hunter Nichols 9696401f34 Added graph exclusions to replica column to reduce s_en paths. 2019-07-16 23:47:34 -07:00
mrg e2602dd79b Add comments for pins. Fix noconn in dummy pbitcell. 2019-07-16 17:30:31 -07:00
mrg 37fcf3bf37 Move classes to individual file. 2019-07-16 15:18:04 -07:00
mrg 8ca656959b Change direction of RBL bitline pins 2019-07-16 15:09:46 -07:00
mrg b546ecce2c Check 2 ports only for layout. 2019-07-16 14:11:54 -07:00
mrg 12fa36317e Cleanup unit test. Fix s_en control bug for r-only. 2019-07-16 13:51:31 -07:00
mrg 2f55911604 Simplify column decoder placement. 2019-07-16 11:55:25 -07:00
mrg 70ee026fcf Add cell names to psingle_bank test 2019-07-16 11:54:57 -07:00
mrg 42ad0cd282 Add pbitcell RW test 2019-07-16 11:54:39 -07:00
mrg bea07c2319 SRAM with RBL integration in array. 2019-07-16 09:04:58 -07:00
mrg 37c15937e2 Add multiple control logic port types. 2019-07-15 17:07:50 -07:00