mirror of https://github.com/VLSIDA/OpenRAM.git
Added ability to do partial writes to addresses that have already been written to.
This commit is contained in:
jsowash
parent
a69d35b50a
commit
72e16f8fe6
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@ -42,7 +42,7 @@ class functional(simulation):
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#self.set_feasible_period(sram, spfile, corner)
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self.set_stimulus_variables()
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self.create_signal_names()
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self.initilize_wmask()
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self.initialize_wmask()
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# Number of checks can be changed
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self.num_cycles = 2
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@ -50,16 +50,13 @@ class functional(simulation):
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self.write_check = []
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self.read_check = []
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def initilize_wmask(self):
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self.wmask = [None]*self.num_wmasks
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def initialize_wmask(self):
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#self.wmask = [None]*self.num_wmasks
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self.wmask = ""
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if self.write_size is not None:
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# initialize wmask to 1
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# initialize all wmask bits to 1
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for bit in range(self.num_wmasks):
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self.wmask[bit] = 1
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# if bit == 0:
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# self.wmask[self.num_wmask-1 - bit] = 1
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# else:
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# self.wmask[self.num_wmask-1 - bit] = 0
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self.wmask += "1"
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def run(self, feasible_period=None):
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if feasible_period: #period defaults to tech.py feasible period otherwise.
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@ -80,8 +77,12 @@ class functional(simulation):
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return self.check_stim_results()
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def write_random_memory_sequence(self):
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rw_ops = ["noop", "write", "read"]
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w_ops = ["noop", "write"]
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if self.write_size is not None:
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rw_ops = ["noop", "write", "partial_write", "read"]
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w_ops = ["noop", "write", "partial_write"]
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else:
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rw_ops = ["noop", "write", "read"]
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w_ops = ["noop", "write"]
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r_ops = ["noop", "read"]
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rw_read_din_data = "0"*self.word_size
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check = 0
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@ -129,16 +130,45 @@ class functional(simulation):
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elif op == "write":
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addr = self.gen_addr()
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word = self.gen_data()
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# wmask = self.gen_wmask()
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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# comment = self.gen_cycle_comment("write", word, addr, port, wmask, self.t_current)
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comment = self.gen_cycle_comment("read", word, addr, port, self.wmask, self.t_current)
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self.add_write_one_port(comment, addr, word, port)
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self.stored_words[addr] = word
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w_addrs.append(addr)
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elif op == "partial_write":
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#write only to a word that's been written to
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addr, old_word = self.get_data()
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# rand = random.randint(0,len(w_addrs)-1)
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# addr = w_addrs[rand]
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word = self.gen_data()
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wmask = self.gen_wmask()
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new_word = word
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for bit in range(len(wmask)):
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# Remove the bits of the word that's been written to
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if wmask[bit] == "0":
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lower = bit * self.write_size
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upper = lower + self.write_size - 1
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new_word = new_word[:lower] + old_word[lower:upper+1] + new_word[upper + 1:]
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# if bit == self.num_wmask - 1:
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# new_word = new_word[0:lower] + old_word[lower:upper+1]
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# elif bit == 0:
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# new_word = old_word[lower:upper + 1] + new_word[upper + 1:self.word_size]
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# else:
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# new_word = new_word[0:lower] + old_word[lower:upper+1] + new_word[upper+1:self.word_size]
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#wmask = wmask[:index] + "1" + wmask[index + 1:]
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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comment = self.gen_cycle_comment("partial_write", word, addr, port, wmask, self.t_current)
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self.add_partial_write_one_port(comment, addr, word, wmask, port)
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self.stored_words[addr] = new_word
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w_addrs.append(addr)
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else:
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(addr,word) = random.choice(list(self.stored_words.items()))
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# cannot read from an address that is currently being written to
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@ -191,26 +221,48 @@ class functional(simulation):
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return(1, "SUCCESS")
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def gen_wmask(self):
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wmask_bits = [None]*self.num_wmasks
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# wmask_bits = [None]*self.num_wmasks
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# for bit in range(self.num_wmasks):
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# rand = random.randint(0,1)
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# wmask_bits[bit] = rand
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wmask = ""
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for bit in range(self.num_wmasks):
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rand = random.randint(0, 1)
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wmask_bits[bit] = rand
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return wmask_bits
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wmask += str(rand)
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# prevent the wmask from having all bits on
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all_zeroes = True
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all_ones = True
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for bit in range(self.num_wmasks):
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if wmask[bit]=="0":
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all_ones = False
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elif wmask[bit]=="1":
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all_zeroes = False
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if all_zeroes:
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index = random.randint(0, self.num_wmasks - 1)
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wmask = wmask[:index] + "1" + wmask[index + 1:]
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elif all_ones:
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index = random.randint(0, self.num_wmasks - 1)
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wmask = wmask[:index] + "0" + wmask[index + 1:]
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return wmask
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# prevent the wmask from having all bits off
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# def gen_data(self):
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# """ Generates a random word to write. """
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# rand = random.randint(0,(2**self.word_size)-1)
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# data_bits = self.convert_to_bin(rand,False)
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# return data_bits
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def gen_data(self):
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""" Generates a random word, either all 0 or all 1's, to write. """
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rand = random.randint(0,1)
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bits = []
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for bit in range(self.word_size):
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bits.append(rand)
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data_bits = ''.join(map(str,bits))
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""" Generates a random word to write. """
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rand = random.randint(0,(2**self.word_size)-1)
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data_bits = self.convert_to_bin(rand,False)
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return data_bits
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# def gen_data(self):
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# """ Generates a random word, either all 0 or all 1's, to write. """
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# rand = random.randint(0,1)
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# bits = []
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# for bit in range(self.word_size):
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# bits.append(rand)
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# data_bits = ''.join(map(str,bits))
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# return data_bits
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def gen_addr(self):
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""" Generates a random address value to write to. """
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@ -221,7 +273,7 @@ class functional(simulation):
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def get_data(self):
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""" Gets an available address and corresponding word. """
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# Currently unused but may need later depending on how the functional test develops
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addr = random.choice(self.stored_words.keys())
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addr = random.choice(list(self.stored_words.keys()))
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word = self.stored_words[addr]
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return (addr,word)
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@ -294,8 +346,8 @@ class functional(simulation):
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# Generate wmask bits
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for port in self.write_ports:
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self.sf.write("\n* Generation of wmask sibfssgnals\n")
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if self.write_size is not None:
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self.sf.write("\n* Generation of wmask signals\n")
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for bit in range(self.num_wmasks):
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sig_name = "WMASK{0}_{1} ".format(port, bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period,
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@ -135,7 +135,7 @@ class simulation():
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def add_wmask(self, wmask, port):
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""" Add the array of address values """
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debug.check(len(wmask) == self.num_wmask, "Invalid wmask size.")
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debug.check(len(wmask) == self.num_wmasks, "Invalid wmask size.")
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bit = self.addr_size - 1
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for c in wmask:
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@ -144,7 +144,8 @@ class simulation():
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elif c == "1":
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self.wmask_values[port][bit].append(1)
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else:
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debug.error("Non-binary address string", 1)
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print(c)
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#debug.error("Non-binary wmask string", 1)
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bit -= 1
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def add_write(self, comment, address, data, port):
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@ -208,10 +209,24 @@ class simulation():
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debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "write")
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self.add_data(data,port)
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self.add_address(address,port)
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def add_partial_write_one_port(self, comment, address, data, wmask, port):
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""" Add the control values for a write cycle (partial). Does not increment the period. """
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debug.check(port in self.write_ports,
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"Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port,
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self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "write")
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self.add_data(data, port)
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self.add_address(address, port)
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#self.add_wmask(wmask,port)
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def add_read_one_port(self, comment, address, din_data, port):
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""" Add the control values for a read cycle. Does not increment the period. """
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@ -249,22 +264,20 @@ class simulation():
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t_current,
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t_current+self.period)
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elif op == "write":
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if self.write_size is not None:
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comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
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addr,
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wmask,
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port,
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int(t_current / self.period),
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t_current,
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t_current + self.period)
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else:
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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elif op == "partial_write":
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comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
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addr,
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wmask,
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port,
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int(t_current / self.period),
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t_current,
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t_current + self.period)
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else:
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comment = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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