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Removed layout related rw port's special pen.

This commit is contained in:
jsowash 2019-07-24 16:01:12 -07:00
parent 3bcb79d9d5
commit c8bbee884b
1 changed files with 17 additions and 17 deletions
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34
compiler/modules/control_logic.py
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@ -647,11 +647,11 @@ class control_logic(design.design):
x_off = self.control_x_offset
(y_off,mirror)=self.get_offset(row)
if self.port_type == "rw":
offset = vector(x_off, y_off)
self.pre_p_en_inst.place(offset, mirror)
x_off += self.and2.width
# if self.port_type == "rw":
# offset = vector(x_off, y_off)
# self.pre_p_en_inst.place(offset, mirror)
#
# x_off += self.and2.width
offset = vector(x_off,y_off)
self.p_en_bar_inst.place(offset, mirror)
@ -659,18 +659,18 @@ class control_logic(design.design):
self.row_end_inst.append(self.p_en_bar_inst)
def route_pen(self):
if self.port_type == "rw":
# Connect the NAND gate inputs to the bus
pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"])
self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets)
out_pos = self.pre_p_en_inst.get_pin("Z").center()
in_pos = self.p_en_bar_inst.get_pin("A").lc()
mid1 = vector(out_pos.x,in_pos.y)
self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos])
else:
in_map = zip(["A"], ["gated_clk_buf"])
self.connect_vertical_bus(in_map, self.p_en_bar_inst, self.rail_offsets)
# if self.port_type == "rw":
# # Connect the NAND gate inputs to the bus
# pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"])
# self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets)
#
# out_pos = self.pre_p_en_inst.get_pin("Z").center()
# in_pos = self.p_en_bar_inst.get_pin("A").lc()
# mid1 = vector(out_pos.x,in_pos.y)
# self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos])
# else:
in_map = zip(["A"], ["gated_clk_buf"])
self.connect_vertical_bus(in_map, self.p_en_bar_inst, self.rail_offsets)
self.connect_output(self.p_en_bar_inst, "Z", "p_en_bar")