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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 08:27:11 +02:00
Fix some regression fails.
This commit is contained in:
Matt Guthaus
@@ -393,7 +393,7 @@ class replica_bitcell_array(design.design):
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = parameter["rbl_height_percentage"]
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bl_swing = OPTS.rbl_delay_percentage
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freq = spice["default_event_rate"]
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bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
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@@ -451,4 +451,4 @@ class replica_bitcell_array(design.design):
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def get_cell_name(self, inst_name, row, col):
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"""Gets the spice name of the target bitcell."""
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return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col)
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return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col)
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@@ -61,28 +61,27 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl': [0.2121267],
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'delay_lh': [0.2121267],
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'leakage_power': 0.0023761999999999998,
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'min_period': 0.43,
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'read0_power': [0.5139368],
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'read1_power': [0.48940979999999995],
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'slew_hl': [0.0516745],
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'slew_lh': [0.0516745],
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'write0_power': [0.46267169999999996],
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'write1_power': [0.4670826]}
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golden_data = {'delay_hl': [0.2192123],
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'delay_lh': [0.2192123],
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'leakage_power': 0.006427800000000001,
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'min_period': 0.527,
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'read0_power': [0.4519997],
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'read1_power': [0.42609269999999994],
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'slew_hl': [0.10185999999999999],
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'slew_lh': [0.10185999999999999],
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'write0_power': [0.49744869999999997],
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'write1_power': [0.4460337]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.288],
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'delay_lh': [1.288],
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'leakage_power': 0.0273896,
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'min_period': 2.578,
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'read0_power': [16.9996],
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'read1_power': [16.2616],
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'slew_hl': [0.47891700000000004],
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'slew_lh': [0.47891700000000004],
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'write0_power': [16.0656],
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'write1_power': [16.2616]}
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golden_data = {'delay_hl': [1.4249],
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'delay_lh': [1.4249],
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'leakage_power': 0.7340832,
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'min_period': 3.125,
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'read0_power': [14.8099],
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'read1_power': [14.0866],
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'slew_hl': [0.7280485],
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'slew_lh': [0.7280485],
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'write0_power': [16.865],
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'write1_power': [14.8288]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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@@ -15,8 +15,9 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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class model_delay_sram_test(openram_test):
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class model_delay_test(openram_test):
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""" Compare the accuracy of the analytical model with a spice simulation. """
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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OPTS.analytical_delay = False
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@@ -61,9 +62,9 @@ class model_delay_sram_test(openram_test):
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debug.info(1,"Spice Delays={}".format(spice_delays))
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debug.info(1,"Model Delays={}".format(model_delays))
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if OPTS.tech_name == "freepdk45":
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error_tolerance = .25
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error_tolerance = 0.25
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elif OPTS.tech_name == "scn4m_subm":
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error_tolerance = .25
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error_tolerance = 0.25
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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@@ -54,28 +54,27 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl': [0.2108836],
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'delay_lh': [0.2108836],
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'leakage_power': 0.001564799,
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'min_period': 0.508,
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'read0_power': [0.43916689999999997],
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'read1_power': [0.4198608],
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'slew_hl': [0.0455126],
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'slew_lh': [0.0455126],
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'write0_power': [0.40681890000000004],
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'write1_power': [0.4198608]}
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golden_data = {'delay_hl': [0.2265453],
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'delay_lh': [0.2265453],
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'leakage_power': 0.003688569,
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'min_period': 0.547,
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'read0_power': [0.4418831],
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'read1_power': [0.41914969999999996],
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'slew_hl': [0.103665],
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'slew_lh': [0.103665],
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'write0_power': [0.48889660000000007],
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'write1_power': [0.4419755]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.5747600000000002],
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'delay_lh': [1.5747600000000002],
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'leakage_power': 0.00195795,
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'min_period': 3.281,
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'read0_power': [14.92874],
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'read1_power': [14.369810000000001],
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'slew_hl': [0.49631959999999997],
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'slew_lh': [0.49631959999999997],
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'write0_power': [13.79953],
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'write1_power': [14.369810000000001]}
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golden_data = {'delay_hl': [1.718183],
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'delay_lh': [1.718183],
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'leakage_power': 0.1342958,
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'min_period': 3.75,
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'read0_power': [14.1499],
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'read1_power': [13.639719999999999],
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'slew_hl': [0.7794919],
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'slew_lh': [0.7794919],
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'write0_power': [15.978829999999999],
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'write1_power': [14.128079999999999]}
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else:
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self.assertTrue(False) # other techs fail
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