mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports.		2020-08-13 14:29:10 -07:00
..
sram.py	fix: generated pex file was not passed correctly to lib characterizer	2020-08-03 10:16:12 +02:00
sram_1bank.py	Don't obstruct control logic signals with dffs when no column mux.	2020-07-29 10:31:18 -07:00
sram_2bank.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
sram_base.py	Fix up to SRAM level with new replica bitcell array ports.	2020-08-13 14:29:10 -07:00
sram_config.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00