mrg f55b57033d Route col decoder address with data bits in channel

2020-12-15 16:37:23 -08:00

..

sram_1bank.py

Route col decoder address with data bits in channel

2020-12-15 16:37:23 -08:00

sram_2bank.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

sram_base.py

Only run DRC and LVS at SRAM level if not a unit test to reduce run time.

2020-12-15 10:46:55 -08:00

sram_config.py

Refactor dynamic cell name to utilize base class

2020-11-03 13:18:46 -08:00

sram.py

Merged with dev

2020-11-10 15:47:56 -08:00