luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,920 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

3346 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low fbe3032246 add case for single spare col spare_wen_dff i/o 2022-05-26 12:18:47 -07:00
mrg 1bab395946 Merge branch 'sky130_fixes' into dev 2022-05-24 09:12:37 -07:00
mrg cb3d7b9d5d Add spares for sky130 unit tests. 2022-05-23 17:27:26 -07:00
mrg b84b4dab43 Fail on pin mismatch too. 2022-05-23 16:28:28 -07:00
mrg 8c85230033 Remove experimental power option. 2022-05-23 10:08:35 -07:00
mrg 51b0f125fb Add offset to 0,0 that was inadvertantly removed for router debug. 2022-05-23 09:59:41 -07:00
mrg 735d66c9f1 Start dff array supplies on first rather than second bit. 2022-05-17 15:54:54 -07:00
mrg 3e02a0e7df Update column decoder and dff array supplies 2022-05-17 15:49:50 -07:00
mrg c8905c410a Fix case where distance is zero length comparison 2022-05-17 15:49:06 -07:00
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg 8217a84165 Uniquify overlap points during segment overlap computation. 2022-05-17 13:31:23 -07:00
mrg 9b592ab432 Fix missing hash recompute in vector class. 2022-05-17 13:30:41 -07:00
mrg bed12d2a9e pbitcell vdd/gnd are on layer m1 only. 2022-05-16 17:02:53 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 4be075e586 Overlap length can include a rectangle overlap. 2022-05-16 14:57:32 -07:00
mrg 3101643964 Check for no pins and fix closest pin return type 2022-05-13 14:34:26 -07:00
mrg 74c2c5ae0e Don't double prefix a name 2022-05-13 14:32:52 -07:00
mrg fbb2ea5fb6 Intersection now returns a pin_layout fixed during LEF computation. 2022-05-13 13:56:16 -07:00
mrg 4345136d1a Fix offsets for local bitcell arrays. 2022-05-13 10:46:00 -07:00
mrg 357f967a93 Leave supply routing to new helper functions. 2022-05-11 11:01:14 -07:00
mrg 8f2d787d53 Add min area metal in preferred direction 2022-05-11 10:50:32 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg 50045e54e8 Fix a couple supply routing issues. 2022-05-03 11:45:51 -07:00
mrg f8f3f16b1f Move delay line supply strap for pin access. 2022-05-02 16:42:14 -07:00
mrg 942ab89754 Remove debug output. 2022-05-02 16:42:04 -07:00
mrg 3e48991acb Skip partial pins if they are too small to prevent DRC overlap errors. 2022-05-02 16:07:05 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 23b5655cab Split replica_bitcell_array test 2022-03-23 15:59:29 -07:00
mrg 9f7426052d Split port_address tests 2022-03-23 14:46:41 -07:00
mrg e31bec131c Remove 1rw1r combined test and add separate tests. 2022-03-22 11:59:04 -07:00
mrg a8f50f212e Change track spacing for freepdk45 2022-03-18 16:01:57 -07:00
mrg 2bfc94fcdd Add unblocking of source and destination pins to router. 2022-03-18 14:44:13 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg 4567c2ebcd Add space after docker command. Regress to klayout v0.27.4 2022-03-10 08:37:48 -08:00
mrg e16defdae4 Add a sleep to see if problem is async one 2022-03-09 10:24:50 -08:00
mrg b841e18abd Remove breakpoint 2022-03-07 16:59:55 -08:00
mrg 2796800898 Fix bug with incorrect pitch while adding channel route trunks. 2022-03-07 16:12:20 -08:00
mrg 772fbd6f96 Remove extra well tap to save area. 2022-03-07 15:38:25 -08:00
mrg f17d661e3a Add spare column option to tests for sky130 2022-03-07 07:58:41 -08:00
mrg 4faf97005f Add even columns for sky130 to ring test 2022-03-06 12:21:09 -08:00
mrg 6eeb81b9fe Skip sky130 23_lib tests and 4096 row hierarchical decoder test 2022-03-06 11:27:13 -08:00
mrg a0f1327f5e Add odd rows to 23_lib tests 2022-03-06 11:26:18 -08:00
mrg 6da3e44b6f Split up 06_hierarchical_decoder test 2022-03-06 11:26:03 -08:00
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00