 mrg
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cd66ddb37c
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Add supply rails to dff array. PEP8 cleanup.
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2020-04-21 15:21:29 -07:00 |
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mrg
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5f76514cf0
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Remove end of line whitespace
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2020-04-21 15:20:51 -07:00 |
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mrg
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ab91d0ab1d
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Add purpose to string output
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2020-04-21 15:20:30 -07:00 |
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mrg
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f6135f3471
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PEP8 formatting
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2020-04-20 16:38:30 -07:00 |
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mrg
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dfbf6fe45c
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Default is to use preferred layer directions
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2020-04-20 15:33:53 -07:00 |
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mrg
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8c177f9947
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Split col mux test
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2020-04-20 15:03:32 -07:00 |
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mrg
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7995451cbb
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PEP8 formatting
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2020-04-20 14:45:18 -07:00 |
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mrg
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69d0e5e372
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Split port data test into single and multi-port.
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2020-04-20 14:26:44 -07:00 |
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mrg
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7f65176908
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Configured bitline directions into prot_data
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2020-04-20 14:23:40 -07:00 |
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mrg
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cbb67ad483
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Update to run LVS when no DRC errors too.
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2020-04-17 13:57:52 -07:00 |
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mrg
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f1925420cf
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Only allow DRC fail with LVS pass if using Magic.
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2020-04-17 10:30:26 -07:00 |
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mrg
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75fce9894c
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Allow LVS to run even if DRC fails.
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2020-04-17 09:35:07 -07:00 |
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mrg
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8ece411954
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Merge branch 'dev' into tech_migration
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2020-04-16 11:32:02 -07:00 |
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mrg
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843e9414df
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Parameterize vdd and gnd pin in write driver array.
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2020-04-16 11:28:35 -07:00 |
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mrg
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770533e7b1
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Parameterize vdd and gnd pin in sense amp array.
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2020-04-16 11:27:26 -07:00 |
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mrg
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d1319d633d
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Don't widen too short wires either
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2020-04-16 11:02:54 -07:00 |
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mrg
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b347e3f7a8
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Try both layers for reversed layer stacks.
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2020-04-15 16:49:04 -07:00 |
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mrg
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9d2902de9e
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Conditional well spacing
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2020-04-15 15:55:49 -07:00 |
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mrg
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94eb2afa36
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Change to callable DRC rule. Use bottom coordinate for bus offsets.
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2020-04-15 15:29:55 -07:00 |
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mrg
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e95c97d7a5
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PEP8 cleanup
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2020-04-15 14:29:43 -07:00 |
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mrg
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1564d6e02b
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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mrg
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43fe1ae023
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Improve pitch computation
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2020-04-15 11:16:45 -07:00 |
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mrg
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331a4f4606
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Fix wire width bug in short jogs. PEP8 cleanup.
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2020-04-15 09:48:42 -07:00 |
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mrg
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0941ebc3da
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Fix well spacing issue
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2020-04-14 14:08:07 -07:00 |
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mrg
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32d190b8b1
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Jog connection on M1 for bank select.
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2020-04-14 12:15:56 -07:00 |
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mrg
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43dcf675a1
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Move pnand outputs to M1. Debug hierarchical decoder multirow.
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2020-04-14 10:52:25 -07:00 |
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mrg
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2e67d44cd7
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First pass of multiple bitcells per decoder row
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2020-04-10 13:29:41 -07:00 |
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mrg
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7888e54fc4
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Remove dynamic bitcell multiple detection.
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
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2020-04-09 11:38:18 -07:00 |
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mrg
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8a55c223df
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Use single height for netlist_only mode
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2020-04-09 09:48:54 -07:00 |
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mrg
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58fbc5351a
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Change rows to outputs in hierarchical decoder
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2020-04-08 17:05:16 -07:00 |
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mrg
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745450fadc
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Syntax error
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2020-04-08 17:04:50 -07:00 |
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|
mrg
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cddfaa0dc8
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Tech dependent fudge factor
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2020-04-08 17:04:14 -07:00 |
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mrg
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ade3b78711
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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mrg
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0c27942bb2
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Dynamically try and DRC decoder for height
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2020-04-08 16:45:28 -07:00 |
|
 Hunter Nichols
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4103745de2
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Merged with dev, fixed conflict in ptx
|
2020-04-08 02:33:05 -07:00 |
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Hunter Nichols
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95363856e4
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Added logical effort and input load for ptx module.
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2020-04-08 02:29:57 -07:00 |
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mrg
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7872b6a68c
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Merge branch 'dev' into tech_migration
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2020-04-07 10:42:05 -07:00 |
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mrg
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a3797094d0
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Swap lvs and sp dimensions for s8
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2020-04-07 10:37:49 -07:00 |
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mrg
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c8c74e8b69
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Fix lvs_write in sram class
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2020-04-06 15:20:59 -07:00 |
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mrg
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f20246abdc
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-04-06 14:08:45 -07:00 |
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mrg
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cd8dc8e20b
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Output lvs model instead of spice model
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2020-04-06 14:08:38 -07:00 |
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mrg
|
a12b5d9e6c
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Split decoder pbitcell tests
|
2020-04-06 13:31:31 -07:00 |
|
 Jesse Cirimelli-Low
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b59c789dec
|
remove whitespace
|
2020-04-05 03:58:26 -07:00 |
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|
Jesse Cirimelli-Low
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beef9441b7
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fix pin check debug typo
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2020-04-05 02:55:15 -07:00 |
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|
Jesse Cirimelli-Low
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8b33cb519f
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Merge branch 'dev' into custom_mod
|
2020-04-03 17:05:56 -07:00 |
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mrg
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ab5dd47182
|
Ptx is in microns if lvs_lib exists
|
2020-04-03 14:06:56 -07:00 |
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mrg
|
f358de78bb
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Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
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2020-04-03 13:39:54 -07:00 |
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mrg
|
8603d3edd6
|
PEP8 cleanup
|
2020-04-03 11:37:06 -07:00 |
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|
mrg
|
2850b9efb5
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Don't force check in lib characterization. PEP8 formatting.
|
2020-04-02 12:52:42 -07:00 |
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|
mrg
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f105c9ab36
|
Netlist only in verilog test
|
2020-04-02 12:43:19 -07:00 |
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