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OpenRAM
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4,968 Commits 5 Branches 63 Tags 79 MiB
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81 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low c3987f2537 change power ring spacing from magic numbers to drc based 2026-05-07 14:18:58 -07:00
Jesse Cirimelli-Low c7f3ac33cd sky130 cypress dp working with offset relative to crba 2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission 2026-01-14 12:08:26 -08:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
Jesse Cirimelli-Low d7c3bbea3e crba passing again norbl/leftrbl 2023-10-28 18:05:07 -07:00
Jesse Cirimelli-Low 2faa067ea6 add support for col offset to rbc; fix rba mirroring 2023-09-12 12:12:21 -07:00
Jesse Cirimelli-Low 036cc54b99 rba done w/o wordline 2023-08-24 02:55:45 -07:00
Jesse Cirimelli-Low 450f8ab0c3 replica col generating, funny dummy cell placement 2023-08-22 00:45:57 -07:00
Jesse Cirimelli-Low be72bcfa01 trim bitcells and fix replica column excluding 2023-08-10 00:34:16 -07:00
Jesse Cirimelli-Low 1aa04db2b6 add isntance naming templates 2023-08-03 16:24:24 -07:00
Jesse Cirimelli-Low 5e01bad2ee remove whitespace 2023-08-03 00:42:42 -07:00
Jesse Cirimelli-Low 61cfa55d75 fix replica col 2023-08-02 15:19:48 -07:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
samuelkcrow 8bc3903a04 remove end caps from replica column (will not pass sky130 drc) 2022-09-26 14:23:09 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg f7e3672c89 Route horizontal supplies in write driver. 2022-03-01 14:37:51 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
Hunter Nichols 16e658726e When determining bitline names, added a technology check for sky130. 2021-06-16 17:04:02 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg da48b8d98c Fix replica column bit index 2020-12-14 14:18:39 -08:00
mrg 718c327527 Fix iteration bug with new type 2020-11-20 17:33:15 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 620e271562 Fix various typos and errors 2020-11-13 16:04:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
jcirimel 05667d784f move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
mrg c3d6be27be Fix argument name bug for remove wordlines 2020-10-08 16:58:38 -07:00
mrg 01fe02bd90 Fixes to replica bitline array. 
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
 2020-10-08 14:53:44 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
mrg c2629edc1b Allow 16-way column mux 2020-10-06 16:27:02 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00