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OpenRAM
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4,785 Commits 5 Branches 63 Tags 79 MiB
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1168 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low ba51149dce placement working for sp capped rba, need fix rowcap patterns 2023-08-26 18:54:07 -07:00
Jesse Cirimelli-Low 036cc54b99 rba done w/o wordline 2023-08-24 02:55:45 -07:00
Jesse Cirimelli-Low 450f8ab0c3 replica col generating, funny dummy cell placement 2023-08-22 00:45:57 -07:00
Jesse Cirimelli-Low f890160601 add nwell routing in bca 2023-08-21 20:12:36 -07:00
Jesse Cirimelli-Low 5a6c78865d singleport bitcell array laying out 2023-08-21 19:24:06 -07:00
Jesse Cirimelli-Low 9ac894e2ef update bitcell array trimming 2023-08-15 11:30:16 -07:00
Jesse Cirimelli-Low e4c15d33c4 Merge branch 'singleport_refactor' of github.com:VLSIDA/PrivateRAM into singleport_refactor 2023-08-14 18:53:22 -07:00
Sam Crow cd1b0f973d Revert pin/net spice object work 
This reverts commits 01116 6e3e9 2ced8 c67fd 2b9e7 bfabe 09aa3 5907c aa717 478c7 45b88 d0339 e15fe 7581d c8c43 146ef
 2023-08-14 18:44:51 -07:00
Jesse Cirimelli-Low 0391bf6593 add dummy mirroring for sky130 dp 2023-08-14 14:25:57 -07:00
Jesse Cirimelli-Low 30ee5a0a2e add dummy cell mirroring for sky130 2023-08-14 14:19:58 -07:00
Jesse Cirimelli-Low 74c12f944f mirror skywater dp 2023-08-14 13:59:31 -07:00
Jesse Cirimelli-Low e23289d5ae merge in dev 2023-08-10 17:04:45 -07:00
Jesse Cirimelli-Low be72bcfa01 trim bitcells and fix replica column excluding 2023-08-10 00:34:16 -07:00
Jesse Cirimelli-Low 1aa04db2b6 add isntance naming templates 2023-08-03 16:24:24 -07:00
Jesse Cirimelli-Low 5e01bad2ee remove whitespace 2023-08-03 00:42:42 -07:00
Eren Dogan f8b2c1e9b9 Change OPTS.route_supplies option since there's only one router now 2023-08-02 21:48:29 -07:00
Eren Dogan 54fc34392d Remove unnecessary imports 2023-08-02 21:28:21 -07:00
Eren Dogan 87eca6b7db Use the initial bbox to route supply and signals 2023-08-02 18:01:09 -07:00
Jesse Cirimelli-Low 61cfa55d75 fix replica col 2023-08-02 15:19:48 -07:00
Eren Dogan 5b0f97860a Calculate bbox inside the router 2023-08-02 09:30:50 -07:00
Eren Dogan 877f20e071 Use the new routers in ROMs 2023-08-01 19:10:02 -07:00
Jesse Cirimelli-Low 5a764c9d43 remove MY mirroring in scmos 2023-08-01 19:05:55 -07:00
Eren Dogan dd152da5c2 Change signal escape router's high-level function name 2023-08-01 11:26:25 -07:00
Eren Dogan 993b47be4c Remove old routers from sram_1bank 2023-08-01 11:22:50 -07:00
Eren Dogan db2a276077 Split graph router class to use it for signal escaping later 2023-07-31 19:43:09 -07:00
Jesse Cirimelli-Low d9d8cb2983 capped norbl scmos passing 2023-07-30 22:39:23 -07:00
Jesse Cirimelli-Low 6b12d442fa placement fixed 2023-07-30 22:01:30 -07:00
Jesse Cirimelli-Low 811eb43459 working on updated placemet code 2023-07-30 20:06:40 -07:00
Jesse Cirimelli-Low c1acdadd81 remove print statements 2023-07-29 17:39:27 -07:00
Jesse Cirimelli-Low 6f9618f28a fix 2023-07-28 21:46:07 -07:00
Jesse Cirimelli-Low 8d8f243f99 scmos passing with odd sizses again 2023-07-27 18:39:18 -07:00
Jesse Cirimelli-Low a6e07aa364 cleanup 2023-07-26 18:53:39 -07:00
Jesse Cirimelli-Low dde4103d49 scmos pass 2023-07-26 18:40:37 -07:00
Jesse Cirimelli-Low 8a4b34dee1 proper tiling 2023-07-26 18:05:36 -07:00
Jesse Cirimelli-Low 4baec81f82 lvs failures 2023-07-26 02:51:31 -07:00
Jesse Cirimelli-Low 3fe44a3751 scmos array placing 2023-07-26 01:28:50 -07:00
Eren Dogan 54ce1377c5 Merge branch 'dev' into gridless_router 2023-07-25 20:03:59 -07:00
Jesse Cirimelli-Low 4cf3ea91ff scmos array connecting 2023-07-25 15:02:06 -07:00
Jesse Cirimelli-Low cb21443e2d start of pattern refactor 2023-07-24 23:25:35 -07:00
Eren Dogan 5de7b9cda7 Make graph router the default supply router 2023-07-24 13:07:43 -07:00
Sam Crow 09aa395174 cast pins dict to list 2023-07-18 16:13:29 -07:00
Eren Dogan 53d00f5b34 Merge branch 'dev' into gridless_router 2023-07-18 10:00:00 -07:00
Eren Dogan 5ef964d01f Merge branch 'dev' into gridless_router 2023-07-18 09:31:20 -07:00
Eren Dogan 094e71764a Change option name for the gridless router 2023-07-13 12:16:58 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 468c972acb add optional guard band to delay chain sizing 2023-07-05 16:34:42 -07:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow b4a9784835 model vth delay swing delay 2023-07-05 12:17:48 -07:00
Sam Crow 5235cf9667 model p_en and wl_en delays in delay chain sizing 2023-07-03 17:02:11 -07:00
Sam Crow e1865083d7 incomplete work on improved delay modeling 2023-06-29 14:44:42 -07:00