mirror of https://github.com/VLSIDA/OpenRAM.git
start of pattern refactor
This commit is contained in:
Jesse Cirimelli-Low
parent
7bd312faff
commit
cb21443e2d
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@ -476,6 +476,13 @@ class layout():
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# debug.info(4, "instance list: " + ",".join(x.name for x in self.insts))
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return self.insts[-1]
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def add_existing_inst(self, inst):
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self.mods.add(inst.mod)
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self.inst_names.add(self.name)
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self.insts.append(inst)
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debug.info(3, "adding existing instance{}".format(self.insts[-1]))
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return self.insts[-1]
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def get_inst(self, name):
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""" Retrieve an instance by name """
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for inst in self.insts:
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@ -10,7 +10,8 @@ from openram.tech import drc, spice
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from openram.sram_factory import factory
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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from .pattern import pattern
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from openram.base import geometry, instance
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class bitcell_array(bitcell_base_array):
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"""
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@ -42,7 +43,7 @@ class bitcell_array(bitcell_base_array):
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def create_layout(self):
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self.place_array("bit_r{0}_c{1}")
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self.place_array()
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self.add_layout_pins()
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@ -56,19 +57,29 @@ class bitcell_array(bitcell_base_array):
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""" Add the modules used in this design """
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self.cell = factory.create(module_type=OPTS.bitcell)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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# def create_instances(self):
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# """ Create the module instances used in this design """
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# self.cell_inst = {}
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# for col in range(self.column_size):
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# for row in range(self.row_size):
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# name = "bit_r{0}_c{1}".format(row, col)
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# self.cell_inst[row, col]=self.add_inst(name=name,
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# mod=self.cell)
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# self.connect_inst(self.get_bitcell_pins(row, col))
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#
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# # If it is a "core" cell, it could be trimmed for sim time
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# if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
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# self.trim_insts.add(name)
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# If it is a "core" cell, it could be trimmed for sim time
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if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
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self.trim_insts.add(name)
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def create_instances(self):
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self.cell_inst={}
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core_block = [[0 for x in range(2)] for y in range(2)]
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core_block[0][0] = geometry.instance("core_0_0", mod=self.cell)
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core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, mirror="MX")
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core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, mirror="MY")
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core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, mirror="XY")
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self.pattern = pattern(self, "bitcell_array", core_block, self.row_size/2, self.column_size/2)
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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@ -6,10 +6,11 @@
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# All rights reserved.
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#
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from openram import debug
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from openram.base.geometry import instance
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from openram.base import design
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from openram.sram_factory import factory
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from openram import OPTS
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from openram.modules import pattern
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class bitcell_base_array(design):
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"""
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@ -184,32 +185,35 @@ class bitcell_base_array(design):
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dir_x = True
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return (tempy, dir_x)
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def place_array(self, name_template, row_offset=0):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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# def place_array(self, name_template: str, row_offset=0):
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# # We increase it by a well enclosure so the precharges don't overlap our wells
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# self.height = self.row_size * self.cell.height
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# self.width = self.column_size * self.cell.width
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#
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# xoffset = 0.0
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# for col in range(self.column_size):
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# yoffset = 0.0
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# tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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#
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# for row in range(self.row_size):
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# tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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#
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# if dir_x and dir_y:
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# dir_key = "XY"
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# elif dir_x:
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# dir_key = "MX"
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# elif dir_y:
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# dir_key = "MY"
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# else:
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# dir_key = ""
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#
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# self.cell_inst[row, col].place(offset=[tempx, tempy],
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# mirror=dir_key)
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# yoffset += self.cell.height
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# xoffset += self.cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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def place_array(self):
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self.pattern.place_array()
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def get_column_offsets(self):
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"""
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@ -0,0 +1,129 @@
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from openram import debug
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from openram.base.geometry import instance,geometry
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from typing import List
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from typing import Optional
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from openram.base import design
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from openram.globals import OPTS
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class pattern():
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"""
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This class is used to desribe the internals of a bitcell array. It describes
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instance modules, rotation, and ordering
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"""
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block = List[List[instance]]
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def __init__(self,
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parent_design: design,
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name:str,
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core_block:block,
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num_core_x:int,
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num_core_y:int,
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cores_per_x_block: int = 1,
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cores_per_y_block: int = 1,
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x_block: Optional[block] = None,
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y_block: Optional[block] = None,
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xy_block: Optional[block] = None,
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initial_x_block:bool = False,
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initial_y_block:bool = False,
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final_x_block:bool = False,
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final_y_block:bool = False
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):
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"""
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a "block" is a 2d list of instances
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core_block defines the main block that is tiled
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num_core defines the number of times the core block is to be tiled
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(i.e. bitcells in dimension / bitcells in core_block)
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x_block defines a block that is inserted to the right of the core_block
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y_block defines a block that is inserted below the core block
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xy_block defines a block that is a inserted where the x_block and y_block intercept
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the initial and final booleans determine whether the pattern begins and/or ends with x/y blocks
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"""
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self.parent_design = parent_design
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self.name = name
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self.core_block = core_block
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self.x_block = x_block
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self.y_block = y_block
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self.xy_block = xy_block
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self.cores_per_x_block = cores_per_x_block
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self.cores_per_y_block = cores_per_y_block
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self.initial_x_block = initial_x_block
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self.initial_y_block = initial_y_block
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self.final_x_block = final_x_block
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self.final_y_block = final_y_block
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if not OPTS.netlist_only:
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self.verify_interblock_dimensions()
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def compute_and_verify_intrablock_dimensions(self, block: block) -> List[int]:
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for row in block:
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row_height = row[0].height
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for inst in row:
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debug.check(row_height == inst.height, "intrablock instances within the same row are different heights")
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for y in range(len(block[0])):
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debug.check(all([row[y].width for row in block]), "intrablock instances within the same column are different widths")
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block_width = sum([instance.width for instance in block[0]])
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block_height = sum([row[0].height for row in block])
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return [block_width, block_height]
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def verify_interblock_dimensions(self) -> None:
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"""
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Ensure the individual blocks are valid and interblock dimensions are valid
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"""
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debug.check(len(self.core_block) >= 1, "invalid core_block dimension: core_block rows must be >=1")
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debug.check(len(self.core_block[0]) >= 1, "invalid core_block dimension: core_block cols must be >=1")
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if self.x_block and self.y_block:
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debug.check(self.xy_block is not None, "must have xy_block if both x_block and y_block are provided")
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(self.core_block_width, self.core_block_height) = self.compute_and_verify_intrablock_dimensions(self.core_block)
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if self.x_block:
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(self.x_block_width, self.x_block_height) = self.compute_and_verify_intrablock_dimensions(self.x_block)
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if self.y_block:
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(self.y_block_width, self.y_block_height) = self.compute_and_verify_intrablock_dimensions(self.y_block)
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if self.xy_block:
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(self.xy_block_width, self.xy_block_height) = self.compute_and_verify_intrablock_dimensions(self.xy_block)
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if(self.x_block):
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debug.check(self.core_block_width * self.cores_per_x_block == self.x_block_width, "core_block does not align with x_block")
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if(self.y_block):
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debug.check(self.core_block_height * self.cores_per_y_block == self.y_block_height, "core_block does not aligns with y_block")
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if(self.xy_block):
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debug.check(self.xy_block_height == self.x_block_height, "xy_block does not align with x_block")
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debug.check(self.xy_block_width == self.y_block_width, "xy_block does not align with y_block")
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def place_block(self, block: block, x: float, y: float, x_count: int, y_count: int) -> None:
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return
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def connect_block(self, block: block, x: int, y: int) -> None:
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for dy in range(len(block)):
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for dx in range(len(block[0])):
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inst = block[dy][dx]
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print(inst.name)
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self.parent_design.cell_inst[x + dx, y + dy] = self.parent_design.add_existing_inst(inst)
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self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(x+dx, y+dy))
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def connect_array(self) -> None:
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x = 0
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y = 0
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self.connect_block(self.core_block, x,y)
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def place_array(self) -> None:
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array_x = 0
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array_y = 0
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# if(self.initial_x_block and self.initial_y_block):
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# self.place_block(array, self.xy_block, array_x, array_y)
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# array_x += self.xy_block_width
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# if(self.initial_x_block):
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# self.place_block(array, self.xy_block, array_x, array_y)
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# array_x += self.x_block_width
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self.connect_array()
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self.place_block(self.core_block, array_x, array_y, 0, 0)
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def connect_pins(self, array: design) -> None:
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array.connect_isnt()
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