Merge branch 'dev' into gridless_router

Makefile

@@ -3,6 +3,9 @@ include $(TOP_DIR)/openram.mk
 
 .DEFAULT_GOAL := install
 
+# Set the shell here
+SHELL := /bin/bash
+
 # Skywater PDK SRAM library
 SRAM_LIB_DIR ?= $(PDK_ROOT)/sky130_fd_bd_sram
 # Use this for release

README.md

@@ -4,6 +4,7 @@
 [![Python 3.5](https://img.shields.io/badge/Python-3.5-green.svg)](https://www.python.org/)
 [![License: BSD 3-clause](https://raw.githubusercontent.com/VLSIDA/OpenRAM/stable/images/license_badge.svg)](./LICENSE)
 [![PyPI - Downloads](https://img.shields.io/pypi/dm/openram?color=brightgreen&label=PyPI)](https://pypi.org/project/openram/)
+[![Open In Colab](https://colab.research.google.com/assets/colab-badge.svg)](https://githubtocolab.com/sfmth/openram-playground/blob/main/OpenRAM.ipynb)
 
 An open-source static random access memory (SRAM) compiler.
 
@@ -56,13 +57,13 @@ OpenRAM is licensed under the [BSD 3-Clause License](./LICENSE).
 # Publications
 
 + [M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016.](https://escholarship.org/content/qt8x19c778/qt8x19c778_noSplash_b2b3fbbb57f1269f86d0de77865b0691.pdf)
-+ [S. Ataei, J. Stine, M. Guthaus, “A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS,” International Conference on Computer Design (ICCD), 2016, pp. 499-506.](https://escholarship.org/uc/item/99f6q9c9)
-+ [E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE International Symposium on Circuits and Systems (ISCAS), 2017.](https://escholarship.org/content/qt7nn0j5x3/qt7nn0j5x3_noSplash_172457455e1aceba20694c3d7aa489b4.pdf)
-+ [B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization",  IEEE International Symposium on Circuits and Systems (ISCAS), 2019.](https://escholarship.org/content/qt98s4c1hp/qt98s4c1hp_noSplash_753dcc3e218f60aafff98ef77fb56384.pdf)
-+ [B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://ieeexplore.ieee.org/document/8920325)
-+ [H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://escholarship.org/content/qt7047n3k0/qt7047n3k0.pdf?t=q4gcij)
-+ [H. Nichols, "Statistical Modeling of SRAMs", M.S. Thesis, UCSC, 2022.](https://escholarship.org/content/qt7vx9n089/qt7vx9n089_noSplash_cfc4ba479d8eb1b6ec25d7c92357bc18.pdf?t=ra9wzr)
-+ [M. Guthaus, H. Nichols, J. Cirimelli-Low, J. Kunzler, B. Wu, "Enabling Design Technology Co-Optimization of SRAMs though Open-Source Software", IEEE International Electron Devices Meeting (IEDM), 2020.](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9372047)
++ [S. Ataei, J. Stine, M. Guthaus, "A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS," International Conference on Computer Design (ICCD), 2016, pp. 499-506.](https://escholarship.org/uc/item/99f6q9c9)
++ [E. Ebrahimi, M. Guthaus, J. Renau, "Timing Speculative SRAM," IEEE International Symposium on Circuits and Systems (ISCAS), 2017.](https://escholarship.org/content/qt7nn0j5x3/qt7nn0j5x3_noSplash_172457455e1aceba20694c3d7aa489b4.pdf)
++ [B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization,"  IEEE International Symposium on Circuits and Systems (ISCAS), 2019.](https://escholarship.org/content/qt98s4c1hp/qt98s4c1hp_noSplash_753dcc3e218f60aafff98ef77fb56384.pdf)
++ [B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://ieeexplore.ieee.org/document/8920325)
++ [H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://escholarship.org/content/qt7047n3k0/qt7047n3k0.pdf?t=q4gcij)
++ [M. Guthaus, H. Nichols, J. Cirimelli-Low, J. Kunzler, B. Wu, "Enabling Design Technology Co-Optimization of SRAMs though Open-Source Software," IEEE International Electron Devices Meeting (IEDM), 2020.](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9372047)
++ [H. Nichols, "Statistical Modeling of SRAMs," M.S. Thesis, UCSC, 2022.](https://escholarship.org/content/qt7vx9n089/qt7vx9n089_noSplash_cfc4ba479d8eb1b6ec25d7c92357bc18.pdf?t=ra9wzr)
 
 
  

VERSION

@@ -1 +1 @@
-1.2.11
+1.2.16

__init__.py

@@ -22,17 +22,22 @@ if "OPENRAM_HOME" not in os.environ.keys():
 __path__.insert(0, OPENRAM_HOME)
 
 
-# Find the conda installation directory
+# Find the conda installer script
 if os.path.exists(OPENRAM_HOME + "/install_conda.sh"):
+    CONDA_INSTALLER = OPENRAM_HOME + "/install_conda.sh"
     CONDA_HOME = OPENRAM_HOME + "/miniconda"
 elif os.path.exists(OPENRAM_HOME + "/../install_conda.sh"):
+    CONDA_INSTALLER = OPENRAM_HOME + "/../install_conda.sh"
     CONDA_HOME = os.path.abspath(OPENRAM_HOME + "/../miniconda")
-# Add CONDA_HOME to environment variables
+# Override CONDA_HOME if it's set as an environment variable
+if "CONDA_HOME" in os.environ.keys():
+    CONDA_HOME = os.environ["CONDA_HOME"]
+# Add CONDA_HOME to environment variables just in case
 try:
     os.environ["CONDA_HOME"] = CONDA_HOME
 except:
     from openram import debug
-    debug.warning("Couldn't find install_conda.sh")
+    debug.warning("Couldn't find conda setup directory.")
 
 
 # Import everything in globals.py

compiler/base/__init__.py

@@ -16,6 +16,7 @@ from .lef import *
 from .logical_effort import *
 from .pin_layout import *
 from .power_data import *
+from .rom_verilog import *
 from .route import *
 from .timing_graph import *
 from .utils import *

compiler/base/rom_verilog.py

@@ -0,0 +1,173 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import math
+from openram.tech import spice
+
+
+class rom_verilog:
+    """
+    Create a behavioral Verilog file for simulation.
+    This is inherited by the rom_base class.
+    """
+    def __init__(self):
+        pass
+
+    def verilog_write(self, verilog_name):
+        """ Write a behavioral Verilog model. """
+        self.vf = open(verilog_name, "w")
+
+        self.vf.write("// OpenROM ROM model\n")
+
+        #basic info
+        self.vf.write("// Words: {0}\n".format(self.num_words))
+        self.vf.write("// Word size: {0}\n".format(self.word_size))
+        self.vf.write("// Word per Row: {0}\n".format(self.words_per_row))
+        self.vf.write("// Data Type: {0}\n".format(self.data_type))
+        self.vf.write("// Data File: {0}\n".format(self.rom_data))
+
+        self.vf.write("\n")
+
+        try:
+            self.vdd_name = spice["power"]
+        except KeyError:
+            self.vdd_name = "vdd"
+        try:
+            self.gnd_name = spice["ground"]
+        except KeyError:
+            self.gnd_name = "gnd"
+
+        #add multiple banks later
+        self.vf.write("module {0}(\n".format(self.name))
+        self.vf.write("`ifdef USE_POWER_PINS\n")
+        self.vf.write("    {},\n".format(self.vdd_name))
+        self.vf.write("    {},\n".format(self.gnd_name))
+        self.vf.write("`endif\n")
+
+        for port in self.all_ports:
+            if port in self.read_ports:
+                self.vf.write("// Port {0}: R\n".format(port))
+                self.vf.write("    clk{0},csb{0},addr{0},dout{0}".format(port))
+            # Continue for every port on a new line
+            if port != self.all_ports[-1]:
+                self.vf.write(",\n")
+        self.vf.write("\n  );\n\n")
+
+        self.vf.write("  parameter DATA_WIDTH = {0} ;\n".format(self.word_size))
+        self.vf.write("  parameter ADDR_WIDTH = {0} ;\n".format(math.ceil(math.log(self.num_words,2))))
+        self.vf.write("  parameter ROM_DEPTH = 1 << ADDR_WIDTH;\n")
+        self.vf.write("  // FIXME: This delay is arbitrary.\n")
+        self.vf.write("  parameter DELAY = 3 ;\n")
+        self.vf.write("  parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n")
+        self.vf.write("  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n")
+        self.vf.write("\n")
+
+        self.vf.write("`ifdef USE_POWER_PINS\n")
+        self.vf.write("    inout {};\n".format(self.vdd_name))
+        self.vf.write("    inout {};\n".format(self.gnd_name))
+        self.vf.write("`endif\n")
+
+        for port in self.all_ports:
+            self.add_inputs_outputs(port)
+
+        self.vf.write("\n")
+
+        # This is the memory array itself
+        self.vf.write("  reg [DATA_WIDTH-1:0]    mem [0:ROM_DEPTH-1];\n\n")
+
+        #write memory init here
+        self.vf.write(f"  initial begin\n")
+        if self.data_type == "bin":
+            self.vf.write(f"    $readmemb(\"{self.rom_data}\",mem,0,ROM_DEPTH-1);\n")
+        elif self.data_type == "hex":
+            self.vf.write(f"    $readmemh(\"{self.rom_data}\",mem,0, ROM_DEPTH-1);\n")
+        else:
+            raise ValueError(f"Data type: {self.data_type} is not supported!")
+        self.vf.write(f"  end\n\n")
+
+        for port in self.all_ports:
+            self.register_inputs(port)
+
+        for port in self.all_ports:
+            if port in self.read_ports:
+                self.add_read_block(port)
+
+        self.vf.write("\n")
+        self.vf.write("endmodule\n")
+        self.vf.close()
+
+    def register_inputs(self, port):
+        """
+        Register the control signal, address and data inputs.
+        """
+        self.add_regs(port)
+        self.add_flops(port)
+
+    def add_regs(self, port):
+        """
+        Create the input regs for the given port.
+        """
+        self.vf.write("  reg  csb{0}_reg;\n".format(port))
+        self.vf.write("  reg [ADDR_WIDTH-1:0]  addr{0}_reg;\n".format(port))
+        if port in self.read_ports:
+            self.vf.write("  reg [DATA_WIDTH-1:0]  dout{0};\n".format(port))
+
+
+    def add_flops(self, port):
+        """
+        Add the flop behavior logic for a port.
+        """
+        self.vf.write("\n")
+        self.vf.write("  // All inputs are registers\n")
+        self.vf.write("  always @(posedge clk{0})\n".format(port))
+        self.vf.write("  begin\n")
+        self.vf.write("    csb{0}_reg = csb{0};\n".format(port))
+        self.vf.write("    addr{0}_reg = addr{0};\n".format(port))
+        if port in self.read_ports:
+            self.add_write_read_checks(port)
+
+        if port in self.read_ports:
+            self.vf.write("    #(T_HOLD) dout{0} = {1}'bx;\n".format(port, self.word_size))
+            self.vf.write("    if ( !csb{0}_reg && VERBOSE ) \n".format(port))
+            self.vf.write("      $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
+
+        self.vf.write("  end\n\n")
+
+    def add_inputs_outputs(self, port):
+        """
+        Add the module input and output declaration for a port.
+        """
+        self.vf.write("  input  clk{0}; // clock\n".format(port))
+        self.vf.write("  input   csb{0}; // active low chip select\n".format(port))
+
+        self.vf.write("  input [ADDR_WIDTH-1:0]  addr{0};\n".format(port))
+        if port in self.read_ports:
+            self.vf.write("  output [DATA_WIDTH-1:0] dout{0};\n".format(port))
+
+    def add_write_block(self, port):
+        """
+        ROM does not take writes thus this function does nothing
+        """
+        self.vf.write("\n")
+    def add_read_block(self, port):
+        """
+        Add a read port block.
+        """
+        self.vf.write("\n")
+        self.vf.write("  // Memory Read Block Port {0}\n".format(port))
+        self.vf.write("  // Read Operation : When web{0} = 1, csb{0} = 0\n".format(port))
+        self.vf.write("  always @ (negedge clk{0})\n".format(port))
+        self.vf.write("  begin : MEM_READ{0}\n".format(port))
+        self.vf.write("    if (!csb{0}_reg)\n".format(port))
+        self.vf.write("       dout{0} <= #(DELAY) mem[addr{0}_reg];\n".format(port))
+        self.vf.write("  end\n")
+
+    def add_write_read_checks(self, rport):
+        """
+        Since ROMs dont have write ports this does nothing
+        """
+        pass

compiler/characterizer/functional.py

@@ -363,7 +363,7 @@ class functional(simulation):
     def gen_addr(self):
         """ Generates a random address value to write to. """
         if self.valid_addresses:
-            random_value = random.sample(self.valid_addresses, 1)[0]
+            random_value = random.sample(list(self.valid_addresses), 1)[0]
         else:
             random_value = random.randint(0, self.max_address)
         addr_bits = binary_repr(random_value, self.bank_addr_size)

compiler/globals.py

@@ -31,26 +31,23 @@ OPTS = options.options()
 
 
 def parse_args():
-    """ Parse the optional arguments for OpenRAM """
+    """ Parse the optional arguments for OpenRAM. """
 
     global OPTS
 
     option_list = {
-        optparse.make_option("-b",
-                             "--backannotated",
+        optparse.make_option("-b", "--backannotated",
                              action="store_true",
                              dest="use_pex",
                              help="Back annotate simulation"),
-        optparse.make_option("-o",
-                             "--output",
+        optparse.make_option("-o", "--output",
                              dest="output_name",
                              help="Base output file name(s) prefix",
                              metavar="FILE"),
         optparse.make_option("-p", "--outpath",
                              dest="output_path",
                              help="Output file(s) location"),
-        optparse.make_option("-i",
-                             "--inlinecheck",
+        optparse.make_option("-i", "--inlinecheck",
                              action="store_true",
                              help="Enable inline LVS/DRC checks",
                              dest="inline_lvsdrc"),
@@ -68,36 +65,29 @@ def parse_args():
                              type="int",
                              help="Specify the number of spice simulation threads (default: 3)",
                              dest="num_sim_threads"),
-        optparse.make_option("-v",
-                             "--verbose",
+        optparse.make_option("-v", "--verbose",
                              action="count",
                              dest="verbose_level",
                              help="Increase the verbosity level"),
-        optparse.make_option("-t",
-                             "--tech",
+        optparse.make_option("-t", "--tech",
                              dest="tech_name",
                              help="Technology name"),
-        optparse.make_option("-s",
-                             "--spice",
+        optparse.make_option("-s", "--spice",
                              dest="spice_name",
                              help="Spice simulator executable name"),
-        optparse.make_option("-r",
-                             "--remove_netlist_trimming",
+        optparse.make_option("-r", "--remove_netlist_trimming",
                              action="store_false",
                              dest="trim_netlist",
                              help="Disable removal of noncritical memory cells during characterization"),
-        optparse.make_option("-c",
-                             "--characterize",
+        optparse.make_option("-c", "--characterize",
                              action="store_false",
                              dest="analytical_delay",
                              help="Perform characterization to calculate delays (default is analytical models)"),
-        optparse.make_option("-k",
-                             "--keeptemp",
+        optparse.make_option("-k", "--keeptemp",
                              action="store_true",
                              dest="keep_temp",
                              help="Keep the contents of the temp directory after a successful run"),
-        optparse.make_option("-d",
-                             "--debug",
+        optparse.make_option("-d", "--debug",
                              action="store_true",
                              dest="debug",
                              help="Run in debug mode to drop to pdb on failure")
@@ -125,7 +115,7 @@ def parse_args():
 
 
 def print_banner():
-    """ Conditionally print the banner to stdout """
+    """ Conditionally print the banner to stdout. """
     global OPTS
     if OPTS.is_unit_test:
         return
@@ -160,8 +150,7 @@ def check_versions():
     try:
         subprocess.check_output(["git", "--version"])
     except:
-        debug.error("Git is required. Please install git.")
-        sys.exit(1)
+        debug.error("Git is required. Please install git.", -1)
 
     # FIXME: Check versions of other tools here??
     # or, this could be done in each module (e.g. verify, characterizer, etc.)
@@ -226,8 +215,8 @@ def install_conda():
 
     debug.info(1, "Creating conda setup...");
 
-    from openram import CONDA_HOME
-    subprocess.call("./install_conda.sh", cwd=os.path.abspath(CONDA_HOME + "/.."))
+    from openram import CONDA_INSTALLER
+    subprocess.call(CONDA_INSTALLER)
 
 
 def setup_bitcell():
@@ -280,18 +269,17 @@ def get_tool(tool_type, preferences, default_name=None):
                         2)
         else:
             debug.info(1, "Using {0}: {1}".format(tool_type, exe_name))
-            return(default_name, exe_name)
+            return (default_name, exe_name)
     else:
         for name in preferences:
             exe_name = find_exe(name)
             if exe_name != None:
                 debug.info(1, "Using {0}: {1}".format(tool_type, exe_name))
-                return(name, exe_name)
+                return (name, exe_name)
             else:
-                debug.info(1,
-                           "Could not find {0}, trying next {1} tool.".format(name, tool_type))
+                debug.info(1, "Could not find {0}, trying next {1} tool.".format(name, tool_type))
         else:
-            return(None, "")
+            return (None, "")
 
 
 def read_config(config_file, is_unit_test=False):
@@ -381,7 +369,7 @@ def read_config(config_file, is_unit_test=False):
 
 
 def end_openram():
-    """ Clean up openram for a proper exit """
+    """ Clean up openram for a proper exit. """
     cleanup_paths()
 
     if OPTS.check_lvsdrc:
@@ -393,8 +381,7 @@ def end_openram():
 
 def purge_temp():
     """ Remove the temp directory. """
-    debug.info(1,
-               "Purging temp directory: {}".format(OPTS.openram_temp))
+    debug.info(1, "Purging temp directory: {}".format(OPTS.openram_temp))
     #import inspect
     #s = inspect.stack()
     #print("Purge {0} in dir {1}".format(s[3].filename, OPTS.openram_temp))
@@ -416,8 +403,7 @@ def cleanup_paths():
     """
     global OPTS
     if OPTS.keep_temp:
-        debug.info(0,
-                   "Preserving temp directory: {}".format(OPTS.openram_temp))
+        debug.info(0, "Preserving temp directory: {}".format(OPTS.openram_temp))
         return
     elif os.path.exists(OPTS.openram_temp):
         purge_temp()
@@ -434,7 +420,6 @@ def setup_paths():
 
     # Use a unique temp subdirectory if multithreaded
     if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp":
-
         # Make a unique subdir
         tempdir = "/openram_{0}_{1}_temp".format(getpass.getuser(),
                                                  os.getpid())
@@ -449,14 +434,15 @@ def setup_paths():
 
 def is_exe(fpath):
     """ Return true if the given is an executable file that exists. """
+
     return os.path.exists(fpath) and os.access(fpath, os.X_OK)
 
 
 def find_exe(check_exe):
     """
-    Check if the binary exists in any path dir
-    and return the full path.
+    Check if the binary exists in any path dir and return the full path.
     """
+
     # Search for conda setup if used
     if OPTS.use_conda:
         from openram import CONDA_HOME
@@ -465,6 +451,7 @@ def find_exe(check_exe):
                                              os.environ["PATH"])
     else:
         search_path = os.environ["PATH"]
+
     # Check if the preferred spice option exists in the path
     for path in search_path.split(os.pathsep):
         exe = os.path.join(path, check_exe)
@@ -475,18 +462,20 @@ def find_exe(check_exe):
 
 
 def init_paths():
-    """ Create the temp and output directory if it doesn't exist """
+    """ Create the temp and output directory if it doesn't exist. """
+
     if os.path.exists(OPTS.openram_temp):
         purge_temp()
     else:
-        # make the directory if it doesn't exist
+        # Make the directory if it doesn't exist
         try:
-            debug.info(1,
-                       "Creating temp directory: {}".format(OPTS.openram_temp))
+            debug.info(1, "Creating temp directory: {}".format(OPTS.openram_temp))
             os.makedirs(OPTS.openram_temp, 0o750)
         except OSError as e:
-            if e.errno == 17:  # errno.EEXIST
+            if e.errno == 17: # errno.EEXIST
                 os.chmod(OPTS.openram_temp, 0o750)
+            else:
+                debug.error("Unable to make temp directory: {}".format(OPTS.openram_temp), -1)
     #import inspect
     #s = inspect.stack()
     #from pprint import pprint
@@ -499,10 +488,10 @@ def init_paths():
     try:
         os.makedirs(OPTS.output_path, 0o750)
     except OSError as e:
-        if e.errno == 17:  # errno.EEXIST
+        if e.errno == 17: # errno.EEXIST
             os.chmod(OPTS.output_path, 0o750)
-    except:
-        debug.error("Unable to make output directory.", -1)
+        else:
+            debug.error("Unable to make output directory: {}".format(OPTS.output_path), -1)
 
 
 def set_default_corner():
@@ -572,7 +561,7 @@ def import_tech():
     # Add all of the paths
     for tech_path in OPENRAM_TECH.split(":"):
         debug.check(os.path.isdir(tech_path),
-                    "$OPENRAM_TECH does not exist: {0}".format(tech_path))
+                    "$OPENRAM_TECH does not exist: {}".format(tech_path))
         sys.path.append(tech_path)
         debug.info(1, "Adding technology path: {}".format(tech_path))
 
@@ -580,7 +569,7 @@ def import_tech():
     try:
         tech_mod = __import__(OPTS.tech_name)
     except ImportError:
-        debug.error("Nonexistent technology module: {0}".format(OPTS.tech_name), -1)
+        debug.error("Nonexistent technology module: {}".format(OPTS.tech_name), -1)
 
     OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/"
 
@@ -649,7 +638,7 @@ def report_status():
     total_size = OPTS.word_size*OPTS.num_words*OPTS.num_banks
     debug.print_raw("Total size: {} bits".format(total_size))
     if total_size >= 2**14 and not OPTS.analytical_delay:
-        debug.warning("Characterizing large memories ({0}) will have a large run-time. ".format(total_size))
+        debug.warning("Characterizing large memories ({0}) will have a large run-time.".format(total_size))
     debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
                                                                     OPTS.num_words,
                                                                     OPTS.num_banks))

compiler/modules/rom_bank.py

@@ -10,13 +10,14 @@ import datetime
 from math import ceil, log
 from openram.base import vector
 from openram.base import design
+from openram.base import rom_verilog
 from openram import OPTS, print_time
 from openram.sram_factory import factory
 from openram.tech import drc, layer, parameter
 from openram.router import router_tech
 
 
-class rom_bank(design):
+class rom_bank(design,rom_verilog):
 
     """
     Rom data bank with row and column decoder + control logic
@@ -509,4 +510,4 @@ class rom_bank(design):
         rtr=router(layers=self.m3_stack,
                    design=self,
                    bbox=bbox)
-        rtr.escape_route(pins_to_route)
+        rtr.escape_route(pins_to_route)

compiler/modules/sram_1bank.py

@@ -28,7 +28,6 @@ class sram_1bank(design, verilog, lef):
         design.__init__(self, name)
         lef.__init__(self, ["m1", "m2", "m3", "m4"])
         verilog.__init__(self)
-
         self.sram_config = sram_config
         sram_config.set_local_config(self)
 

compiler/options.py

@@ -58,6 +58,7 @@ class options(optparse.Values):
     ###################
     rom_endian = "little"
     rom_data = None
+    data_type = "bin"
     strap_spacing = 8
     scramble_bits = True
 

compiler/rom.py

@@ -26,7 +26,8 @@ class rom():
                                 words_per_row=OPTS.words_per_row,
                                 rom_endian=OPTS.rom_endian,
                                 scramble_bits=OPTS.scramble_bits,
-                                strap_spacing=OPTS.strap_spacing)
+                                strap_spacing=OPTS.strap_spacing,
+                                data_type=OPTS.data_type)
 
         if name is None:
             name = OPTS.output_name
@@ -38,7 +39,7 @@ class rom():
         from openram.base import design
         design.name_map=[]
 
-        debug.info(2, "create rom of size {0} with {1} num of words".format(self.word_size,
+        debug.print_raw("create rom of word size {0} with {1} num of words".format(self.word_size,
                                                                                        self.num_words))
         start_time = datetime.datetime.now()
 
@@ -137,20 +138,22 @@ class rom():
 
 
         # Write the config file
+        # Should also save the provided data file
         start_time = datetime.datetime.now()
         from shutil import copyfile
         copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
+        copyfile(self.rom_data, OPTS.output_path + self.rom_data)
         debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
         print_time("Config", datetime.datetime.now(), start_time)
 
         # TODO: Write the datasheet
 
-        # TODO: Write a verilog model
-        # start_time = datetime.datetime.now()
-        # vname = OPTS.output_path + self.r.name + '.v'
-        # debug.print_raw("Verilog: Writing to {0}".format(vname))
-        # self.verilog_write(vname)
-        # print_time("Verilog", datetime.datetime.now(), start_time)
+        #Write a verilog model
+        start_time = datetime.datetime.now()
+        vname = OPTS.output_path + self.r.name + '.v'
+        debug.print_raw("Verilog: Writing to {0}".format(vname))
+        self.verilog_write(vname)
+        print_time("Verilog", datetime.datetime.now(), start_time)
 
         # Write out options if specified
         if OPTS.output_extended_config:

compiler/rom_config.py

@@ -16,14 +16,14 @@ from openram import OPTS
 class rom_config:
     """ This is a structure that is used to hold the ROM configuration options. """
 
-    def __init__(self, word_size, rom_data, words_per_row=None, rom_endian="little", scramble_bits=True, strap_spacing=8):
+    def __init__(self, word_size, rom_data, words_per_row=None, rom_endian="little", scramble_bits=True, strap_spacing=8, data_type="hex"):
         self.word_size = word_size
         self.word_bits = self.word_size * 8
         self.rom_data = rom_data
         self.strap_spacing = strap_spacing
         # TODO: This currently does nothing. It should change the behavior of the chunk funciton.
         self.endian = rom_endian
-
+        self.data_type = data_type
         # This should pretty much always be true. If you want to make silicon art you might set to false
         self.scramble_bits = scramble_bits
         # This will get over-written when we determine the organization
@@ -57,18 +57,12 @@ class rom_config:
     def compute_sizes(self):
         """  Computes the organization of the memory using data size by trying to make it a rectangle."""
 
-        # Read data as hexidecimal text file
-        hex_file = open(self.rom_data, 'r')
-        hex_data = hex_file.read()
-
-        # Convert from hex into an int
-        data_int = int(hex_data, 16)
-        # Then from int into a right aligned, zero padded string
-        bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
-
-        # Then turn the string into a list of ints
-        bin_data = list(bin_string)
-        raw_data = [int(x) for x in bin_data]
+        if self.data_type == "hex":
+            raw_data = self.read_data_hex()
+        elif self.data_type == "bin":
+            raw_data = self.read_data_bin()
+        else:
+            debug.error(f"Invalid input data type: {self.data_type}", -1)
 
         # data size in bytes
         data_size = len(raw_data) / 8
@@ -93,6 +87,35 @@ class rom_config:
         OPTS.words_per_row = self.words_per_row
         debug.info(1, "Read rom data file: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, self.num_words, self.cols, self.rows, self.words_per_row))
 
+    def read_data_hex(self) -> List[int]:
+        # Read data as hexidecimal text file
+        with open(self.rom_data, 'r') as hex_file:
+            hex_data = hex_file.read()
+
+        # Convert from hex into an int
+        data_int = int(hex_data, 16)
+        # Then from int into a right aligned, zero padded string
+        bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
+
+        # Then turn the string into a list of ints
+        bin_data = list(bin_string)
+        raw_data = [int(x) for x in bin_data]
+        return raw_data
+
+    def read_data_bin(self) -> List[int]:
+
+        # Read data as a binary file
+        with open(self.rom_data, 'rb') as bin_file:
+            bin_data = bin_file.read()
+
+        # Convert from a list of bytes to a single string of bits
+        bin_string = "".join(f"{n:08b}" for n in bin_data)
+
+        # Then turn the string into a list of ints
+        bin_data = list(bin_string)
+        raw_data = [int(x) for x in bin_data]
+        return raw_data
+
 
     def chunk_data(self, raw_data: List[int]):
         """

docs/source/architecture.md

@@ -22,4 +22,14 @@ This page of the documentation explains the architecture of OpenRAM.
     * Write Driver(s)
     * Control Logic with Replica Bitline
 
-![OpenRAM SRAM Architecture](../assets/images/architecture/sram_architecture.png)
+![OpenRAM SRAM Architecture](../assets/images/architecture/sram_architecture.png)
+
+## ROM Architecture
+* Bit-cell Array
+    * 1T NAND Bitcell
+* Row Address Decoder
+* Wordline Driver(s)
+* Column Multiplexer
+* Column Pre-Decoder
+* Bitline Precharge(s)
+* Control Logic

docs/source/basic_rom_usage.md

@@ -0,0 +1,99 @@
+
+### [Go Back](./index.md#table-of-contents)
+
+# Basic Usage
+This page of the documentation explains the basic usage of OpenRAM's ROM compiler (OpenROM). For usage of the RAM compiler see [here](./basic_usage.md#go-back)
+
+
+
+## Table of Contents
+1. [Environment Variable Setup](#environment-variable-setup-assuming-bash)
+1. [Command Line Usage](#command-line-usage)
+1. [Script Usage](#script-usage)
+1. [Configuration Files](#configuration-files)
+1. [Common Configuration File Options](#common-configuration-file-options)
+1. [Output Files](#output-files)
+
+
+
+## Environment Variable Setup (assuming bash)
+Environment configuration is the same as described in [basic SRAM usage](./basic_usage#environment-variable-setup-assuming-bash)
+
+
+## Accepted Data formats
+OpenROM currently supports input data formatted as a binary file or a text file
+of hexadecimal-encoded data. For hexadecimal data, the input file must contain
+a single line of hexadecimal text. The data in any input file will be written
+the ROM in the order it appears in the input file, ie. the first bit in the input
+will be written to address 0.
+
+## Command Line Usage
+Once you have defined the environment, you can run OpenROM from the command line
+using a single configuration file written in Python. You can then run OpenROM by
+executing:
+```
+python3 $OPENRAM_HOME/../rom_compiler.py myconfig
+```
+You can see all of the options for the configuration file in
+$OPENRAM\_HOME/options.py
+
+To run macros, it is suggested to use, for example:
+```
+cd OpenRAM/macros/rom_configs
+make sky130_rom_1kbyte
+```
+
+* Common arguments:
+    * `-h` print all arguments
+    * `-t` specify technology (currently only sky130 is supported)
+    * `-v` increase verbosity of output
+    * `-n` don't run DRC/LVS
+    * `-d` don't purge /tmp directory contents
+
+
+## Configuration Files
+* Shares some configuration options with SRAM compiler.
+* Complete configuration options are in `$OPENRAM_HOME/options.py`
+* Some options can be specified on the command line as well
+    * Not recommended for replicating results
+* Example configuration file:
+    ```python
+
+    # Data word size
+    word_size = 2
+
+    # Enable LVS/DRC checking
+    check_lvsdrc = True
+
+    # Path to input data. Either binary file or hex.
+    rom_data = "data_1kbyte.bin"
+    # Format type of input data
+    data_type = "bin"
+
+    # Technology to use in $OPENRAM_TECH, currently only sky130 is supported
+    tech_name = "sky130"
+
+    # Output directory for the results
+    output_path = "temp"
+    # Output file base name
+    output_name = "rom_1kbyte"
+
+    # Only nominal process corner generation is currently supported
+    nominal_corner_only = True
+
+    # Add a supply ring to the generated layout
+    route_supplies = "ring"
+    ```
+
+
+## Output Files
+The output files are placed in the `output_dir` defined in the configuration
+file.
+
+The base name is specified by `output_name` and suffixes are added. Currently only layout and schematic files are generated.
+
+The final results files are:
+* GDS (.gds)
+* SPICE (.sp)
+* Log (.log)
+* Configuration (.py) for replication of creation

docs/source/basic_setup.md

@@ -1,7 +1,7 @@
 ### [Go Back](./index.md#table-of-contents)
 
 # Basic Setup
-This page shows the basic setup for using OpenRAM.
+This page shows the basic setup for using OpenRAM to generate an SRAM.
 
 
 
@@ -37,6 +37,12 @@ OpenRAM uses Anaconda by default, but you can turn this feature off by setting
 `use_conda = False` in your config file. Then, OpenRAM will use the tools you
 have installed on your system.
 
+You can also tell OpenRAM where Anaconda should be installed or which Anaconda
+setup it should use. You can set the `$CONDA_HOME` variable like this:
+```
+export CONDA_HOME="/path/to/conda/setup"
+```
+
 > **Note**: If you want to install Anaconda without running OpenRAM (for example
 > to run unit tests, which do not install Anaconda), you can run:
 > ```

docs/source/basic_usage.md

@@ -1,7 +1,7 @@
 ### [Go Back](./index.md#table-of-contents)
 
 # Basic Usage
-This page of the documentation explains the basic usage of OpenRAM.
+This page of the documentation explains the basic usage of OpenRAM's SRAM compiler. For usage of the ROM compiler see [here](./basic_rom_usage.md#go-back)
 
 
 

docs/source/index.md

@@ -9,8 +9,10 @@ navigate through the documentation.
 ## Table of Contents
 1. [OpenRAM Dependencies](#openram-dependencies)
 1. [Supported Technologies](#supported-technologies)
+1. [Online Playground](./OpenRAM.ipynb)
 1. [Basic Setup](./basic_setup.md#go-back)
-1. [Basic Usage](./basic_usage.md#go-back)
+1. [Basic SRAM Usage](./basic_usage.md#go-back)
+1. [Basic ROM Usage](./basic_rom_usage.md#go-back)
 1. [Python Library](./python_library.md#go-back)
 1. [Bitcells](./bitcells.md#go-back)
 1. [Architecture](./architecture.md#go-back)
@@ -108,10 +110,11 @@ Commercial tools (optional):
     * Michael Grimes
     * Jennifer Sowash
     * Jesse Cirimelli-Low
-    <img align="right" height="100" src="../assets/images/logos/vlsida.png">
+    <img align="right" height="100" src="../assets/images/logos/vlsida.png">https://www.youtube.com/watch?v=rd5j8mG24H4&t=0s
 * Many other past students:
     * Jeff Butera
     * Tom Golubev
     * Marcelo Sero
     * Seokjoong Kim
+    * Sage Walker
 

install_conda.sh

@@ -1,17 +1,17 @@
 #!/bin/bash
 CONDA_INSTALLER_URL="https://repo.anaconda.com/miniconda/Miniconda3-py38_22.11.1-1-Linux-x86_64.sh"
 CONDA_INSTALLER_FILE="miniconda_installer_py38.sh"
-CONDA_BASE="miniconda"
+CONDA_HOME="${CONDA_HOME:-miniconda}"
 
 TOOLS="klayout magic netgen ngspice trilinos xyce"
 
-# Install miniconda if not installed
-if [ ! -d "miniconda" ]
+# Install miniconda if not already installed
+if [[ ! -d "${CONDA_HOME}/bin" ]]
 then
     curl -s -o ${CONDA_INSTALLER_FILE} ${CONDA_INSTALLER_URL}
-    /bin/bash ${CONDA_INSTALLER_FILE} -b -p ${CONDA_BASE}
+    /bin/bash ${CONDA_INSTALLER_FILE} -b -p ${CONDA_HOME}
     rm ${CONDA_INSTALLER_FILE}
-    source ${CONDA_BASE}/bin/activate
+    source ${CONDA_HOME}/bin/activate
 
     # Prioritize channels to prevent version conflicts
     conda config --add channels conda-forge
@@ -28,7 +28,7 @@ then
 
     # Install required Python packages
     # (This step isn't required but used to prevent possible issues)
-    pip3 install -r requirements.txt
+    python3 -m pip install -r requirements.txt
 
     conda deactivate
 fi

macros/Makefile

@@ -6,6 +6,7 @@ include $(TOP_DIR)/openram.mk
 
 SKY130_PDK ?= $(PDK_ROOT)/sky130A
 
+OPENRAM_DIR = $(MACRO_DIR)
 OPENRAM_OPTS := $(OPENRAM_OPTS)
 # Define `OPENRAM_FULL` in your environment to run a full characterize
 ifeq ($(OPENRAM_FULL),)
@@ -40,7 +41,7 @@ configs:
 
 .PHONY: configs
 
-BROKEN := 
+BROKEN :=
 
 WORKING_SRAM_STAMPS=$(filter-out $(addsuffix .ok, $(BROKEN)), $(SRAM_STAMPS))
 WORKING_ROM_STAMPS=$(filter-out $(addsuffix .ok, $(BROKEN)), $(ROM_STAMPS))
@@ -50,7 +51,7 @@ SKY130_STAMPS=$(filter sky130%, $(WORKING_SRAM_STAMPS)) $(filter sky130%, $(WORK
 FREEPDK45_STAMPS=$(filter freepdk45%, $(WORKING_STAMPS)) $(filter freepdk45%, $(WORKING_ROM_STAMPS))
 SCN4M_SUBM_STAMPS=$(filter scn4m_subm%, $(WORKING_STAMPS)) $(filter scn4m_subm%, $(WORKING_ROM_STAMPS))
 
-all: | configs 
+all: | configs
 	@echo
 	@echo "Building following working configs"
 	@for S in $(WORKING_STAMPS); do echo " - $$S"; done
@@ -75,7 +76,7 @@ rom: $(WORKING_ROM_STAMPS)
 
 sram: $(WORKING_SRAM_STAMPS)
 .PHONY: sram
-	
+
 %.ok: sram_configs/%.py
 	@echo "Building $*"
 	@mkdir -p $*

macros/rom_configs/sky130_rom_1kbyte.py

@@ -10,7 +10,8 @@ word_size = 1
 
 check_lvsdrc = True
 
-rom_data = "macros/rom_configs/example_1kbyte.dat"
+rom_data = "rom_configs/example_1kbyte.bin"
+data_type = "bin"
 
 output_name = "rom_1kbyte"
 output_path = "macro/{output_name}".format(**locals())

macros/rom_configs/sky130_rom_common.py

@@ -1,4 +1,10 @@
-
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
 tech_name = "sky130"
 nominal_corner_only = True
 

technology/sky130/custom/replica_bitcell_array.py

@@ -0,0 +1,731 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from openram import debug
+from openram.base import vector
+from openram.base import contact
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram.tech import cell_properties as props
+from openram import OPTS
+from openram.modules import bitcell_base_array
+
+
+class replica_bitcell_array(bitcell_base_array):
+    """
+    Creates a bitcell array of cols x rows and then adds the replica
+    and dummy columns and rows.  Replica columns are on the left and
+    right, respectively and connected to the given bitcell ports.
+    Dummy are the outside columns/rows with WL and BL tied to gnd.
+    Requires a regular bitcell array, replica bitcell, and dummy
+    bitcell (BL/BR disconnected).
+    """
+    def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
+        super().__init__(name=name, rows=rows, cols=cols, column_offset=0)
+        debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
+                                                                                             rows,
+                                                                                             cols,
+                                                                                             rbl,
+                                                                                             left_rbl,
+                                                                                             right_rbl))
+        self.add_comment("rows: {0} cols: {1}".format(rows, cols))
+        self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
+
+        self.column_size = cols
+        self.row_size = rows
+        # This is how many RBLs are in all the arrays
+        if rbl:
+            self.rbl = rbl
+        else:
+            self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
+        # This specifies which RBL to put on the left or right
+        # by port number
+        # This could be an empty list
+        if left_rbl != None:
+            self.left_rbl = left_rbl
+        else:
+            self.left_rbl = [0]
+        # This could be an empty list
+        if right_rbl != None:
+            self.right_rbl = right_rbl
+        else:
+            self.right_rbl=[1] if len(self.all_ports) > 1 else []
+        self.rbls = self.left_rbl + self.right_rbl
+
+        debug.check(sum(self.rbl) == len(self.all_ports),
+                    "Invalid number of RBLs for port configuration.")
+        debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl),
+                    "Invalid number of RBLs for port configuration.")
+
+        # Two dummy rows plus replica even if we don't add the column
+        self.extra_rows = sum(self.rbl)
+        # Two dummy cols plus replica if we add the column
+        self.extra_cols = len(self.left_rbl) + len(self.right_rbl)
+
+        # If we aren't using row/col caps, then we need to use the bitcell
+        if not self.cell.end_caps:
+            self.extra_rows += 2
+            self.extra_cols += 2
+
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+        # We don't offset this because we need to align
+        # the replica bitcell in the control logic
+        # self.offset_all_coordinates()
+
+    def create_netlist(self):
+        """ Create and connect the netlist """
+        self.add_modules()
+        self.add_pins()
+        self.create_instances()
+
+    def add_modules(self):
+        """  Array and dummy/replica columns
+
+        d or D = dummy cell (caps to distinguish grouping)
+        r or R = replica cell (caps to distinguish grouping)
+        b or B = bitcell
+         replica columns 1
+         v              v
+        bdDDDDDDDDDDDDDDdb <- Dummy row
+        bdDDDDDDDDDDDDDDrb <- Dummy row
+        br--------------rb
+        br|   Array    |rb
+        br| row x col  |rb
+        br--------------rb
+        brDDDDDDDDDDDDDDdb <- Dummy row
+        bdDDDDDDDDDDDDDDdb <- Dummy row
+
+          ^^^^^^^^^^^^^^^
+          dummy rows cols x 1
+
+        ^ dummy columns  ^
+          1 x (rows + 4)
+        """
+        # Bitcell array
+        self.bitcell_array = factory.create(module_type="bitcell_array",
+                                            column_offset=1 + len(self.left_rbl),
+                                            cols=self.column_size,
+                                            rows=self.row_size)
+
+        # Replica bitlines
+        self.replica_columns = {}
+
+        for port in self.all_ports:
+            if port in self.left_rbl:
+                # We will always have self.rbl[0] rows of replica wordlines below
+                # the array.
+                # These go from the top (where the bitcell array starts ) down
+                replica_bit = self.rbl[0] - port
+                column_offset = self.rbl[0]
+
+            elif port in self.right_rbl:
+
+                # We will always have self.rbl[0] rows of replica wordlines below
+                # the array.
+                # These go from the bottom up
+                replica_bit = self.rbl[0] + self.row_size + port
+                column_offset = self.rbl[0] + self.column_size + 1
+            else:
+                continue
+
+            self.replica_columns[port] = factory.create(module_type="replica_column",
+                                                        rows=self.row_size,
+                                                        rbl=self.rbl,
+                                                        column_offset=column_offset,
+                                                        replica_bit=replica_bit)
+
+        # Dummy row
+        self.dummy_row = factory.create(module_type="dummy_array",
+                                            cols=self.column_size,
+                                            rows=1,
+                                            # dummy column + left replica column
+                                            column_offset=1 + len(self.left_rbl),
+                                            mirror=0)
+
+        # Dummy Row or Col Cap, depending on bitcell array properties
+        col_cap_module_type = ("col_cap_array" if self.cell.end_caps else "dummy_array")
+        self.col_cap_top = factory.create(module_type=col_cap_module_type,
+                                          cols=self.column_size,
+                                          rows=1,
+                                          # dummy column + left replica column(s)
+                                          column_offset=1 + len(self.left_rbl),
+                                          mirror=0,
+                                          location="top")
+
+        self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
+                                             cols=self.column_size,
+                                             rows=1,
+                                             # dummy column + left replica column(s)
+                                             column_offset=1 + len(self.left_rbl),
+                                             mirror=0,
+                                             location="bottom")
+
+        # Dummy Col or Row Cap, depending on bitcell array properties
+        row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array")
+
+        self.row_cap_left = factory.create(module_type=row_cap_module_type,
+                                            cols=1,
+                                            column_offset=0,
+                                            rows=self.row_size + self.extra_rows,
+                                            mirror=(self.rbl[0] + 1) % 2)
+
+        self.row_cap_right = factory.create(module_type=row_cap_module_type,
+                                            cols=1,
+                                            #   dummy column
+                                            # + left replica column(s)
+                                            # + bitcell columns
+                                            # + right replica column(s)
+                                            column_offset=1 + len(self.left_rbl) + self.column_size + self.rbl[0],
+                                            rows=self.row_size + self.extra_rows,
+                                            mirror=(self.rbl[0] + 1) %2)
+
+    def add_pins(self):
+
+        # Arrays are always:
+        # bitlines (column first then port order)
+        # word lines (row first then port order)
+        # dummy wordlines
+        # replica wordlines
+        # regular wordlines (bottom to top)
+        # # dummy bitlines
+        # replica bitlines (port order)
+        # regular bitlines (left to right port order)
+        #
+        # vdd
+        # gnd
+
+        self.add_bitline_pins()
+        self.add_wordline_pins()
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
+
+    def add_bitline_pins(self):
+        # The bit is which port the RBL is for
+        for bit in self.rbls:
+            for port in self.all_ports:
+                self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit))
+            for port in self.all_ports:
+                self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit))
+        # Make a flat list too
+        self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
+
+        self.bitline_names = self.bitcell_array.bitline_names
+        # Make a flat list too
+        self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
+
+        for port in self.left_rbl:
+            self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
+        self.add_pin_list(self.all_bitline_names, "INOUT")
+        for port in self.right_rbl:
+            self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
+
+    def add_wordline_pins(self):
+
+        # Wordlines to ground
+        self.gnd_wordline_names = []
+
+        for port in self.all_ports:
+            for bit in self.all_ports:
+                self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
+                if bit != port:
+                    self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
+
+        self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
+
+        self.wordline_names = self.bitcell_array.wordline_names
+        self.all_wordline_names = self.bitcell_array.all_wordline_names
+
+        # All wordlines including dummy and RBL
+        self.replica_array_wordline_names = []
+        self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
+        for bit in range(self.rbl[0]):
+            self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
+        self.replica_array_wordline_names.extend(self.all_wordline_names)
+        for bit in range(self.rbl[1]):
+            self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
+        self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
+
+        for port in range(self.rbl[0]):
+            self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
+        self.add_pin_list(self.all_wordline_names, "INPUT")
+        for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
+            self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
+
+    def create_instances(self):
+        """ Create the module instances used in this design """
+        self.supplies = ["vdd", "gnd"]
+
+        # Used for names/dimensions only
+        self.cell = factory.create(module_type=OPTS.bitcell)
+
+        # Main array
+        self.bitcell_array_inst=self.add_inst(name="bitcell_array",
+                                                mod=self.bitcell_array)
+        self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
+
+        # Replica columns
+        self.replica_col_insts = []
+        for port in self.all_ports:
+            if port in self.rbls:
+                self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
+                                                            mod=self.replica_columns[port]))
+                self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
+            else:
+                self.replica_col_insts.append(None)
+
+        # Dummy rows under the bitcell array (connected with with the replica cell wl)
+        self.dummy_row_replica_insts = []
+        # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
+        for port in self.all_ports:
+            self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
+                                                                mod=self.dummy_row))
+            self.connect_inst(self.all_bitline_names + [x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
+
+        # Top/bottom dummy rows or col caps
+        self.dummy_row_insts = []
+        self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
+                                                  mod=self.col_cap_bottom))
+        self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies)
+        self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
+                                                  mod=self.col_cap_top))
+        self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies)
+
+        # Left/right Dummy columns
+        self.dummy_col_insts = []
+        self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
+                                                    mod=self.row_cap_left))
+        self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.replica_array_wordline_names + self.supplies)
+        self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
+                                                    mod=self.row_cap_right))
+        self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.replica_array_wordline_names + self.supplies)
+
+    def create_layout(self):
+
+        # This creates space for the unused wordline connections as well as the
+        # row-based or column based power and ground lines.
+        self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
+        self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
+        self.unused_offset = vector(0.25, 0.25)
+
+        # This is a bitcell x bitcell offset to scale
+        self.bitcell_offset = vector(self.cell.width, self.cell.height)
+        self.col_end_offset = vector(self.cell.width, self.cell.height)
+        self.row_end_offset = vector(self.cell.width, self.cell.height)
+
+        # Everything is computed with the main array
+        self.bitcell_array_inst.place(offset=self.unused_offset)
+
+        self.add_replica_columns()
+
+        self.add_end_caps()
+
+        # Array was at (0, 0) but move everything so it is at the lower left
+        # We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
+        # Note that this doesn't include the row/col cap
+        array_offset = self.bitcell_offset.scale(1 + len(self.left_rbl), 1 + self.rbl[0])
+        self.translate_all(array_offset.scale(-1, -1))
+
+        # Add extra width on the left and right for the unused WLs
+
+        self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x
+        self.height = self.dummy_row_insts[1].uy()
+
+        self.add_layout_pins()
+
+        self.route_supplies()
+
+        self.route_unused_wordlines()
+
+        lower_left = self.find_lowest_coords()
+        upper_right = self.find_highest_coords()
+        self.width = upper_right.x - lower_left.x
+        self.height = upper_right.y - lower_left.y
+        self.translate_all(lower_left)
+
+        self.add_boundary()
+
+        self.DRC_LVS()
+
+    def get_main_array_top(self):
+        """ Return the top of the main bitcell array. """
+        return self.bitcell_array_inst.uy()
+
+    def get_main_array_bottom(self):
+        """ Return the bottom of the main bitcell array. """
+        return self.bitcell_array_inst.by()
+
+    def get_main_array_left(self):
+        """ Return the left of the main bitcell array. """
+        return self.bitcell_array_inst.lx()
+
+    def get_main_array_right(self):
+        """ Return the right of the main bitcell array. """
+        return self.bitcell_array_inst.rx()
+
+    def get_replica_top(self):
+        """ Return the top of all replica columns. """
+        return self.dummy_row_insts[0].by()
+
+    def get_replica_bottom(self):
+        """ Return the bottom of all replica columns. """
+        return self.dummy_row_insts[0].uy()
+
+    def get_replica_left(self):
+        """ Return the left of all replica columns. """
+        return self.dummy_col_insts[0].rx()
+
+    def get_replica_right(self):
+        """ Return the right of all replica columns. """
+        return self.dummy_col_insts[1].rx()
+
+    def get_column_offsets(self):
+        """
+        Return an array of the x offsets of all the regular bits
+        """
+        offsets = [x + self.bitcell_array_inst.lx() for x in self.bitcell_array.get_column_offsets()]
+        return offsets
+
+    def add_replica_columns(self):
+        """ Add replica columns on left and right of array """
+
+        # Grow from left to right, toward the array
+        for bit, port in enumerate(self.left_rbl):
+            offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - 1) + self.unused_offset
+            self.replica_col_insts[bit].place(offset)
+        # Grow to the right of the bitcell array, array outward
+        for bit, port in enumerate(self.right_rbl):
+            offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - 1)
+            self.replica_col_insts[self.rbl[0] + bit].place(offset)
+
+        # Replica dummy rows
+        # Add the dummy rows even if we aren't adding the replica column to this bitcell array
+        # These grow up, toward the array
+        for bit in range(self.rbl[0]):
+            dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2) + self.unused_offset
+            self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
+                                                    mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
+        # These grow up, away from the array
+        for bit in range(self.rbl[1]):
+            dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
+            self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
+                                                                  mirror="MX" if (self.row_size + bit) % 2 else "R0")
+
+    def add_end_caps(self):
+        """ Add dummy cells or end caps around the array """
+
+        # Far top dummy row (first row above array is NOT flipped if even number of rows)
+        flip_dummy = (self.row_size + self.rbl[1]) % 2
+        dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
+        self.dummy_row_insts[1].place(offset=dummy_row_offset,
+                                      mirror="MX" if flip_dummy else "R0")
+
+        # Far bottom dummy row (first row below array IS flipped)
+        flip_dummy = (self.rbl[0] + 1) % 2
+        dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - 1 + flip_dummy) + self.unused_offset
+        self.dummy_row_insts[0].place(offset=dummy_row_offset,
+                                      mirror="MX" if flip_dummy else "R0")
+        # Far left dummy col
+        # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
+        dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -self.rbl[0] - 1)  + self.unused_offset
+        self.dummy_col_insts[0].place(offset=dummy_col_offset)
+
+        # Far right dummy col
+        # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
+        dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
+        self.dummy_col_insts[1].place(offset=dummy_col_offset)
+
+    def add_layout_pins(self):
+        """ Add the layout pins """
+
+        # All wordlines
+        # Main array wl and bl/br
+        for pin_name in self.all_wordline_names:
+            pin_list = self.bitcell_array_inst.get_pins(pin_name)
+            for pin in pin_list:
+                self.add_layout_pin(text=pin_name,
+                                    layer=pin.layer,
+                                    offset=pin.ll().scale(0, 1),
+                                    width=self.width,
+                                    height=pin.height())
+
+        # Replica wordlines (go by the row instead of replica column because we may have to add a pin
+        # even though the column is in another local bitcell array)
+        for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
+            for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
+                if wl_name in self.gnd_wordline_names:
+                    continue
+                pin = inst.get_pin(pin_name)
+                self.add_layout_pin(text=wl_name,
+                                    layer=pin.layer,
+                                    offset=pin.ll().scale(0, 1),
+                                    width=self.width,
+                                    height=pin.height())
+
+        for pin_name in self.all_bitline_names:
+            pin_list = self.bitcell_array_inst.get_pins(pin_name)
+            for pin in pin_list:
+                self.add_layout_pin(text=pin_name,
+                                    layer=pin.layer,
+                                    offset=pin.ll().scale(1, 0),
+                                    width=pin.width(),
+                                    height=self.height)
+
+        # Replica bitlines
+        if len(self.rbls) > 0:
+            for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
+                pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
+                for (bl_name, pin_name) in zip(names, pin_names):
+                    pin = inst.get_pin(pin_name)
+                    self.add_layout_pin(text=bl_name,
+                                        layer=pin.layer,
+                                        offset=pin.ll().scale(1, 0),
+                                        width=pin.width(),
+                                        height=self.height)
+
+    def route_supplies(self):
+
+        if OPTS.bitcell == "pbitcell":
+            bitcell = factory.create(module_type="pbitcell")
+        else:
+            bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
+
+        vdd_dir = bitcell.vdd_dir
+        gnd_dir = bitcell.gnd_dir
+
+        # vdd/gnd are only connected in the perimeter cells
+        supply_insts = self.dummy_col_insts + self.dummy_row_insts
+
+        # For the wordlines
+        top_bot_mult = 1
+        left_right_mult = 1
+
+        # There are always vertical pins for the WLs on the left/right if we have unused wordlines
+        self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
+        self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)
+        # This needs to be big enough so that they aren't in the same supply routing grid
+        left_right_mult = 4
+
+        if gnd_dir == "V":
+            self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult)
+            self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult)
+            # This needs to be big enough so that they aren't in the same supply routing grid
+            top_bot_mult = 4
+
+        if vdd_dir == "V":
+            self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult)
+            self.bot_vdd_locs = self.route_side_pin("vdd", "bot", top_bot_mult)
+        elif vdd_dir == "H":
+            self.left_vdd_locs = self.route_side_pin("vdd", "left", left_right_mult)
+            self.right_vdd_locs = self.route_side_pin("vdd", "right", left_right_mult)
+        else:
+            debug.error("Invalid vdd direction {}".format(vdd_dir), -1)
+
+
+        for inst in supply_insts:
+            for pin in inst.get_pins("vdd"):
+                if vdd_dir == "V":
+                    self.connect_side_pin(pin, "top", self.top_vdd_locs[0].y)
+                    self.connect_side_pin(pin, "bot", self.bot_vdd_locs[0].y)
+                elif vdd_dir == "H":
+                    self.connect_side_pin(pin, "left", self.left_vdd_locs[0].x)
+                    self.connect_side_pin(pin, "right", self.right_vdd_locs[0].x)
+
+
+        for inst in supply_insts:
+            for pin in inst.get_pins("gnd"):
+                if gnd_dir == "V":
+                    self.connect_side_pin(pin, "top", self.top_gnd_locs[0].y)
+                    self.connect_side_pin(pin, "bot", self.bot_gnd_locs[0].y)
+                elif gnd_dir == "H":
+                    self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
+                    self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
+
+
+    def route_unused_wordlines(self):
+        """ Connect the unused RBL and dummy wordlines to gnd """
+        # This grounds all the dummy row word lines
+        for inst in self.dummy_row_insts:
+            for wl_name in self.col_cap_top.get_wordline_names():
+                pin = inst.get_pin(wl_name)
+                self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
+                self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
+
+        # Ground the unused replica wordlines
+        for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
+            for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
+                if wl_name in self.gnd_wordline_names:
+                    pin = inst.get_pin(pin_name)
+                    self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
+                    self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
+
+    def route_side_pin(self, name, side, offset_multiple=1):
+        """
+        Routes a vertical or horizontal pin on the side of the bbox.
+        The multiple specifies how many track offsets to be away from the side assuming
+        (0,0) (self.width, self.height)
+        """
+        if side in ["left", "right"]:
+            return self.route_vertical_side_pin(name, side, offset_multiple)
+        elif side in ["top", "bottom", "bot"]:
+            return self.route_horizontal_side_pin(name, side, offset_multiple)
+        else:
+            debug.error("Invalid side {}".format(side), -1)
+
+    def route_vertical_side_pin(self, name, side, offset_multiple=1):
+        """
+        Routes a vertical pin on the side of the bbox.
+        """
+        if side == "left":
+            bot_loc = vector(-offset_multiple * self.vertical_pitch, 0)
+            top_loc = vector(-offset_multiple * self.vertical_pitch, self.height)
+        elif side == "right":
+            bot_loc = vector(self.width + offset_multiple * self.vertical_pitch, 0)
+            top_loc = vector(self.width + offset_multiple * self.vertical_pitch, self.height)
+
+        layer = self.supply_stack[2]
+        top_via = contact(layer_stack=self.supply_stack,
+                          directions=("H", "H"))
+
+
+#        self.add_layout_pin_rect_ends(text=name,
+#                                      layer=layer,
+#                                      start=bot_loc,
+#                                      end=top_loc)
+        self.add_layout_pin_segment_center(text=name,
+                                           layer=layer,
+                                           start=bot_loc,
+                                           end=top_loc,
+                                           width=top_via.second_layer_width)
+
+        return (bot_loc, top_loc)
+
+    def route_horizontal_side_pin(self, name, side, offset_multiple=1):
+        """
+        Routes a horizontal pin on the side of the bbox.
+        """
+        if side in ["bottom", "bot"]:
+            left_loc = vector(0, -offset_multiple * self.horizontal_pitch)
+            right_loc = vector(self.width, -offset_multiple * self.horizontal_pitch)
+        elif side == "top":
+            left_loc = vector(0, self.height + offset_multiple * self.horizontal_pitch)
+            right_loc = vector(self.width, self.height + offset_multiple * self.horizontal_pitch)
+
+        layer = self.supply_stack[0]
+        side_via = contact(layer_stack=self.supply_stack,
+                           directions=("V", "V"))
+
+#        self.add_layout_pin_rect_ends(text=name,
+#                                      layer=layer,
+#                                      start=left_loc,
+#                                      end=right_loc)
+        self.add_layout_pin_segment_center(text=name,
+                                           layer=layer,
+                                           start=left_loc,
+                                           end=right_loc,
+                                           width=side_via.first_layer_height)
+
+        return (left_loc, right_loc)
+
+    def connect_side_pin(self, pin, side, offset):
+        """
+        Used to connect horizontal layers of pins to the left/right straps
+        locs provides the offsets of the pin strip end points.
+        """
+        if side in ["left", "right"]:
+            self.connect_vertical_side_pin(pin, side, offset)
+        elif side in ["top", "bottom", "bot"]:
+            self.connect_horizontal_side_pin(pin, side, offset)
+        else:
+            debug.error("Invalid side {}".format(side), -1)
+
+    def connect_horizontal_side_pin(self, pin, side, yoffset):
+        """
+        Used to connect vertical layers of pins to the top/bottom horizontal straps
+        """
+        cell_loc = pin.center()
+        pin_loc = vector(cell_loc.x, yoffset)
+
+        # Place the pins a track outside of the array
+        self.add_via_stack_center(offset=pin_loc,
+                                  from_layer=pin.layer,
+                                  to_layer=self.supply_stack[0],
+                                  directions=("V", "V"))
+
+        # Add a path to connect to the array
+        self.add_path(pin.layer, [cell_loc, pin_loc])
+
+
+    def connect_vertical_side_pin(self, pin, side, xoffset):
+        """
+        Used to connect vertical layers of pins to the top/bottom vertical straps
+        """
+        cell_loc = pin.center()
+        pin_loc = vector(xoffset, cell_loc.y)
+
+        # Place the pins a track outside of the array
+        self.add_via_stack_center(offset=pin_loc,
+                                  from_layer=pin.layer,
+                                  to_layer=self.supply_stack[2],
+                                  directions=("H", "H"))
+
+        # Add a path to connect to the array
+        self.add_path(pin.layer, [cell_loc, pin_loc])
+
+    def analytical_power(self, corner, load):
+        """Power of Bitcell array and bitline in nW."""
+        # Dynamic Power from Bitline
+        bl_wire = self.gen_bl_wire()
+        cell_load = 2 * bl_wire.return_input_cap()
+        bl_swing = OPTS.rbl_delay_percentage
+        freq = spice["default_event_frequency"]
+        bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
+
+        # Calculate the bitcell power which currently only includes leakage
+        cell_power = self.cell.analytical_power(corner, load)
+
+        # Leakage power grows with entire array and bitlines.
+        total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
+                                        cell_power.leakage * self.column_size * self.row_size)
+        return total_power
+
+
+    def gen_bl_wire(self):
+        if OPTS.netlist_only:
+            height = 0
+        else:
+            height = self.height
+        bl_pos = 0
+        bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
+        bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
+        return bl_wire
+
+    def graph_exclude_bits(self, targ_row=None, targ_col=None):
+        """
+        Excludes bits in column from being added to graph except target
+        """
+        self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
+
+    def graph_exclude_replica_col_bits(self):
+        """
+        Exclude all replica/dummy cells in the replica columns except the replica bit.
+        """
+
+        for port in self.left_rbl + self.right_rbl:
+            self.replica_columns[port].exclude_all_but_replica()
+
+    def get_cell_name(self, inst_name, row, col):
+        """
+        Gets the spice name of the target bitcell.
+        """
+        return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col)
+
+    def clear_exclude_bits(self):
+        """
+        Clears the bit exclusions
+        """
+        self.bitcell_array.init_graph_params()

technology/sky130/custom/sky130_capped_replica_bitcell_array.py

@@ -0,0 +1,209 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+
+from openram import debug
+from openram.base import vector
+from openram.base import contact
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram.tech import cell_properties as props
+from openram import OPTS
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
+
+
+class sky130_capped_replica_bitcell_array(sky130_bitcell_base_array):
+    """
+    Creates a replica bitcell array then adds the row and column caps to all
+    sides of a bitcell array.
+    """
+    def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
+        super().__init__(name, rows, cols, column_offset=0)
+        debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
+                                                                                             rows,
+                                                                                             cols,
+                                                                                             rbl,
+                                                                                             left_rbl,
+                                                                                             right_rbl))
+        self.add_comment("rows: {0} cols: {1}".format(rows, cols))
+        self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
+
+        self.rbl = rbl
+        self.left_rbl = left_rbl
+        self.right_rbl = right_rbl
+
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+    def create_netlist(self):
+        """ Create and connect the netlist """
+        self.add_modules()
+        self.add_pins()
+        self.create_instances()
+
+    def add_modules(self):
+        self.replica_bitcell_array = factory.create(module_type="replica_bitcell_array",
+                                                    cols=self.column_size,
+                                                    rows=self.row_size,
+                                                    rbl=self.rbl,
+                                                    left_rbl=self.left_rbl,
+                                                    right_rbl=self.right_rbl)
+
+    def add_pins(self):
+
+        # Arrays are always:
+        # bitlines (column first then port order)
+        # word lines (row first then port order)
+        # dummy wordlines
+        # replica wordlines
+        # regular wordlines (bottom to top)
+        # # dummy bitlines
+        # replica bitlines (port order)
+        # regular bitlines (left to right port order)
+        #
+        # vdd
+        # gnd
+
+        self.add_bitline_pins()
+        self.add_wordline_pins()
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
+
+    def add_bitline_pins(self):
+        self.bitline_names = self.replica_bitcell_array.bitline_names
+        self.all_bitline_names = self.replica_bitcell_array.all_bitline_names
+        self.rbl_bitline_names = self.replica_bitcell_array.rbl_bitline_names
+        self.all_rbl_bitline_names = self.replica_bitcell_array.all_rbl_bitline_names
+
+        self.bitline_pins = []
+
+        for port in self.left_rbl:
+            self.bitline_pins.extend(self.rbl_bitline_names[port])
+        self.bitline_pins.extend(self.all_bitline_names)
+        for port in self.right_rbl:
+            self.bitline_pins.extend(self.rbl_bitline_names[port])
+
+        self.add_pin_list(self.bitline_pins, "INOUT")
+
+    def add_wordline_pins(self):
+        # some of these are just included for compatibility with modules instantiating this module
+        self.rbl_wordline_names = self.replica_bitcell_array.rbl_wordline_names
+        self.all_rbl_wordline_names = self.replica_bitcell_array.all_rbl_wordline_names
+        self.wordline_names = self.replica_bitcell_array.wordline_names
+        self.all_wordline_names = self.replica_bitcell_array.all_wordline_names
+
+        self.wordline_pins = []
+
+        for port in range(self.rbl[0]):
+            self.wordline_pins.append(self.rbl_wordline_names[port][port])
+        self.wordline_pins.extend(self.all_wordline_names)
+        for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
+            self.wordline_pins.append(self.rbl_wordline_names[port][port])
+
+        self.add_pin_list(self.wordline_pins, "INPUT")
+
+    def create_instances(self):
+        """ Create the module instances used in this design """
+        self.supplies = ["vdd", "gnd"]
+
+        # Main array
+        self.replica_bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
+                                                      mod=self.replica_bitcell_array)
+        self.connect_inst(self.bitline_pins + self.wordline_pins + self.supplies)
+
+    def create_layout(self):
+
+        self.replica_bitcell_array_inst.place(offset=0)
+
+        self.width = self.replica_bitcell_array.width
+        self.height = self.replica_bitcell_array.height
+
+        for pin_name in self.bitline_pins + self.wordline_pins + self.supplies:
+            self.copy_layout_pin(self.replica_bitcell_array_inst, pin_name)
+
+        self.add_boundary()
+
+        self.DRC_LVS()
+
+    def get_main_array_top(self):
+        return self.replica_bitcell_array.get_main_array_top()
+
+    def get_main_array_bottom(self):
+        return self.replica_bitcell_array.get_main_array_bottom()
+
+    def get_main_array_left(self):
+        return self.replica_bitcell_array.get_main_array_left()
+
+    def get_main_array_right(self):
+        return self.replica_bitcell_array.get_main_array_right()
+
+    def get_replica_top(self):
+        return self.replica_bitcell_array.get_replica_top()
+
+    def get_replica_bottom(self):
+        return self.replica_bitcell_array.get_replica_bottom()
+
+    def get_replica_left(self):
+        return self.replica_bitcell_array.get_replica_left()
+
+    def get_replica_right(self):
+        return self.replica_bitcell_array.get_replica_right()
+
+
+    def get_column_offsets(self):
+        return self.replica_bitcell_array.get_column_offsets()
+
+    def analytical_power(self, corner, load):
+        """Power of Bitcell array and bitline in nW."""
+        # Dynamic Power from Bitline
+        bl_wire = self.gen_bl_wire()
+        cell_load = 2 * bl_wire.return_input_cap()
+        bl_swing = OPTS.rbl_delay_percentage
+        freq = spice["default_event_frequency"]
+        bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
+
+        # Calculate the bitcell power which currently only includes leakage
+        cell_power = self.cell.analytical_power(corner, load)
+
+        # Leakage power grows with entire array and bitlines.
+        total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
+                                        cell_power.leakage * self.column_size * self.row_size)
+        return total_power
+
+
+    def gen_bl_wire(self):
+        if OPTS.netlist_only:
+            height = 0
+        else:
+            height = self.height
+        bl_pos = 0
+        bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
+        bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
+        return bl_wire
+
+    def graph_exclude_bits(self, targ_row=None, targ_col=None):
+        """
+        Excludes bits in column from being added to graph except target
+        """
+        self.replica_bitcell_array.graph_exclude_bits(targ_row, targ_col)
+
+    def graph_exclude_replica_col_bits(self):
+        """
+        Exclude all replica/dummy cells in the replica columns except the replica bit.
+        """
+        self.replica_bitcell_array.graph_exclude_replica_col_bits()
+
+    def get_cell_name(self, inst_name, row, col):
+        """
+        Gets the spice name of the target bitcell.
+        """
+        return self.replica_bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.replica_bitcell_array_inst.name, row, col)
+
+    def clear_exclude_bits(self):
+        """
+        Clears the bit exclusions
+        """
+        self.replica_bitcell_array.clear_exclude_bits()

technology/sky130/custom/sky130_replica_bitcell_array.py

@@ -9,11 +9,11 @@ from math import sqrt
 from openram import debug
 from openram.base import vector
 from openram.base import round_to_grid
-from openram.modules import replica_bitcell_array
 from openram.tech import drc
 from openram.tech import array_row_multiple
 from openram.tech import array_col_multiple
 from openram import OPTS
+from .replica_bitcell_array import replica_bitcell_array
 from .sky130_bitcell_base_array import sky130_bitcell_base_array
 
 

technology/sky130/tech/tech.py

@@ -43,6 +43,7 @@ tech_modules["bitcell_2port"] = "bitcell_2port"
 
 tech_modules["bitcell_array"] = ["sky130_bitcell_array", "bitcell_array"]
 tech_modules["replica_bitcell_array"] = ["sky130_replica_bitcell_array", "replica_bitcell_array"]
+tech_modules["capped_replica_bitcell_array"] = ["sky130_capped_replica_bitcell_array", "capped_replica_bitcell_array"]
 tech_modules["dummy_array"] = ["sky130_dummy_array", "dummy_array"]
 
 tech_modules["replica_column"] = ["sky130_replica_column", "replica_column"]