luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,967 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

419 Commits

Author SHA1 Message Date
mrg b4ebbdd5df Require either device models or device library. Remove sky130 flag. 2020-10-23 14:07:26 -07:00
mrg 3d5c73709b Merge branch 'dev' into spmodels 2020-10-19 14:49:07 -07:00
mrg 7da3653ce5 Only output wmask to lib file in w or rw ports. 2020-10-16 16:59:51 -07:00
mrg 35c91168f7 Add load/slew scale option to config files 2020-10-16 13:52:36 -07:00
mrg ca2ce8b070 Default bitcell opt1 2020-10-12 17:08:32 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00
mrg 9fe6358569 Change .spinit to .spiceinit 2020-10-05 13:50:04 -07:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
mrg d315ff18e5 Add num_threads to options. PEP8 cleanup. 2020-10-01 08:07:03 -07:00
Matt Guthaus 2b475670f7 Check for failed result in functional simulation 2020-09-30 12:40:07 -07:00
mrg bca69b24e3 Optional number of functional cycles 2020-09-29 13:43:54 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
Hunter Nichols 500327d59b Fixed import in simulation and fixed names in functional 2020-09-04 02:24:18 -07:00
Hunter Nichols d027632bdc Moved majority of code duplicated between delay and functional to simulation 2020-09-02 14:22:18 -07:00
Hunter Nichols 42f2ff679e Removed dead code from delay and base module related to characterization 2020-08-27 15:40:41 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
mrg 15c8c200f3 Undo super() in measurement abstract class 2020-08-12 12:10:12 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Hunter Nichols c6f2edc20d Changed warning message for multiport analytical characterization. 2020-07-29 19:50:06 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
Hunter Nichols 206b02a7ee Merge branch 'dev' into characterizer_bug_fixes 2020-07-02 18:00:41 -07:00
Hunter Nichols fb34338fdf Removed debug statements 2020-07-02 18:00:02 -07:00
Hunter Nichols 119bd94689 Fixed warnings with single port characterization. Cleaned up some signal names. 2020-07-02 15:43:23 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00
Hunter Nichols 0464e2df5d Allowed bitline checks for multiple ports. 2020-06-30 01:37:52 -07:00
Hunter Nichols c289637dab Allowed sen's from multiple ports to be characterized 2020-06-29 23:18:31 -07:00
mrg 94c480911b ngspice raw save doesn't work with measures 2020-06-19 07:09:15 -07:00
mrg 403ea17039 PEP8 formatting 2020-06-18 14:55:01 -07:00
mrg 69f5621245 Save raw file from ngspice 2020-06-18 14:54:36 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
Aditi Sinha ef940e0dc5 Fixes for functional test of spare cols 2020-06-08 05:02:04 +00:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
jcirimel 575278998d write only used bitcells to top level in stim and pex output 2020-05-28 23:56:15 -07:00
jcirimel 0f9e38881c update stim for large pex layouts 2020-05-04 03:05:33 -07:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
mrg 4d6d6af0a1 Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
David Ratchkov c2419af2e2 Fix voltage_map names (these do not need to match pg_pin names) 2020-04-22 09:03:22 -07:00
David Ratchkov 5aea45ed69 - Fix switched disabled powers 2020-04-17 16:23:06 -07:00
David Ratchkov 123cc371be - Fix disabled power char 2020-04-17 16:09:58 -07:00
David Ratchkov 1f816e2823 - Characterize actual disabled power (read mode only) 
- Report rise/fall power individually
 2020-04-17 14:55:17 -07:00
David Ratchkov 7e36cd4828 - Write voltage_map and pg_pin 
- Remove 'when' condition on leakage power
- Remove 'clk*' from 'when' condition on internal_power on the same 'clk*' pin
 2020-04-17 13:45:57 -07:00
jcirimel afcb5174ac discrete dff tests working 2020-04-11 01:19:04 -07:00