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OpenRAM
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179 Commits

Author SHA1 Message Date
Michael Timothy Grimes e258199fa3 Removing we_b signal from write ports since it is redundant. 2018-10-04 09:31:04 -07:00
Michael Timothy Grimes a71486e22f Adding mutliport constants to design.py to reduce the need for copied code across multiple modules. 2018-09-28 00:11:39 -07:00
Michael Timothy Grimes 19d68f613e Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport. 2018-09-27 02:01:32 -07:00
Michael Timothy Grimes 1ca0154027 Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port. 2018-09-26 19:10:24 -07:00
Michael Timothy Grimes 648e57d195 Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes. 2018-09-26 14:53:55 -07:00
Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport 2018-09-25 20:00:25 -07:00
Michael Timothy Grimes 2641841e4c Making correction to replica bitline netlist for multiport 2018-09-20 15:21:22 -07:00
Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
Michael Timothy Grimes 43f5316eed Correcting format of replica_pbitcell. 2018-09-13 18:51:52 -07:00
Michael Timothy Grimes 332976dd73 s_en will be shared amongst the sense amps of different ports, so I'm removing the distinct s_en signals from several modules. 2018-09-13 18:46:43 -07:00
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Michael Timothy Grimes 7dfd37f79c Altering control logic for multiport. Netlist changes only. 2018-09-12 00:59:07 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 0cdd3b99bf Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport 2018-09-09 22:42:52 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes 252ae1effa add trailing 0 to web 2018-09-09 15:16:53 -07:00
Michael Timothy Grimes 68c00d7467 Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked. 2018-09-09 14:14:26 -07:00
Michael Timothy Grimes 1429b9ab1a Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming. 2018-09-09 14:00:51 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus 763f1e8dee Finish renaming replica bitcell and bitline pin names. 2018-09-04 14:03:15 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
Matt Guthaus 19c0e1638b Merge remote-tracking branch 'origin/multiport' into multiport 2018-09-04 10:47:55 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Michael Timothy Grimes af0756382f Merging changes and updating multiport syntax across several tests 2018-09-03 19:36:20 -07:00
Michael Timothy Grimes 1e5924d1b7 Adding multiported bank_sel pins 2018-09-03 17:35:00 -07:00
Michael Timothy Grimes d3441c7ba4 Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers 2018-09-03 17:31:12 -07:00
Michael Timothy Grimes f3cca7eea0 Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases. 2018-08-31 23:28:06 -07:00
Matt Guthaus c3bd54696f Merge branch 'dev' into multiport 2018-08-31 12:56:25 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Matt Guthaus 93a6247f26 Unrotate vias in delay chain 2018-08-29 17:21:53 -07:00
Matt Guthaus 27bb1d2ee7 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-29 15:34:45 -07:00
Matt Guthaus 5386b7a0f4 Initial refactor of signal and supply router classes. 2018-08-29 15:34:45 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only 
mode is enabled.
 2018-08-27 16:42:48 -07:00
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
Matt Guthaus 0daad338e4 All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
Matt Guthaus 87f539f3a8 Separate netlist/layout for flop and precharge array. 2018-08-27 10:54:21 -07:00
Matt Guthaus 138a70fc23 Add place_inst routine. 
Separate create netlist and layout in some modules.
 2018-08-27 10:42:40 -07:00
Michael Timothy Grimes 8c73a26daa Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly. 2018-08-26 14:37:17 -07:00
Michael Timothy Grimes 8e3dc332f3 changed control signal names in bank select to accommodate multi-port changes in bank 2018-08-19 00:00:42 -07:00
Michael Timothy Grimes 19ca0d6c2a Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port 2018-08-18 16:51:21 -07:00
Michael Timothy Grimes 0f8da1510e Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines. 2018-08-18 15:27:07 -07:00