 mrg
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99e252d6d4
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Update interface of RBL array
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2020-08-17 17:19:07 -07:00 |
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mrg
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b1e55f9072
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Add local bitcell array
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2020-08-17 15:14:42 -07:00 |
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mrg
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3a692e2846
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Comment updates
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2020-08-17 14:35:39 -07:00 |
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mrg
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60224b105f
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-08-17 14:20:34 -07:00 |
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mrg
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94bfad4113
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Horizontal gnd vias for unused array inputs
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2020-08-17 13:24:34 -07:00 |
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mrg
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bddb251a84
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More room for power contacts
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2020-08-17 12:32:44 -07:00 |
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mrg
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2c43d315db
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Revert gds readonly true
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2020-08-17 12:19:23 -07:00 |
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mrg
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35a1b00aa0
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Extra space for unused wl contacts
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2020-08-14 14:23:40 -07:00 |
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mrg
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170e3feb7d
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Fix order of replica wordlines and bitlines
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2020-08-14 14:14:49 -07:00 |
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mrg
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604e433e22
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Add readonly true for Magic scripts
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2020-08-14 10:40:31 -07:00 |
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mrg
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2ac04efe2e
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Must connect for replica cells other than top/bottom
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2020-08-13 16:26:19 -07:00 |
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mrg
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797c41c750
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Skip local bitcell array test
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2020-08-13 14:36:39 -07:00 |
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mrg
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50525e70f4
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Fix up to SRAM level with new replica bitcell array ports.
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2020-08-13 14:29:10 -07:00 |
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mrg
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8dbaa66aa5
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Merge branch 'super' into dev
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2020-08-12 14:25:13 -07:00 |
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mrg
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7ac4574e4f
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Use micron units for all simulation in sky130
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2020-08-12 13:54:55 -07:00 |
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mrg
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5fc6438553
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Fix pinv_dec super call
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2020-08-12 13:22:28 -07:00 |
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mrg
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15c8c200f3
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Undo super() in measurement abstract class
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2020-08-12 12:10:12 -07:00 |
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mrg
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55814a8f74
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Fix syntax errors in pgates for super edits
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2020-08-12 11:15:32 -07:00 |
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mrg
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0bec6f0439
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Fix SRAM to use simulation spice instead of LVS spice
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2020-08-12 10:41:21 -07:00 |
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mrg
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a55909930f
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Replace replcia_bitcell_array with new one in bank
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2020-08-12 09:49:14 -07:00 |
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mrg
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8e890c2014
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Replica bitcell with all the fixings
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2020-08-11 15:00:29 -07:00 |
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mrg
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30976df48f
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Change inheritance inits to use super
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2020-08-06 11:33:26 -07:00 |
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mrg
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eef97ff215
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Reabstracting bit and word line names.
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2020-08-06 11:17:49 -07:00 |
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mrg
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037de96989
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Merge branch 'dev' into wlbuffer
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2020-08-05 10:37:29 -07:00 |
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mrg
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528cb07635
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Merge branch 'dev' into wlbuffer
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2020-08-05 10:01:43 -07:00 |
|
 Bob Vanhoof
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9b8ef5ef57
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fix: generated pex file was not passed correctly to lib characterizer
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2020-08-03 10:16:12 +02:00 |
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Bob Vanhoof
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487bb6c6e9
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Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate
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2020-08-03 09:32:27 +02:00 |
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Bob Vanhoof
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dc55ededc1
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fix regession tests after calibre fix
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2020-07-31 12:51:34 +02:00 |
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mrg
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487027a9f2
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Fix pex file names
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2020-07-30 11:35:13 -07:00 |
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mrg
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8fa0065aaf
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Undo PR 82 changes -- broke unit test.
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2020-07-30 11:09:19 -07:00 |
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mrg
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a663d903c5
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-07-30 08:44:25 -07:00 |
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|
Matt Guthaus
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68387ec525
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Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
calibrepex: file copy fix
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2020-07-30 08:40:35 -07:00 |
|
 Hunter Nichols
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c6f2edc20d
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Changed warning message for multiport analytical characterization.
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2020-07-29 19:50:06 -07:00 |
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mrg
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64d61f4d56
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-29 12:16:41 -07:00 |
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mrg
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f23d2e36a7
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Don't obstruct control logic signals with dffs when no column mux.
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2020-07-29 10:31:18 -07:00 |
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mrg
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8a2fa90cd5
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Merge remote-tracking branch 'private/dev' into dev
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2020-07-29 10:11:26 -07:00 |
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mrg
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2fa561f98f
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Local bitcell array edits. Skip test by default.
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2020-07-29 10:08:13 -07:00 |
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Hunter Nichols
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b4dafac489
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Fixed issue with sen measurement not being added
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2020-07-27 23:55:03 -07:00 |
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mrg
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c260297366
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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Hunter Nichols
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9ea3616260
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Changed multiport characterization warning to better fit
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2020-07-27 15:47:02 -07:00 |
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Hunter Nichols
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c65178f86c
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Fixed issue with sen delay measure getting mixed with voltage checks
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2020-07-27 15:43:50 -07:00 |
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mrg
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69cab42676
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Add pbuf_dec gate
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2020-07-27 13:59:55 -07:00 |
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mrg
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26b01e37c6
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Fix pbuf test info
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2020-07-27 13:59:35 -07:00 |
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mrg
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2991534d3f
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Drafting local bitline stuff.
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2020-07-23 17:15:39 -07:00 |
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mrg
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e1967dc548
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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mrg
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317662d4aa
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-07-23 14:17:52 -07:00 |
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mrg
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b7c43ae674
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Fix 1w/1r example
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2020-07-23 14:17:13 -07:00 |
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mrg
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58846a4a25
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Limit wordline driver size. Place row addr dff near predecoders.
|
2020-07-20 17:57:38 -07:00 |
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mrg
|
0ed81aa923
|
Removed extraneous shift from added mirroring
|
2020-07-20 14:11:52 -07:00 |
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mrg
|
82bbacdfb5
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Add data bus gap to dynamically computed channel width
|
2020-07-20 13:43:57 -07:00 |
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