mrg 15c8c200f3 Undo super() in measurement abstract class		2020-08-12 12:10:12 -07:00
..
base	Change inheritance inits to use super	2020-08-06 11:33:26 -07:00
bitcells	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
characterizer	Undo super() in measurement abstract class	2020-08-12 12:10:12 -07:00
custom	Change s8 to sky130	2020-06-12 14:23:26 -07:00
datasheet	…
drc	…
example_configs	Fix 1w/1r example	2020-07-23 14:17:13 -07:00
gdsMill	…
modules	Change inheritance inits to use super	2020-08-06 11:33:26 -07:00
pgates	Fix syntax errors in pgates for super edits	2020-08-12 11:15:32 -07:00
router	…
sram	fix: generated pex file was not passed correctly to lib characterizer	2020-08-03 10:16:12 +02:00
tests	Fail unit test, but mention if LVS passes and DRC fails.	2020-06-30 16:22:44 -07:00
verify	Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate	2020-08-03 09:32:27 +02:00
Makefile	…
debug.py	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
gen_stimulus.py	…
globals.py	OpenRAM 1.1.6	2020-07-13 16:26:25 -07:00
openram.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
options.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
run_profile.sh	…
sram_factory.py	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
view_profile.py	…