mrg b1e55f9072 Add local bitcell array		2020-08-17 15:14:42 -07:00
..
base	Comment updates	2020-08-17 14:35:39 -07:00
bitcells	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
characterizer	Undo super() in measurement abstract class	2020-08-12 12:10:12 -07:00
custom	Change s8 to sky130	2020-06-12 14:23:26 -07:00
datasheet	Convert capital names to lower case for consistency	2019-08-21 13:45:34 -07:00
drc	PEP8 cleanup	2020-04-15 11:24:28 -07:00
example_configs	Fix 1w/1r example	2020-07-23 14:17:13 -07:00
gdsMill	added purposes to addText(), removed reference to specific tech from gdsMill	2020-02-19 16:26:52 -08:00
modules	Add local bitcell array	2020-08-17 15:14:42 -07:00
pgates	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-08-17 14:20:34 -07:00
router	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
sram	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-08-17 14:20:34 -07:00
tests	Add local bitcell array	2020-08-17 15:14:42 -07:00
verify	Revert gds readonly true	2020-08-17 12:19:23 -07:00
Makefile	Clean up Makefile for unit tests	2018-12-05 12:58:10 -08:00
debug.py	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
gen_stimulus.py	Fixed errors in extra rows characterization	2020-03-22 20:54:49 +00:00
globals.py	OpenRAM 1.1.6	2020-07-13 16:26:25 -07:00
openram.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
options.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
run_profile.sh	Convert pin map to a set for faster membership.	2019-04-01 15:45:44 -07:00
sram_factory.py	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
view_profile.py	Remove some flake8 errors/warnings.	2019-10-02 23:26:02 +00:00