luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,775 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

3252 Commits

Author SHA1 Message Date
mrg 93c6565b66 Add total failure of tests 2022-02-06 09:13:36 -08:00
mrg 8653b88206 Remove working temp directories 2022-02-06 09:06:20 -08:00
mrg d716a1c361 Don't stop on fail, archive all results, create .bad file on fail. 2022-02-05 07:50:06 -08:00
mrg e45e2f77c9 Rework regression to use docker. 2022-02-04 17:43:48 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg 63a6168b35 Merge branch 'dev' into klayout 2022-02-01 11:57:56 -08:00
mrg 06d391b3e3 Keep files during runs in Makefile 2022-01-13 14:41:24 -08:00
mrg 47690e0076 Merge branch 'dev' into docker 2021-12-29 14:42:32 -08:00
Jesse Cirimelli-Low 9e85d17fbe merge rbc lvs fixes 2021-12-23 21:21:10 -08:00
Jesse Cirimelli-Low c24c37a15a Merge branch 'dev' into lvs 2021-12-22 15:46:09 -08:00
mrg 34dd46c918 Exceptions for sky130 spare columns tests 2021-12-17 10:30:43 -08:00
mrg 82a1a8d87f Add exception for sky130 klayout LVS device output 2021-12-17 10:28:12 -08:00
mrg e460eff014 Add per tool lvs directories 2021-12-17 10:21:34 -08:00
mrg 4fa084f272 Add 1rw decoder test 2021-12-17 10:18:20 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg b94dd79125 Add labels to noconn in dummy bitcell for klayout lvs 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 7d7ffe76e0 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg c2e258709b Merge branch 'lvs' into dev 2021-11-22 11:33:12 -08:00
mrg ce40f2ae28 Allow non-unique matching for replica bitcell test. 2021-11-19 09:42:06 -08:00
Jesse Cirimelli-Low 2fb08af684 change col mux array poly routing from straight to 'L' 2021-11-17 17:22:03 -08:00
mrg edf3a701e4 Update options for arguments and readme. 2021-11-16 14:33:35 -08:00
mrg c102ed728c Move tests to test Makefile 2021-11-03 11:36:19 -07:00
mrg 9d49a369ea Initial docker setup 2021-11-02 11:10:59 -07:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
Jesse Cirimelli-Low 5792256db1 route spare col 2021-10-05 15:28:20 -07:00
samuelkcrow dfbf0ba6e1 Make git dependency visible and enforce it. 
resolves #87
 2021-10-04 14:43:14 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
Hunter Nichols 116f102ebf Fixed units in LIB files when cacti is selected as the model. Changed model data gather to only use the extended config. 2021-09-20 16:35:16 -07:00
mrg fe077e79d5 Use local temp DRC/LVS rules file for running. 2021-09-20 11:06:27 -07:00
mrg be92282150 Prefer open source over commercial 2021-09-20 11:02:40 -07:00
Hunter Nichols 11ff8713c5 Added shared config which is imported in all model configs. Shared config only hold model type for now. 2021-09-15 13:00:51 -07:00
mrg 11c5a644eb Remove previous breakpoint 2021-09-15 11:43:40 -07:00
mrg f3d1c6edc3 klayout DRC/LVS working 2021-09-15 11:33:39 -07:00
mrg 554b3f4ca7 Initial klayout DRC/LVS options 2021-09-07 16:51:16 -07:00
mrg 8d9a4cc27b PEP8 cleanup 2021-09-07 16:49:44 -07:00
mrg 03f87cd681 Add str function for sram_config 2021-09-07 16:49:31 -07:00
mrg 178f1197ca Use spare rows only for sky130 2021-09-07 16:49:11 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
mrg 83f2d14646 Fix unit test errors. 
Skip test 50s for now.
Change golden power values in xyce delay test.
 2021-09-07 14:07:22 -07:00
mrg b2389fe00f Change tolerance to 30% 2021-09-03 14:04:39 -07:00
mrg 3f031a90db Specify two stage wl_en driver to prevent race condition 2021-09-03 12:52:17 -07:00
Hunter Nichols 6b8d143073 Changed cacti RC delay function to better match cacti code in bitcell. Sense amp also has similar changed but is missing transconductance parameter. 2021-09-01 14:27:13 -07:00
Matt Guthaus ea04900acb
Merge pull request #121 from erendo/fix_verilog 
Fix Verilog
 2021-08-30 09:33:35 -07:00
erendo e9b370bf21 Fix write masks in Verilog 2021-08-29 00:31:32 +03:00
Hunter Nichols 680d7b5d93 Added special RC delay functions for the bitline and sense amp to match CACTI. Contains temporary parameters which need to be defined. 2021-08-25 16:12:05 -07:00
mrg 6f4d9f17af v1.1.18 2021-08-18 11:30:00 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
Hunter Nichols b3500982ca Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values. 2021-08-04 16:10:27 -07:00