mrg
11c5a644eb
Remove previous breakpoint
2021-09-15 11:43:40 -07:00
mrg
f3d1c6edc3
klayout DRC/LVS working
2021-09-15 11:33:39 -07:00
mrg
554b3f4ca7
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
mrg
8d9a4cc27b
PEP8 cleanup
2021-09-07 16:49:44 -07:00
mrg
03f87cd681
Add str function for sram_config
2021-09-07 16:49:31 -07:00
mrg
178f1197ca
Use spare rows only for sky130
2021-09-07 16:49:11 -07:00
mrg
83f2d14646
Fix unit test errors.
...
Skip test 50s for now.
Change golden power values in xyce delay test.
2021-09-07 14:07:22 -07:00
mrg
b2389fe00f
Change tolerance to 30%
2021-09-03 14:04:39 -07:00
mrg
3f031a90db
Specify two stage wl_en driver to prevent race condition
2021-09-03 12:52:17 -07:00
Matt Guthaus
ea04900acb
Merge pull request #121 from erendo/fix_verilog
...
Fix Verilog
2021-08-30 09:33:35 -07:00
erendo
e9b370bf21
Fix write masks in Verilog
2021-08-29 00:31:32 +03:00
mrg
6f4d9f17af
v1.1.18
2021-08-18 11:30:00 -07:00
biarmic
85955ce298
Fix addr flop in Verilog
2021-07-30 12:22:55 +03:00
mrg
e88f927e01
v1.1.17
2021-07-29 11:41:41 -07:00
mrg
aa0e221863
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2021-07-28 12:07:05 -07:00
mrg
90a4ad4d75
Update size of 30 config tests to 2 bits.
2021-07-28 12:05:31 -07:00
mrg
9694237dba
Flip MSB and LSB in lib file due to bug report
2021-07-28 08:12:33 -07:00
mrg
cce1305da3
Add technology parameter for library prefix during uniquification of GDS
2021-07-12 11:01:51 -07:00
mrg
bd64912977
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2021-07-09 12:31:48 -07:00
mrg
0d6d707315
Reset write_size to none when it is the same as data word width
2021-07-09 12:31:35 -07:00
Jesse Cirimelli-Low
1a7adcfdad
fix vnb and vpb routing in rba
2021-07-08 18:31:55 -07:00
Jesse Cirimelli-Low
b5daa51a6c
don't use hard coded purpose numbers
2021-07-01 17:31:01 -07:00
mrg
0464ec3f16
Skip 50 tests
2021-07-01 16:38:39 -07:00
mrg
55f09d00a4
Make replica_column sky130 friendly
2021-07-01 16:15:13 -07:00
mrg
879f945aa7
Add risc5 functional tests
2021-07-01 16:13:14 -07:00
Jesse Cirimelli-Low
8a0e3e5caf
Merge remote-tracking branch 'origin/dev' into dev
2021-07-01 15:22:29 -07:00
Jesse Cirimelli-Low
e280efda7b
don't copy pwell pin onto nwell
2021-07-01 15:19:59 -07:00
mrg
6be24d4c6c
Only 25 cycles
2021-07-01 12:50:20 -07:00
mrg
3d2b192682
Add conditional spare row/col to a couple unit tests
2021-07-01 12:49:30 -07:00
mrg
2711093442
Improve signal debug output
2021-07-01 12:47:17 -07:00
mrg
bbdc728ac5
Edits to functional simulation.
...
Use correct .TRAN with max timestep.
Seed functional sim with a 3 writes to start for more read addresses.
Move formatting code to simulation module to share.
2021-07-01 09:59:13 -07:00
Jesse Cirimelli-Low
278c40f4b7
Merge remote-tracking branch 'origin/dev' into dev
2021-06-30 05:24:23 -07:00
Jesse Cirimelli-Low
c9b3f4772e
fix bias correspondence points
2021-06-30 05:21:39 -07:00
mrg
4d49851396
Commit prefixGDS.py utility script
2021-06-29 17:06:43 -07:00
mrg
1ae68637ee
Utilize same format for output
2021-06-29 17:04:32 -07:00
mrg
91603e7e01
Fix spare+value notation error
2021-06-29 16:44:52 -07:00
mrg
f98368f766
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2021-06-29 15:47:59 -07:00
mrg
927de3a240
Debugging then disabling spare cols functional sim for now.
2021-06-29 15:47:53 -07:00
Jesse Cirimelli-Low
bcc956ecdc
merge dev
2021-06-29 11:42:32 -07:00
Jesse Cirimelli-Low
24e42d7cbe
refactor adding bias pins
2021-06-29 11:37:07 -07:00
mrg
833b7b98ab
Conditional import of array col/row multiple
2021-06-29 11:27:54 -07:00
mrg
4a9f361ab9
Save raw file by default for Xyce. Change command debug level.
2021-06-29 11:27:33 -07:00
mrg
ee1c2054d3
Add formatted debug output
2021-06-29 11:26:49 -07:00
mrg
930cc48e16
Add vdd/gnd for all bitcells
2021-06-29 09:37:30 -07:00
mrg
d2a1f6b654
Add num_rows/cols to sim
2021-06-29 09:35:33 -07:00
mrg
e223d434aa
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2021-06-29 09:34:13 -07:00
mrg
c4aec6af8c
Functional fixes.
...
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
2021-06-29 09:33:44 -07:00
Jesse Cirimelli-Low
c36f471333
add vnb/vpb lvs correspondence points
2021-06-29 02:31:56 -07:00
Jesse Cirimelli-Low
c599d8f62c
use special purposes with _get_gds_reader
2021-06-23 13:21:19 -07:00
mrg
958f5e45bb
Add extra dnwell spacing for single port
2021-06-23 11:14:58 -07:00
mrg
erendo
Jesse Cirimelli-Low