mrg d2a1f6b654 Add num_rows/cols to sim		2021-06-29 09:35:33 -07:00
..
base	add vnb/vpb lvs correspondence points	2021-06-29 02:31:56 -07:00
bitcells	Merged with dev, addressed conflict in port data	2021-06-21 17:23:32 -07:00
characterizer	Add num_rows/cols to sim	2021-06-29 09:35:33 -07:00
custom	Add noninverting logic function to custom decoder cells.	2021-04-22 16:13:54 -07:00
datasheet	Merge branch 'dev' into automated_analytical_model	2021-02-01 01:49:45 -08:00
drc	…
example_configs	Improve supply routing for ring and side pins	2021-05-28 10:58:30 -07:00
gdsMill	add vnb/vpb lvs correspondence points	2021-06-29 02:31:56 -07:00
model_configs	Added more configs for model and respective data.	2021-06-09 15:42:15 -07:00
modules	add vnb/vpb lvs correspondence points	2021-06-29 02:31:56 -07:00
pgates	uncomment test (passing)	2021-05-03 13:08:04 -07:00
router	Optional save supply pin centers for summer project	2021-06-23 10:03:38 -07:00
sram	Add extra dnwell spacing for single port	2021-06-23 11:14:58 -07:00
tests	Functional fixes.	2021-06-29 09:33:44 -07:00
verify	Fix comment	2021-06-13 14:18:55 -07:00
Makefile	Added more configs for model and respective data.	2021-06-09 15:42:15 -07:00
debug.py	Skywater changes.	2021-03-22 15:48:14 -07:00
gen_stimulus.py	…
globals.py	merge in dev	2021-05-28 14:06:23 -07:00
model_data_util.py	Added more data for regression models	2021-06-04 13:37:21 -07:00
openram.py	…
options.py	Finalize uniquify option for SRAMs	2021-06-22 16:13:33 -07:00
printGDS.py	…
processGDS.py	…
run_profile.sh	…
sram_factory.py	…
uniquifyGDS.py	Fix arg off by one error in uniquifyGDS	2021-06-22 16:18:03 -07:00
view_profile.py	…