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OpenRAM
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3176 Commits

Author SHA1 Message Date
Hunter Nichols 7fc4469b97 Converted input load to Farads for cacti module to fit other units. 2021-07-25 17:22:03 -07:00
Hunter Nichols 7dd9023ce4 Uncommented horowitz delay function. 2021-07-21 15:02:39 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
Hunter Nichols f6924b7cc2 Removed unusued inputs in drain_c function 2021-07-20 11:33:18 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
Hunter Nichols 2c9f755a73 Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
Hunter Nichols e9bea4f0b6 Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. 2021-07-12 13:02:22 -07:00
Hunter Nichols c1efa2de59 Added delay function for cacti, moved cacti related delay functions to hierarchy_spice, and trimmed the functions to remove irrelevant options for OpenRAM. 2021-07-07 13:22:30 -07:00
Hunter Nichols 8c48520de6 Added cacti-like model and adapted several functions from cacti into python. 2021-06-30 15:50:54 -07:00
Jesse Cirimelli-Low 278c40f4b7 Merge remote-tracking branch 'origin/dev' into dev 2021-06-30 05:24:23 -07:00
Jesse Cirimelli-Low c9b3f4772e fix bias correspondence points 2021-06-30 05:21:39 -07:00
mrg 4d49851396 Commit prefixGDS.py utility script 2021-06-29 17:06:43 -07:00
mrg 1ae68637ee Utilize same format for output 2021-06-29 17:04:32 -07:00
mrg 91603e7e01 Fix spare+value notation error 2021-06-29 16:44:52 -07:00
mrg f98368f766 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-29 15:47:59 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
Jesse Cirimelli-Low bcc956ecdc merge dev 2021-06-29 11:42:32 -07:00
Jesse Cirimelli-Low 24e42d7cbe refactor adding bias pins 2021-06-29 11:37:07 -07:00
mrg 833b7b98ab Conditional import of array col/row multiple 2021-06-29 11:27:54 -07:00
mrg 4a9f361ab9 Save raw file by default for Xyce. Change command debug level. 2021-06-29 11:27:33 -07:00
mrg ee1c2054d3 Add formatted debug output 2021-06-29 11:26:49 -07:00
mrg 930cc48e16 Add vdd/gnd for all bitcells 2021-06-29 09:37:30 -07:00
mrg d2a1f6b654 Add num_rows/cols to sim 2021-06-29 09:35:33 -07:00
mrg e223d434aa Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-29 09:34:13 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
Jesse Cirimelli-Low c36f471333 add vnb/vpb lvs correspondence points 2021-06-29 02:31:56 -07:00
Jesse Cirimelli-Low c599d8f62c use special purposes with _get_gds_reader 2021-06-23 13:21:19 -07:00
mrg 958f5e45bb Add extra dnwell spacing for single port 2021-06-23 11:14:58 -07:00
mrg ef733bb7aa Optional save supply pin centers for summer project 2021-06-23 10:03:38 -07:00
mrg 28c99dae4a Fix error with uniquify where root has a null 2021-06-22 16:39:10 -07:00
mrg b14992b213 Fix arg off by one error in uniquifyGDS 2021-06-22 16:18:03 -07:00
mrg 288f6cbb9f Rename prefixGDS to uniquifyGDS 2021-06-22 16:15:56 -07:00
mrg 04382a2271 Change number of arguments check in prefixGDS.py 2021-06-22 16:15:31 -07:00
mrg c69eb47a7a Finalize uniquify option for SRAMs 2021-06-22 16:13:33 -07:00
mrg 8095c72fc8 Debug prefixGDS.py utility script 2021-06-22 15:53:45 -07:00
mrg 8d71a98ce9 Make purposes argument to gdsMill. Create prefixGDS.py script. 2021-06-22 14:40:43 -07:00
Hunter Nichols a0921b4afc Merge branch 'dev' into automated_analytical_model 2021-06-22 01:39:38 -07:00
mrg 6e22771794 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-21 17:37:41 -07:00
mrg 58f8c66020 Fix disconnected spare_wen_0_0 2021-06-21 17:36:20 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 470317eaa4 Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules. 2021-06-21 17:20:25 -07:00
Hunter Nichols b408a871f9 Added direction information functions to 2-port bitcell modules 2021-06-21 17:19:15 -07:00
Jesse Cirimelli-Low 3502bec231 Merge remote-tracking branch 'origin/dev' into dev 2021-06-21 15:27:32 -07:00
mrg bb1ac1a38e Fix incorrect bus indexing of spare_wen. Convert internal signals to not use braces. 2021-06-21 15:23:08 -07:00
Jesse Cirimelli-Low 2760beae34 swap sky130 replica bitcell array power bias routing 2021-06-21 15:22:31 -07:00
mrg f3f19aeeeb Remove print statement 2021-06-21 15:16:36 -07:00
mrg 1ce5823df8 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-06-21 13:14:23 -07:00
mrg d53bc98ff5 Exit with error when spice models not found. Use ngspice if no simulator defined. 2021-06-21 13:14:08 -07:00
mrg af31027504 Fix error in 1 spare column Verilog 2021-06-21 13:13:53 -07:00