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OpenRAM
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4,514 Commits 5 Branches 63 Tags 79 MiB
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4514 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 6f4ee4ad2d pass modules by pointer not value 2023-08-09 14:06:35 -07:00
Jesse Cirimelli-Low 1aa04db2b6 add isntance naming templates 2023-08-03 16:24:24 -07:00
Jesse Cirimelli-Low 5e01bad2ee remove whitespace 2023-08-03 00:42:42 -07:00
Jesse Cirimelli-Low 61cfa55d75 fix replica col 2023-08-02 15:19:48 -07:00
Jesse Cirimelli-Low 5a764c9d43 remove MY mirroring in scmos 2023-08-01 19:05:55 -07:00
Jesse Cirimelli-Low d9d8cb2983 capped norbl scmos passing 2023-07-30 22:39:23 -07:00
Jesse Cirimelli-Low 6b12d442fa placement fixed 2023-07-30 22:01:30 -07:00
Jesse Cirimelli-Low 811eb43459 working on updated placemet code 2023-07-30 20:06:40 -07:00
Jesse Cirimelli-Low 4d6e836b20 revert bitcell test numbers 2023-07-29 17:43:09 -07:00
Jesse Cirimelli-Low c1acdadd81 remove print statements 2023-07-29 17:39:27 -07:00
Jesse Cirimelli-Low 6f9618f28a fix 2023-07-28 21:46:07 -07:00
Jesse Cirimelli-Low 8d8f243f99 scmos passing with odd sizses again 2023-07-27 18:39:18 -07:00
Jesse Cirimelli-Low a6e07aa364 cleanup 2023-07-26 18:53:39 -07:00
Jesse Cirimelli-Low dde4103d49 scmos pass 2023-07-26 18:40:37 -07:00
Jesse Cirimelli-Low 8a4b34dee1 proper tiling 2023-07-26 18:05:36 -07:00
Jesse Cirimelli-Low 4baec81f82 lvs failures 2023-07-26 02:51:31 -07:00
Jesse Cirimelli-Low 3fe44a3751 scmos array placing 2023-07-26 01:28:50 -07:00
Jesse Cirimelli-Low 4cf3ea91ff scmos array connecting 2023-07-25 15:02:06 -07:00
Jesse Cirimelli-Low cb21443e2d start of pattern refactor 2023-07-24 23:25:35 -07:00
vlsida-bot 7bd312faff Bump version: 1.2.19 -> 1.2.20 2023-07-18 00:59:02 +00:00
Sam Crow b1b6886bac Merge branch 'delay_ctrl' into dev 2023-07-17 16:05:57 -07:00
vlsida-bot 37b7de4653 Bump version: 1.2.18 -> 1.2.19 2023-07-11 00:25:28 +00:00
Sam Crow 89d8441108 Merge branch 'dev' into delay_ctrl 2023-07-10 14:31:26 -07:00
Samuel Crow 042a3ed14f
skip non-scmos delay control tests for now 2023-07-10 14:28:19 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Jesse Cirimelli-Low 513c7e9f71 update sram library commit 2023-07-10 13:12:13 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 468c972acb add optional guard band to delay chain sizing 2023-07-05 16:34:42 -07:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow b4a9784835 model vth delay swing delay 2023-07-05 12:17:48 -07:00
Sam Crow 5235cf9667 model p_en and wl_en delays in delay chain sizing 2023-07-03 17:02:11 -07:00
Sam Crow e1865083d7 incomplete work on improved delay modeling 2023-06-29 14:44:42 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
vlsida-bot 3620d56790 Bump version: 1.2.17 -> 1.2.18 2023-06-27 00:22:04 +00:00
Jesse Cirimelli-Low 14f8008c4f
Update index.md 
fix typo in index.md
 2023-06-26 15:37:42 -07:00
Sam Crow 28ea93bd0a convert 1-indexing to 0-indexing 2023-06-25 11:03:10 -07:00
Sam Crow 006eacd6d0 add pinout message output 2023-06-25 10:46:58 -07:00
vlsida-bot 3cd3a63419 Bump version: 1.2.16 -> 1.2.17 2023-06-24 16:55:37 +00:00
Eren Dogan 3ada5347eb Set shell in the Makefile 2023-06-23 20:59:28 -07:00
Eren Dogan 92c8770472 Fix publications 2023-06-23 20:38:49 -07:00
Sam Crow 8992c0fb68 first approximation of delay values 2023-06-20 16:22:03 -07:00
Sam Crow dbc9de6c9a implement relationship between delay pinouts 2023-06-14 17:10:07 -07:00
vlsida-bot 542df33878 Bump version: 1.2.15 -> 1.2.16 2023-06-14 23:14:13 +00:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia b9e61f346a Merge branch 'dev' into openROM-verilogoutput 
To test recent changes with ROM verilog output
 2023-06-14 12:26:07 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Sam Crow bf516a927d add skeleton for delay chain sizing 2023-06-13 13:44:32 -07:00
Sam Crow fee90283b9 add spacing and a comment 2023-06-12 16:56:44 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Sam Crow 96a1d400fa add single port bank test for norbl 2023-06-12 12:50:50 -07:00