 mrg
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67de7efd49
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Fix syntax error. No DRC/LVS in netlist only mode.
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2020-04-02 11:31:28 -07:00 |
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mrg
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9106e22b58
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Fix typo and syntax error.
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2020-04-02 10:37:21 -07:00 |
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mrg
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5349323acd
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PEP8 cleanup. DRC/LVS returns errors.
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2020-04-02 09:47:39 -07:00 |
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mrg
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0d6c84036d
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Adjust fudge factor for pin spacing.
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2020-04-02 09:47:13 -07:00 |
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mrg
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a3683c5898
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Separate pbitcell from hierarchical decoder
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2020-04-01 16:39:47 -07:00 |
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mrg
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a9d3548be1
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Refactor drc/lvs error output
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2020-04-01 15:54:06 -07:00 |
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mrg
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3b662026d2
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pnand3 constant hack for input separation
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2020-04-01 11:36:04 -07:00 |
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mrg
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7956b63d9f
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Add licon option to precharge
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2020-04-01 11:26:45 -07:00 |
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mrg
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3e41664db6
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Split precharge array to multiport and normal cell
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2020-04-01 11:26:31 -07:00 |
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mrg
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3074cf3b86
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Small format cleanup
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2020-04-01 11:15:29 -07:00 |
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mrg
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da334e47aa
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Separate pbitcell tests for precharge
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2020-04-01 11:14:50 -07:00 |
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mrg
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bc9cbe70a7
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Poly overlap doesn't convert to tx device
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2020-04-01 09:42:07 -07:00 |
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mrg
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d916322b74
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PEP8 updates
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2020-03-31 10:15:46 -07:00 |
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 Joey Kunzler
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b0d2946c80
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update to sense amp and write driver modules
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2020-03-30 20:00:32 -07:00 |
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mrg
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9907daaffa
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Min area only for multiple layers
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2020-03-26 13:05:02 -07:00 |
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mrg
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d2c97d75a7
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Add well contact and min area to power pin of precharge
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2020-03-26 11:49:32 -07:00 |
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mrg
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1e3734cb26
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Hack to fix pnand3 in freepdk45
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2020-03-26 11:08:53 -07:00 |
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mrg
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2f353187ba
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Skywater extraction mode for si unit scales
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2020-03-24 12:41:15 -07:00 |
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mrg
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1e2163c3a6
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Hack for pnand3 pin spacing
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2020-03-24 12:40:41 -07:00 |
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mrg
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e9d0db44fd
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Add li_stack contact to ptx and pgate if it exists.
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2020-03-23 16:55:38 -07:00 |
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mrg
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f491876a5a
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Move up B input in pnor2
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2020-03-23 13:49:08 -07:00 |
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mrg
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c15b4167b6
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Merge branch 'dev' into tech_migration
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2020-03-23 11:57:03 -07:00 |
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mrg
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f598a359d5
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Remove unused contact in pnor2
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2020-03-23 11:55:17 -07:00 |
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mrg
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717cbb0fe5
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Remove unused contact in pnand3
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2020-03-23 11:52:19 -07:00 |
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mrg
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0ee6963198
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Remove unused contact in pnand2
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2020-03-23 11:46:21 -07:00 |
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mrg
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f21791a904
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Add source drain contact options to ptx.
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2020-03-23 11:36:45 -07:00 |
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mrg
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9df99beb28
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Merge branch 'tech_migration' into dev
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2020-03-06 15:03:46 -08:00 |
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mrg
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fd7af7fc25
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Matt sucks skip test
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2020-03-06 15:03:31 -08:00 |
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mrg
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c5a1be703c
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Rotate via and PEP8 formatting
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2020-03-06 13:39:46 -08:00 |
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mrg
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23501c7b35
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Convert pnand+pinv to pand in decoders.
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2020-03-06 13:26:40 -08:00 |
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mrg
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1a2efd77ad
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Move rbl route away from bitcell array
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2020-03-06 09:48:20 -08:00 |
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mrg
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ee18f61cbf
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Route RBL to edge of bank.
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2020-03-06 09:03:52 -08:00 |
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mrg
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05f9e809b4
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PEP8 Formatting
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2020-03-05 16:27:35 -08:00 |
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mrg
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6506622dfb
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PEP8 Formatting
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2020-03-05 16:20:21 -08:00 |
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mrg
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5b23653369
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PEP8 Formatting
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2020-03-05 16:13:49 -08:00 |
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mrg
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ad98137cd4
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Merge branch 'dev' into tech_migration
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2020-03-05 14:18:06 -08:00 |
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mrg
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5312629702
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Remove jog in precharge. Jog is in port data
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2020-03-05 12:10:13 -08:00 |
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mrg
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9c1f0657dd
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PEP8 Formatting
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2020-03-05 11:58:36 -08:00 |
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mrg
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7adeef6c9e
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PEP8 Formatting
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2020-03-05 10:21:18 -08:00 |
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mrg
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287a31f598
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Precharge updates.
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
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2020-03-04 17:39:11 -08:00 |
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Joey Kunzler
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d7529ce526
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Vdd/gnd via stacks now use perferred directions, added cell property to override
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2020-03-04 17:05:19 -08:00 |
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mrg
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7ba9e09e12
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Incomplete precharge layer decoupling
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2020-03-04 22:23:05 +00:00 |
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mrg
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bb2305d56a
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PEP8 format fixes
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2020-02-28 18:24:39 +00:00 |
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mrg
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e1b97f58e1
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Add instance center location
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2020-02-28 18:24:09 +00:00 |
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mrg
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0b73979388
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Space inputs by M1 pitch
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2020-02-28 18:23:49 +00:00 |
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mrg
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073bd47b31
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Add source/drain/gate to structure
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2020-02-28 18:23:36 +00:00 |
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Matt Guthaus
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1617840ed3
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-02-27 08:50:19 -08:00 |
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 Olof Kindgren
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1d8f2a4ad6
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Update documentation
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2020-02-27 07:09:26 +01:00 |
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mrg
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266d68c395
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Generalize pgate width based on nwell/pwell contacts
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2020-02-25 17:09:07 +00:00 |
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Matt Guthaus
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0db0c5a3a9
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Update version to 1.1.4
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2020-02-25 08:09:08 -08:00 |
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