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OpenRAM
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375 Commits

Author SHA1 Message Date
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 54bd022efc Rework precharge route supply horizontally 2022-02-28 11:36:10 -08:00
mrg 53e4c45038 Add tap to nand in pnand 2022-02-23 09:30:31 -08:00
mrg ab3acb99da Fix offsets of new nwell/pwell contacts. 2022-02-11 12:09:42 -08:00
mrg 8fdd4966a7 Initial update of new psdm/nsdm implants 2022-02-02 09:36:05 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg 82a1a8d87f Add exception for sky130 klayout LVS device output 2021-12-17 10:28:12 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
Hunter Nichols b44f840814 Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values. 2021-08-01 19:25:54 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
Hunter Nichols 2c9f755a73 Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
Hunter Nichols e9bea4f0b6 Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. 2021-07-12 13:02:22 -07:00
Jesse Cirimelli-Low 31364e508e uncomment test (passing) 2021-05-03 13:08:04 -07:00
Jesse Cirimelli-Low 64b1946d6e sky130 singlebank drc clean 2021-05-03 12:52:07 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
Jesse Cirimelli-Low 6ea4bdc5e5 Merge branch 'dev' into laptop_checkpoint 2021-04-23 22:50:23 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 504f9aa892 Space tx in pinv_dec for power routing. 2021-01-08 11:34:58 -08:00
mrg 5c4389efa4 PEP8 fixes 2020-12-14 14:18:53 -08:00
mrg b4cab6ec57 Change mult to 1 always. 2020-12-01 15:20:24 -08:00
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
Hunter Nichols 9fd473ce70 Fixed issue with selection of column address when checking bitline names. 2020-11-20 01:11:08 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
Hunter Nichols 7a0f5e15db Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later. 2020-11-17 15:05:07 -08:00
mrg 493c9125f1 Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
mrg ce7be7466f Model as subckt for Magic too 2020-11-05 13:11:36 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg ae0f4fe682 Fix spice model bin parameter error 2020-10-28 10:39:54 -07:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg dcd29214bc Temp fix to use old device names during Calibre LVS. 2020-10-21 17:05:48 -07:00
mrg af40f3077c Change sky130 device cards to start with X 2020-10-15 13:56:10 -07:00
mrg ca2ce8b070 Default bitcell opt1 2020-10-12 17:08:32 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg 4a58f09c1c Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg f8146e3f69 Add decoder4x16 2020-10-02 15:52:09 -07:00
mrg 1fc4040607 Add pand4 and pnand4 2020-10-02 14:54:12 -07:00
mrg d65eb16513 Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00
mrg 6f06bb9dd5 Create sized RBL WL driver in port_address 2020-09-28 11:30:21 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
jcirimel 854d51c721 merge dev 2020-08-19 14:25:41 -07:00
mrg 60224b105f Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-17 14:20:34 -07:00
jcirimel e7c9914d77 decoder passing except for bus route 2020-08-13 16:20:39 -07:00
mrg 8dbaa66aa5 Merge branch 'super' into dev 2020-08-12 14:25:13 -07:00