 jcirimel
|
559dfbc7a6
|
single port bitcell array done
|
2020-09-16 05:46:14 -07:00 |
|
|
jcirimel
|
d22164bd48
|
single port progess
|
2020-09-14 18:11:38 -07:00 |
|
|
jcirimel
|
73443c8c95
|
Merge branch 'dev' into s8_single_port
|
2020-09-01 15:37:10 -07:00 |
|
 mrg
|
c1c1535210
|
Merge branch 'wlbuffer' into dev
|
2020-08-27 15:44:29 -07:00 |
|
|
mrg
|
11a82b7283
|
Fixed local bitcell array for single and dual port
|
2020-08-27 14:03:05 -07:00 |
|
|
mrg
|
da827d923f
|
Merge branch 'wlbuffer' into dev
|
2020-08-26 10:00:34 -07:00 |
|
|
mrg
|
c321d85595
|
Fix syntax error for dual port
|
2020-08-26 09:54:41 -07:00 |
|
|
mrg
|
e92337ddaf
|
Separate get_ and get_all for bitlines and wordlines
|
2020-08-25 17:08:48 -07:00 |
|
|
mrg
|
652f160aca
|
Merge branch 'wlbuffer' into dev
|
2020-08-25 15:50:08 -07:00 |
|
|
mrg
|
bdb18b4cab
|
Fix disconnected replica pins
|
2020-08-25 14:51:49 -07:00 |
|
|
mrg
|
bd8bf9afd8
|
Remove RBL label at top level of SRAM
|
2020-08-25 14:42:21 -07:00 |
|
|
mrg
|
856cce1e62
|
Add -json for detailed LVS output
|
2020-08-25 13:58:28 -07:00 |
|
|
mrg
|
28bd93bf51
|
Still working on array refactor
|
2020-08-25 11:50:44 -07:00 |
|
|
jcirimel
|
3f45d10797
|
fix column decoder
|
2020-08-25 02:46:16 -07:00 |
|
|
mrg
|
8dee5520e0
|
Standardize array names independent of bitcell
|
2020-08-21 13:44:35 -07:00 |
|
|
jcirimel
|
854d51c721
|
merge dev
|
2020-08-19 14:25:41 -07:00 |
|
|
mrg
|
b762580ee2
|
Skip global test for now
|
2020-08-19 11:36:21 -07:00 |
|
|
mrg
|
593a98e29a
|
Update local bitcell array for dual port
|
2020-08-19 11:35:55 -07:00 |
|
|
jcirimel
|
b7ef5496c4
|
decoder drc clean
|
2020-08-19 00:39:55 -07:00 |
|
|
mrg
|
e215c0e016
|
Drafting global bitcell array
|
2020-08-18 16:30:55 -07:00 |
|
|
mrg
|
5776788574
|
Order of wordlines and bitlines in bank
|
2020-08-18 16:30:38 -07:00 |
|
|
mrg
|
224e359208
|
Fix pin order for replica array
|
2020-08-18 15:59:05 -07:00 |
|
|
mrg
|
f58fc6579f
|
Rename local/global tests
|
2020-08-18 15:58:44 -07:00 |
|
|
mrg
|
e3e4bac922
|
Fix replica bitcell array for right only RBL
|
2020-08-18 15:47:52 -07:00 |
|
|
mrg
|
59d65c46c3
|
Fix bug in not adding RBLs in local bitcell array
|
2020-08-18 15:11:10 -07:00 |
|
|
mrg
|
2643a96f97
|
Order inputs wordline, bitline, supply
|
2020-08-18 14:29:36 -07:00 |
|
|
mrg
|
b288bba43e
|
Add global bitcell array test
|
2020-08-18 14:29:23 -07:00 |
|
|
mrg
|
f98fbb175b
|
Merge branch 'wlbuffer' into dev
|
2020-08-18 10:06:52 -07:00 |
|
|
mrg
|
e37a9234cc
|
Update replica column call to new refactor
|
2020-08-18 09:14:50 -07:00 |
|
|
mrg
|
17504a7da3
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-08-18 09:01:41 -07:00 |
|
|
mrg
|
bc974ff78e
|
Update replica column unit tests for new refactor
|
2020-08-18 08:56:24 -07:00 |
|
|
jcirimel
|
9cecf367ee
|
Merge branch 'dev' into pex
|
2020-08-17 17:49:41 -07:00 |
|
|
jcirimel
|
714b57d48e
|
Merge branch 'dev' into pex
|
2020-08-17 17:48:21 -07:00 |
|
|
mrg
|
99e252d6d4
|
Update interface of RBL array
|
2020-08-17 17:19:07 -07:00 |
|
|
mrg
|
b1e55f9072
|
Add local bitcell array
|
2020-08-17 15:14:42 -07:00 |
|
|
mrg
|
3a692e2846
|
Comment updates
|
2020-08-17 14:35:39 -07:00 |
|
|
mrg
|
60224b105f
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-08-17 14:20:34 -07:00 |
|
|
mrg
|
94bfad4113
|
Horizontal gnd vias for unused array inputs
|
2020-08-17 13:24:34 -07:00 |
|
|
mrg
|
bddb251a84
|
More room for power contacts
|
2020-08-17 12:32:44 -07:00 |
|
|
mrg
|
2c43d315db
|
Revert gds readonly true
|
2020-08-17 12:19:23 -07:00 |
|
|
mrg
|
35a1b00aa0
|
Extra space for unused wl contacts
|
2020-08-14 14:23:40 -07:00 |
|
|
mrg
|
170e3feb7d
|
Fix order of replica wordlines and bitlines
|
2020-08-14 14:14:49 -07:00 |
|
|
mrg
|
604e433e22
|
Add readonly true for Magic scripts
|
2020-08-14 10:40:31 -07:00 |
|
|
mrg
|
2ac04efe2e
|
Must connect for replica cells other than top/bottom
|
2020-08-13 16:26:19 -07:00 |
|
|
jcirimel
|
e7c9914d77
|
decoder passing except for bus route
|
2020-08-13 16:20:39 -07:00 |
|
|
mrg
|
797c41c750
|
Skip local bitcell array test
|
2020-08-13 14:36:39 -07:00 |
|
|
mrg
|
50525e70f4
|
Fix up to SRAM level with new replica bitcell array ports.
|
2020-08-13 14:29:10 -07:00 |
|
|
mrg
|
8dbaa66aa5
|
Merge branch 'super' into dev
|
2020-08-12 14:25:13 -07:00 |
|
|
mrg
|
7ac4574e4f
|
Use micron units for all simulation in sky130
|
2020-08-12 13:54:55 -07:00 |
|
|
mrg
|
5fc6438553
|
Fix pinv_dec super call
|
2020-08-12 13:22:28 -07:00 |
|