mrg e3e4bac922 Fix replica bitcell array for right only RBL		2020-08-18 15:47:52 -07:00
..
base	Comment updates	2020-08-17 14:35:39 -07:00
bitcells	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
characterizer	Undo super() in measurement abstract class	2020-08-12 12:10:12 -07:00
custom	Change s8 to sky130	2020-06-12 14:23:26 -07:00
datasheet	…
drc	…
example_configs	Fix 1w/1r example	2020-07-23 14:17:13 -07:00
gdsMill	…
modules	Fix replica bitcell array for right only RBL	2020-08-18 15:47:52 -07:00
pgates	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-08-17 14:20:34 -07:00
router	…
sram	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-08-17 14:20:34 -07:00
tests	Fix replica bitcell array for right only RBL	2020-08-18 15:47:52 -07:00
verify	Revert gds readonly true	2020-08-17 12:19:23 -07:00
Makefile	…
debug.py	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
gen_stimulus.py	…
globals.py	OpenRAM 1.1.6	2020-07-13 16:26:25 -07:00
openram.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
options.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
run_profile.sh	…
sram_factory.py	…
view_profile.py	…