mrg 17504a7da3 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

2020-08-18 09:01:41 -07:00

..

base

Merge branch 'dev' into pex

2020-08-17 17:49:41 -07:00

bitcells

update to new metal stack names

2020-07-31 05:27:19 -07:00

characterizer

Merge branch 'dev' into pex

2020-08-17 17:49:41 -07:00

custom

Change s8 to sky130

2020-06-12 14:23:26 -07:00

datasheet

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drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

Fix 1w/1r example

2020-07-23 14:17:13 -07:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

2020-08-18 09:01:41 -07:00

pgates

Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

2020-08-17 14:20:34 -07:00

router

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

sram

Merge branch 'dev' into pex

2020-08-17 17:49:41 -07:00

tests

Update interface of RBL array

2020-08-17 17:19:07 -07:00

verify

Merge branch 'dev' into pex

2020-08-17 17:49:41 -07:00

debug.py

DRC/LVS and errors fixes.

2020-06-30 07:16:05 -07:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

OpenRAM 1.1.6

2020-07-13 16:26:25 -07:00

Makefile

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openram.py

Add words_per_row and others in config file.

2020-07-13 12:37:56 -07:00

options.py

Add words_per_row and others in config file.

2020-07-13 12:37:56 -07:00

run_profile.sh

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sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

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